INFO:2026-10-22T06:45:36Z:root:pulling... From github.com:llvm/llvm-project * branch main -> FETCH_HEAD fb3ef8699477..28bb0cf8d076 main -> origin/main Switched to branch 'main' Your branch is behind 'origin/main' by 1 commit, and can be fast-forwarded. (use "git pull" to update your local branch) HEAD is now at 28bb0cf8d076 [mlir][complex] Fix exp special values for infinite real part (#232791) INFO:2026-10-22T06:45:40Z:root:syncing... Deleted branch merge (was b4cf4d00f204). Switched to a new branch 'merge' branch 'merge' set up to track 'origin/main'. [merge 04c6de3103ae] [gn build] Port ea4c43d796c4 1 file changed, 1 insertion(+) [gn build] Port ea4c43d796c4 -- https://github.com/llvm/llvm-project/commit/ea4c43d796c4 INFO:2026-10-22T06:45:41Z:root:building ninja: Entering directory `out/gn' [0/1] Regenerating ninja files [1/3] COPY ../../libcxxabi/include/__cxxabi_config.h include/c++/v1/__cxxabi_config.h [2/3] COPY ../../libcxxabi/include/cxxabi.h include/c++/v1/cxxabi.h [3/3] ACTION //libcxx/include:copy_headers(//llvm/utils/gn/build/toolchain:unix) INFO:2026-10-22T06:45:42Z:root:analyze skipping analyze because previous build was not green INFO:2026-10-22T06:45:42Z:root:testing INFO:2026-10-22T06:45:42Z:root:test check-clang ninja: Entering directory `out/gn' [0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix) llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld -- Testing: 27910 tests, 64 workers -- Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (1 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c0b29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c0b297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c0b29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c02733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c0278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c02733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c0271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c0b230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c0b230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c0b2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c0aec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c0aec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c0271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c0271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c0271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c0aec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (2 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b186701eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1866fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b18670262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe758733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe75878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe758733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe75871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b186697bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b186697a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b18667c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b18632be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b18632bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe75871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe75871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe75871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b18632ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (3 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647422aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647422a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647422ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0a0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0a00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0a0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0a0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564742240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564742240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647422258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564741ed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564741ed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0a0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0a00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0a00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564741ed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (4 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c059d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c059d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c059d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb321e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb321e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb321e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb321e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c0596dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c0596da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c059528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c05601e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c05601b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb321e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb321e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb321e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c05601a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (5 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp sle i32 %2, %3 # | %sle.i = zext i1 %4 to i32 # | ret i32 %sle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp ule i32 %2, %3 # | %sleu.i = zext i1 %4 to i32 # | ret i32 %sleu.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = sext i16 %1 to i32 # | %exths.i = sext i16 %1 to i32 # | ret i32 %exths.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = zext i16 %1 to i32 # | %exthz.i = zext i16 %1 to i32 # | ret i32 %exthz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = sext i8 %1 to i32 # | %extbs.i = sext i8 %1 to i32 # | ret i32 %extbs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = zext i8 %1 to i32 # | %extbz.i = zext i8 %1 to i32 # | ret i32 %extbz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | st # | ... # `---data was truncated (10240/15696) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556873ff7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556873ff4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556873ff862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ea3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ea3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ea3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ea3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556873f8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556873f8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556873f728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556873c21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556873c21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ea3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ea3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ea3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556873c21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (6 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df8be28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df8be25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df8be2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18acf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18acf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18acf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18aceed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df8bdbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df8bdbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df8bda38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df8ba52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df8ba52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18aceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18aceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18aceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df8ba52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (7 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fd5f3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fd5f3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fd5f4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7751e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7751ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7751e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7751e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fd5ed5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fd5ed5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fd5eba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fd5b69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fd5b69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7751e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7751e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7751e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fd5b69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (8 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563664530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056366452de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056366453162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99c3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99c395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99c3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99c38ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636644c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636644c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636644ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056366415ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056366415ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99c38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99c38ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99c38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056366415aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (9 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b029997eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b029994e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b02999862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef37533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef3758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef37533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef3751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b02992dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b02992da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0299128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0295c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0295c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef3751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef3751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef3751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0295c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (10 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644fdfdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644fdfdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644fdfdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cd021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cd02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cd021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cd0203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644fdf74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644fdf74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644fdf598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644fdc08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644fdc08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5cd0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cd02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cd02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644fdc08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (11 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be94c5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be94c57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be94c5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44b7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44b72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44b7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44b7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be94bf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be94bf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be94bd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be94884e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be94884b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44b7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44b72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44b72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be94884a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (12 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4673c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4673c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4673c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cd7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cd798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cd7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cd791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f46735dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f46735da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4673428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f466ff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f466ff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1cd791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cd791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cd791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f466ff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (13 of 27910) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.funcref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557686b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557686b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557686b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99cf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055576864ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055576864ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557686338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557682e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557682e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557682e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (14 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.a # | ... # `---data was truncated (10240/73947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557512505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557512502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055751250662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fbff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fbff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fbff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fbff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055751249bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055751249ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575124808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055751212fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055751212fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4fbff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fbff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fbff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055751212fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (15 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (16 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b67d33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b67d30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b67d3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f814441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81444725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f814441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8144403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b67cc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b67cc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b67cae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b6795de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b6795db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8144404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81444050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81444050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b6795da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (17 of 27910) ******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.annotated_flex = type { i64, i8, [0 x i8] } # | # | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8 # | @sink = external global i64, align 8 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_fam(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %2 = ptrtoint ptr %arraydecay to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %3 = icmp sgt i64 %flexible_array_member_size, -1 # | %4 = select i1 %3, i64 %flexible_array_member_size, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_subscript(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2 # | %2 = ptrtoint ptr %arrayidx to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 2 # | %3 = icmp sgt i64 %result, -1 # | %4 = and i1 true, %3 # | %5 = select i1 %4, i64 %result, i64 0 # | ret i64 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_addrof(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %2 = ptrtoint ptr %fam to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_fam() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %0 = icmp sgt i64 %flexible_array_member_size, -1 # | %1 = select i1 %0, i64 %flexible_array_member_size, i64 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_subscript() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %0 = icmp sgt i64 %result, -1 # | %1 = and i1 true, %0 # | %2 = select i1 %1, i64 %result, i64 0 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_addrof() #0 { # | entry: # | %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_fam(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %2 = icmp sgt i64 %flexible_array_member_size, -1 # | %3 = select i1 %2, i64 %flexible_array_member_size, i64 0 # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %2 = icmp sgt i64 %result, -1 # | %3 = and i1 true, %2 # | %4 = select i1 %3, i64 %result, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005559512c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559512c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559512ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f892c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f892c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f892c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f892c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055595125fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055595125fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559512448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555950ef3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555950ef3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f892c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f892c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f892c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555950ef3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (18 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (19 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/18641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6448b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6448b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6448b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4baa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4baa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4baa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4baa51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f64484dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f64484da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6448328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6444e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6444e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4baa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4baa51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4baa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6444e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (20 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fe0c80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fe0c7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fe0c8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6597449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6597449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6597431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fe0c16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fe0c16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fe0bfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fe08aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fe08aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6597432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65974330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fe08aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (21 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055681671aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556816717e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055681671b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd095133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd09518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd095133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd09511b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568166b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568166b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568166958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556816344e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556816344b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd09511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd09511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd09511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556816344a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (22 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (23 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555777cf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555777ceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555777cf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfc5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfc555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfc5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfc54ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555777c87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555777c87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555777c6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055577791be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055577791bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfc54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfc54ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfc54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055577791ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (24 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a60f758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a60f755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a60f75962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a62533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a6258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a62533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a6251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a60f6eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a60f6eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a60f6d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a60f382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a60f382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a6251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a6251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a6251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a60f382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (25 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639d0913eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639d0910e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639d091462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b0b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b0b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b0b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b0b203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639d08a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639d08a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639d088e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639d053de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639d053db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b0b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b0b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b0b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639d053da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (26 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x # | ... # `---data was truncated (10240/164783) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559e0bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559e0bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559e0bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a14649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a14649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a14631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559e0b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559e0b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559e0b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559e07e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559e07e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a14632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a146330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559e07e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (27 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (28 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556034b99eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556034b96e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556034b9a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a1b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a1b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a1b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a1b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556034b2fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556034b2fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556034b148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560347c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560347c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a1b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a1b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a1b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560347c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (29 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652e5397eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652e5394e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652e539862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35ac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35ac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35ac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35ac71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652e532dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652e532da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652e53128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652e4fc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652e4fc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35ac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35ac71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35ac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652e4fc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (30 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (31 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055953616deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055953616ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055953616e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d39649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d396a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d39649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d39631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559536103bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559536103a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595360e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559535d97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559535d97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d39632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d396330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d396330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559535d97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (32 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce40dceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce40dcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce40dcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f83449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f83449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f83431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce40d64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce40d64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce40d498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce409f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce409f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f83432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f834330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce409f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (33 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056145ef78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056145ef75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056145ef7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f252b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f252b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f252b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f252b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056145ef0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056145ef0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056145eef38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056145eba2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056145eba2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f252b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f252b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f252b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056145eba2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (34 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056363a4eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056363a4e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056363a4eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae0d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae0d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae0d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae0d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056363a480bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056363a480a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056363a4658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056363a114e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056363a114b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae0d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae0d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae0d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056363a114a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (35 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret bfloat %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x bfloat> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | !llvm.errno.tbaa = !{!6} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # | !6 = !{!7, !8, i64 0} # | !7 = !{!"__libc_errno", !8, i64 0} # | !8 = !{!"int", !9, i64 0} # | !9 = !{!"omnipotent char", !10, i64 0} # | !10 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558c255dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c255dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c255e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21acb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21acb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21acb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21acb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c25575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c25575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c2555a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c25209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c25209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21acb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21acb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21acb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c25209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (36 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (37 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e3f2c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e3f2c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e3f2c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae59249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae592a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae59249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae59231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e3f25dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e3f25da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e3f2428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e3eef1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e3eef1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae59232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae592330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae592330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e3eef1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (38 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055652dd60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055652dd5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055652dd6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29ecb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055652dcf6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055652dcf6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055652dcdb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055652d98ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055652d98ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055652d98aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (39 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (40 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643ec669eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643ec666e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643ec66a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff689733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff68978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff689733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff68971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643ec5ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643ec5ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643ec5e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643ec293e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643ec293b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff68971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff68971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff68971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643ec293a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (41 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055753e566eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055753e563e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055753e56762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f817db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f817db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f817db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f817db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055753e4fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055753e4fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055753e4e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055753e190e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055753e190b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f817db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f817db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f817db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055753e190a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (42 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # | #0 0x0000560948c19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560948c16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560948c1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b64533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b6458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b64533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b6451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560948bafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560948bafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560948b948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560948843e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560948843b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b6451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b6451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b6451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560948843a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (43 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056509028aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565090287e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056509028b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5167b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5167b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5167b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5167b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565090220bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565090220a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650902058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056508feb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056508feb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5167b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5167b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5167b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056508feb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (44 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056099e2a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056099e2a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056099e2a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9de5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9de5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9de5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9de5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056099e23dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056099e23da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056099e2228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056099ded1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056099ded1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9de5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9de5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9de5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056099ded1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (45 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602b7463eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602b7460e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602b746462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73e5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73e5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73e5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73e5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602b73f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602b73f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602b73de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602b708de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602b708db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73e5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73e5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73e5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602b708da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (46 of 27910) ******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type { ptr, ptr, %struct.A } # | %struct.A = type { i32 } # | # | $_ZTV1B = comdat any # | # | $_ZTI1B = comdat any # | # | $_ZTS1B = comdat any # | # | $_ZTI1A = comdat any # | # | $_ZTS1A = comdat any # | # | @y = local_unnamed_addr global i8 2, align 1 # | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8 # | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8 # | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8 # | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr] # | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1 # | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8 # | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr] # | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000055f4186c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4186c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4186c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f215261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21526725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f215261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2152603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f41865bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f41865ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4186408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4182efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4182efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2152604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21526050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21526050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4182efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (47 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd273a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd273a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd273aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe934c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe934ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe934c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe934c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd2733fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd2733fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd273248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd26fd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd26fd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe934c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe934c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe934c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd26fd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (48 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056390ec5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056390ec57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056390ec5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8812c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8812ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8812c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8812c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056390ebf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056390ebf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056390ebd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056390e884e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056390e884b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8812c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8812c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8812c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056390e884a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (49 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask. # | ... # `---data was truncated (10240/28162) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055710ab7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055710ab77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055710ab7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2cb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2cb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2cb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2cb631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055710ab10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055710ab10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055710aaf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055710a7a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055710a7a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2cb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2cb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2cb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055710a7a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (50 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a45d5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a45d57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a45d5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f350bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f350bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f350bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f350bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a45cf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a45cf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a45cd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a45984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a45984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f350bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f350bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f350bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a45984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (51 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmov_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.and.z.nxv16i1( %0, %1, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c598091eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c59808ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c59809262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd442933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd44298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd442933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd44291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c598027bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c598027a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c59800c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c597cbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c597cbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd44291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd44291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd44291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c597cbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (52 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcf76aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcf76a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcf76ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f034981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03498725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f034981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0349803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcf7640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcf7640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcf76258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcf72d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcf72d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0349804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03498050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03498050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcf72d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (53 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602a1658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602a1655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602a165962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c8c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c8c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c8c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c8c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602a15eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602a15eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602a15d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602a1282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602a1282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c8c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c8c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c8c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602a1282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (54 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/12656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647ab29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647ab297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647ab29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbb1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbb158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbb1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbb151b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647ab230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647ab230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647ab2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647aaec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647aaec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbb151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbb151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbb151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647aaec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (55 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6cb81eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6cb81be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6cb81f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a38a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a38aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a38a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a38a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6cb7b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6cb7b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6cb7998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e6cb448e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e6cb448b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a38a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a38a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a38a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6cb448a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (56 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bee100deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bee100ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bee100e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a1a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a1a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a1a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a1a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bee0fa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bee0fa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bee0f888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bee0c37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bee0c37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a1a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a1a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a1a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bee0c37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (57 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b13bebeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b13bebbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b13bebf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf09933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf0998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf09933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf0991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b13be54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b13be54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b13be398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b13bae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b13bae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf0991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf0991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf0991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b13bae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (58 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | # | ... # `---data was truncated (10240/19083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056512b23eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056512b23be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056512b23f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3912c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3912ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3912c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3912c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056512b1d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056512b1d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056512b1b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056512ae68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056512ae68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3912c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3912c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3912c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056512ae68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (59 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f2246feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f2246ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f2247062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b7e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b7e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b7e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b7e831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f22405bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f22405a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f223ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f22099e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f22099b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b7e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b7e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b7e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f22099a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (60 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.a # | ... # `---data was truncated (10240/63518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d71eda7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d71eda4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d71eda862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b6fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b6fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b6fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b6fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d71ed3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d71ed3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d71ed228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d71e9d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d71e9d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b6fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b6fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b6fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d71e9d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (61 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vsqaddb_u8() #0 { # | entry: # | %__p0.addr.i = alloca i8, align 1 # | %__p1.addr.i = alloca i8, align 1 # | %__ret.i = alloca i8, align 1 # | %ref.tmp.i = alloca i8, align 1 # | store i8 1, ptr %__p0.addr.i, align 1 # | store i8 -1, ptr %__p1.addr.i, align 1 # | %0 = load i8, ptr %__p0.addr.i, align 1 # | %1 = load i8, ptr %__p1.addr.i, align 1 # | %2 = insertelement <8 x i8> poison, i8 %0, i64 0 # | %3 = insertelement <8 x i8> poison, i8 %1, i64 0 # | %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3) # | %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0 # | store i8 %4, ptr %ref.tmp.i, align 1 # | %5 = load i8, ptr %ref.tmp.i, align 1 # | store i8 %5, ptr %__ret.i, align 1 # | %6 = load i8, ptr %__ret.i, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vsqaddh_u16() #0 { # | entry: # | %__p0.addr.i = alloca i16, align 2 # | %__p1.addr.i = alloca i16, align 2 # | %__ret.i = alloca i16, align 2 # | %ref.tmp.i = alloca i16, align 2 # | store i16 1, ptr %__p0.addr.i, align 2 # | store i16 -1, ptr %__p1.addr.i, align 2 # | %0 = load i16, ptr %__p0.addr.i, align 2 # | %1 = load i16, ptr %__p1.addr.i, align 2 # | %2 = insertelement <4 x i16> poison, i16 %0, i64 0 # | %3 = insertelement <4 x i16> poison, i16 %1, i64 0 # | %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3) # | %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0 # | store i16 %4, ptr %ref.tmp.i, align 2 # | %5 = load i16, ptr %ref.tmp.i, align 2 # | store i16 %5, ptr %__ret.i, align 2 # | %6 = load i16, ptr %__ret.i, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vsqadds_u32() #0 { # | entry: # | %__p0.addr.i = alloca i32, align 4 # | %__p1.addr.i = alloca i32, align 4 # | %__ret.i = alloca i32, align 4 # | %ref.tmp.i = alloca i32, align 4 # | store i32 1, ptr %__p0.addr.i, align 4 # | store i32 -1, ptr %__p1.addr.i, align 4 # | %0 = load i32, ptr %__p0.addr.i, align 4 # | %1 = load i32, ptr %__p1.addr.i, align 4 # | %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1) # | store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4 # | %2 = load i32, ptr %ref.tmp.i, align 4 # | store i32 %2, ptr %__ret.i, align 4 # | %3 = load i32, ptr %__ret.i, align 4 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vsqaddd_u64() #0 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i64, align 8 # | %ref.tmp.i = alloca i64, align 8 # | store i64 1, ptr %__p0.addr.i, align 8 # | store i64 -1, ptr %__p1.addr.i, align 8 # | %0 = load i64, ptr %__p0.addr.i, align 8 # | %1 = load i64, ptr %__p1.addr.i, align 8 # | %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1) # | store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8 # | %2 = load i64, ptr %ref.tmp.i, align 8 # | store i64 %2, ptr %__ret.i, align 8 # | %3 = load i64, ptr %__ret.i, align 8 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # | #0 0x00005563d6af4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563d6af1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563d6af562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf9e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf9e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf9e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf9e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563d6a8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563d6a8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563d6a6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563d671ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563d671eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf9e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf9e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf9e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563d671ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (62 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616570cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616570cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616570ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc632649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6326a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc632649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc632631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561657063bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561657063a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616570488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561656cf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561656cf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc632632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6326330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6326330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561656cf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (63 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8727a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d87279fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8727a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feccb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feccb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feccb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feccb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d872738bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d872738a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d87271d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8723cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8723ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feccb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feccb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feccb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8723cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (64 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055683a8fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055683a8fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055683a8fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1260d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1260d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1260d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1260d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055683a893bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055683a893a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055683a8788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055683a527e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055683a527b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1260d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1260d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1260d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055683a527a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (65 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (66 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e52733eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e52730e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e5273462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe13a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe13a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe13a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe13a631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e526c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e526c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e526ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e5235de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e5235db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe13a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe13a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe13a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e5235da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (67 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556406d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556406d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556406d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7667533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f766758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7667533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f766751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055564066bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055564066ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556406508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556402ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556402ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f766751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f766751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f766751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556402ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (68 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b74eccaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b74ecc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b74eccb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc095f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc095f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc095f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc095f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b74ec60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b74ec60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b74ec458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b74e8f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b74e8f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc095f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc095f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc095f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b74e8f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (69 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623f9220eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623f921de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623f922162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd0f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd0f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd0f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd0f8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623f91b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623f91b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623f919b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623f8e4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623f8e4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd0f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd0f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd0f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623f8e4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (70 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a7740beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a77408e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a7740c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd18621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1862725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd18621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd186203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a773a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a773a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a773868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a77035e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a77035b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd186204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1862050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1862050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a77035a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (71 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643714a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643714a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643714a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbb5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbb5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbb5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbb5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056437143abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056437143aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056437141f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643710cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643710ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbb5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbb5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbb5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643710cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (72 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2afb3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2afb39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2afb3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa10f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa10f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa10f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa10f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2afad2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2afad2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2afab78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2af766e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2af766b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa10f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa10f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa10f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2af766a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (73 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (74 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e40a9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e40a9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e40a9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1440333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f144038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1440333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f144031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e40a33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e40a33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e40a188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e406c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e406c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f144031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f144031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f144031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e406c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (75 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (76 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i) # | %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8> # | store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %6, ptr %__ret.i, align 8 # | %7 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %acc, ptr %acc.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %acc.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float> # | %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float> # | %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float> # | %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i) # | %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8> # | store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %lhs.addr = alloca <8 x half>, align 16 # | %rhs.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %lhs, ptr %lhs.addr, align 16 # | store <8 x half> %rhs, ptr %rhs.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %lhs.addr, align 16 # | %2 = load <8 x half>, ptr %rhs.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half> # | %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half> # | %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half> # | %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i) # | %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8> # | store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %lhs.addr = alloca <4 x float>, align 16 # | %rhs.addr = alloca <4 x float>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <4 x float> %lhs, ptr %lhs.addr, align 16 # | store <4 x float> %rhs, ptr %rhs.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <4 x float>, ptr %lhs.addr, align 16 # | %2 = load <4 x float>, ptr %rhs.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float> # | %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float> # | %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float> # | %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i) # | %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8> # | store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <2 x double>, align 16 # | %lhs.addr = alloca <2 x double>, align 16 # | %rhs.addr = alloca <2 x double>, align 16 # | store <2 x double> %acc, ptr %acc.addr, align 16 # | store <2 x double> %lhs, ptr %lhs.addr, align 16 # | store <2 x double> %rhs, ptr %rhs.addr, align 16 # | %0 = load <2 x double>, ptr %acc.addr, align 16 # | %1 = load <2 x double>, ptr %lhs.addr, align 16 # | %2 = load <2 x double>, ptr %rhs.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double> # | %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double> # | %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double> # | %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i) # | %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8> # | store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16 # | %6 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %6, ptr %__ret.i, align 16 # | %7 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v # | ... # `---data was truncated (10240/166298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # | #0 0x0000559031d54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559031d51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559031d5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe1e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe1e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe1e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe1e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559031ceabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559031ceaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559031ccf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055903197ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055903197eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe1e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe1e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe1e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055903197ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (77 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (78 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f91047eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f91044e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f9104862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09b8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09b80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09b8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09b8031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f90fddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f90fdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f90fc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f90c71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f90c71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09b8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09b80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09b80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f90c71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (79 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void # | ... # `---data was truncated (10240/179328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ef97dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ef97d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ef97dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b4f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b4f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b4f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b4f631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ef9772bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ef9772a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ef97578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ef9406e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ef9406b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b4f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b4f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b4f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ef9406a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (80 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649d3939eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649d3936e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649d393a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64cc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64cc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64cc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64cc831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649d38cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649d38cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649d38b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649d3563e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649d3563b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f64cc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64cc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64cc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649d3563a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (81 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607990f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607990efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607990f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f849a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f849a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f849a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f849a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560799088bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560799088a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056079906d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560798d1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560798d1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f849a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f849a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f849a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560798d1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (82 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642b6e5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642b6e5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642b6e5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fe3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fe338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fe3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fe331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642b6df3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642b6df3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642b6dd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642b6a87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642b6a87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fe331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fe331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fe331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642b6a87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (83 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (84 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055869911feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055869911ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055869912062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d2e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d2e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d2e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d2e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586990b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586990b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055869909a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558698d49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558698d49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d2e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d2e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d2e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558698d49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (85 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, pt # | ... # `---data was truncated (10240/174721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dc3746eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dc3743e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dc374762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a4b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a4b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a4b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a4b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dc36dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dc36dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dc36c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dc3370e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dc3370b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a4b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a4b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a4b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dc3370a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm64-lanes.c (86 of 27910) ******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %src, ptr %src.addr, align 8 # | %0 = load <2 x float>, ptr %src.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vdups_lane = extractelement <2 x float> %1, i32 0 # | store float %vdups_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %src, ptr %src.addr, align 8 # | %0 = load <1 x double>, ptr %src.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vdupd_lane = extractelement <1 x double> %1, i32 0 # | store double %vdupd_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556161bfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556161bfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556161bff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e57a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e57aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e57a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e57a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556161b94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556161b94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556161b798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556161828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556161828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e57a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e57a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e57a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556161828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (87 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (88 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (89 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564261a0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564261a08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564261a0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe578733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe57878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe578733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe57871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642619a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642619a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642619868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564261635e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564261635b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe57871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe57871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe57871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564261635a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (90 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055790d6aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055790d6a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055790d6ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67a5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67a5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67a5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67a5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055790d640bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055790d640a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055790d6258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055790d2d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055790d2d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67a5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67a5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67a5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055790d2d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (91 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/164791) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a4dd33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a4dd30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4dd3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feacc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feacc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feacc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feacc631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4dcc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4dcc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a4dcae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a4d95de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a4d95db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feacc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feacc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feacc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a4d95da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (92 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fef78abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fef78a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fef78ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ffe505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ffe55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ffe505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ffe4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fef7841bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fef7841a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fef78268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fef74d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fef74d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ffe4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ffe4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ffe4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fef74d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (93 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/150649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056145d753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056145d750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056145d75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf24b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf24b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf24b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf24b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056145d6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056145d6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056145d6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056145d37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056145d37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf24b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf24b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf24b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056145d37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (94 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611cb971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611cb96ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611cb97262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a6901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a690725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a6901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a69003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611cb907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611cb907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611cb8ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611cb59be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611cb59bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a69004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a690050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a690050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611cb59ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (95 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (96 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (97 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (98 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aaa4ac3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aaa4ac0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aaa4ac462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e4f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e4f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e4f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e4f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aaa4a59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aaa4a59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aaa4a3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aaa46ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aaa46edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e4f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e4f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e4f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaa46eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (99 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (100 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i) # | %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8> # | store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i) # | %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8> # | store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i) # | %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8> # | store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i) # | %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8> # | store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i) # | %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8> # | store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i) # | %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8> # | store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i) # | %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8> # | store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i) # | %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8> # | store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i) # | %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8> # | store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i) # | %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8> # | store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i) # | %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8> # | store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x # | ... # `---data was truncated (10240/16447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557343135eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557343132e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055734313662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee4d031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573430cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005573430cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573430b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557342d5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557342d5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee4d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557342d5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/widen.c (101 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = sext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = sext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = sext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = zext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = zext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = zext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i1 = alloca <8 x i8>, align 8 # | %__p0_561.addr.i = alloca <16 x i8>, align 16 # | %__ret_561.i = alloca <8 x i16>, align 16 # | %__a1_561.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %__s0.i = alloca <8 x i8>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0_561.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16 # | store <16 x i8> %1, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <8 x i8>, ptr %__ret.i1, align 8 # | store <8 x i8> %4, ptr %__a1_561.i, align 8 # | %5 = load <8 x i8>, ptr %__a1_561.i, align 8 # | store <8 x i8> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = sext <8 x i8> %6 to <8 x i16> # | store <8 x i16> %7, ptr %ref.tmp1.i, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16 # | store <8 x i16> %8, ptr %__ret.i, align 16 # | %9 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %9, ptr %tmp.i, align 16 # | %10 = load <8 x i16>, ptr %tmp.i, align 16 # | store <8 x i16> %10, ptr %ref.tmp.i, align 16 # | %11 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %11, ptr %__ret_561.i, align 16 # | %12 = load <8 x i16>, ptr %__ret_561.i, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i1 = alloca <4 x i16>, align 8 # | %__p0_567.addr.i = alloca <8 x i16>, align 16 # | %__ret_567.i = alloca <4 x i32>, align 16 # | %__a1_567.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0_567.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16 # | store <8 x i16> %1, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <4 x i16>, ptr %__ret.i1, align 8 # | store <4 x i16> %4, ptr %__a1_567.i, align 8 # | %5 = load <4 x i16>, ptr %__a1_567.i, align 8 # | store <4 x i16> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = sext <4 x i16> %7 to <4 x i32> # | store <4 x i32> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %9, ptr %__ret.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %10, ptr %tmp.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i, align 16 # | %12 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %12, ptr %__ret_567.i, align 16 # | %13 = load <4 x i32>, ptr %__ret_567.i, align 16 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i1 = alloca <2 x i32>, align 8 # | %__p0_564.addr.i = alloca <4 x i32>, align 16 # | %__ret_564.i = alloca <2 x i64>, align 16 # | %__a1_564.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %__s0.i = alloca <2 x i32>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0_564.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16 # | store <4 x i32> %1, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <2 x i32>, ptr %__ret.i1, align 8 # | store <2 x i32> %4, ptr %__a1_564.i, align 8 # | %5 = load <2 x i32>, ptr %__a1_564.i, align 8 # | store <2 x i32> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %8 = sext <2 x i32> %7 to <2 x i64> # | store <2 x i64> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16 # | store <2 x i64> %9, ptr %__ret.i, align 16 # | %10 = load <2 x i64>, ptr %__ret.i, align 16 # | store <2 x i64> %10, ptr %tmp.i, align 16 # | %11 = load <2 x i64>, ptr %tmp.i, align 16 # | store <2 x i64> %11, ptr %ref.tmp.i, align 16 # | %12 = load <2 # | ... # `---data was truncated (10240/16529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d7bafdeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7bafdbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7bafdf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60bc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60bc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60bc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60bc031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7baf74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7baf74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7baf598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7bac08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7bac08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60bc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60bc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60bc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7bac08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/135337) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635359c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635359c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635359c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14be71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056353595dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056353595da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635359428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635355f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635355f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14be71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635355f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fc6625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fc6622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fc662662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5faed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fc65bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fc65bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fc65a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fc624fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fc624fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f5faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5faef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fc624fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0aab00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0aaafde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0aab0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b10d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0aaa96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0aaa96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0aaa7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0aa72ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0aa72ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0aa72aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (105 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, al # | ... # `---data was truncated (10240/58468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561d02c26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d02c23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d02c2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8db0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8db0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8db0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8db0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d02bbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d02bbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d02ba18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d02850e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d02850b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8db0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8db0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8db0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d02850a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (106 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (107 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563b117cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b117c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b117cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f277be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f277bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f277be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f277be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b11761bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b11761a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b117468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b113f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b113f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f277be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f277be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f277be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b113f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/18669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b1aed5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b1aed2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b1aed662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d75449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d75449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d75431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b1ae6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b1ae6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b1ae508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b1aaffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b1aaffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d75432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d754330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b1aaffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x float>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %b.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store <8 x float> %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load <8 x float>, ptr %b.addr, align 8 # | %add = fadd <8 x float> %0, %1 # | store <8 x float> %add, ptr %retval, align 8 # | %2 = load <8 x float>, ptr %retval, # | ... # `---data was truncated (10240/145303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000561c7654beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c76548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c7654c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcae6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcae6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcae6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcae6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c764e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c764e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c764c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c76175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c76175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcae6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcae6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcae6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c76175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (110 of 27910) ******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13) # | ret <2 x double> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundlit # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2cd699eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2cd696e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2cd69a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cf461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cf46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cf461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cf4603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2cd62fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2cd62fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2cd6148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2cd2c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2cd2c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cf4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cf46050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cf46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2cd2c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3e9490eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3e948de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3e949162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85cad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85cad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85cad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85cad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3e9426bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3e9426a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3e940b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3e90bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3e90bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85cad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85cad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85cad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3e90baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8c6fe2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8c6fdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8c6fe362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d21533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d2158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d21533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d2151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8c6f78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8c6f78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8c6f5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8c6c0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8c6c0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d2151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d2151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d2151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8c6c0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641349f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641349f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641349f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6fb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6fb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6fb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6fb031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056413498cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056413498ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641349718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564134620e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564134620b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6fb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6fb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6fb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564134620a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630242b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630242b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630242b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbe4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbe46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbe4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbe4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056302424cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056302424ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630242318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563023ee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563023ee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbe4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbe46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbe46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563023ee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(< # | ... # `---data was truncated (10240/11404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d257a28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d257a25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d257a2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb208e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb208ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb208e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb208e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2579bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2579bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2579a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d257652e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d257652b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb208e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb208e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb208e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d257652a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e71fc82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e71fc7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e71fc8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa18fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa18fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa18fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa18fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e71fc18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e71fc18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e71fbfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e71f8ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e71f8acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa18fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa18fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa18fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e71f8aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555679203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555679200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055567920462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0e8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0e86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0e8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0e8631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555679199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555679199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055567917e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555678e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555678e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0e8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0e86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0e86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555678e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (118 of 27910) ******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> # | ret <8 x float> %shufp # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> # | ret <2 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> # | ret <4 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> # | ret <8 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <4 x double> %b, ptr %b.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <4 x double>, ptr %b.addr, align 32 # | %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> # | ret <4 x double> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> # | ret <8 x float> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <4 x i64>, align 32 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <4 x i64> %b, ptr %b.addr, align 32 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <4 x i64>, ptr %b.addr, align 32 # | %3 = bitcast <4 x i64> %2 to <8 x i32> # | %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> # | %4 = bitcast <8 x i32> %vperm to <4 x i64> # | ret <4 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3 # | store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16 # | %7 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__d.i = alloca double, align 8 # | %.compoundliteral.i = alloca <4 x double>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load double, ptr %1, align 1 # | store double %2, ptr %__d.i, align 8 # | %3 = load double, ptr %__d.i, align 8 # | %vecinit.i = insertelement <4 x double> poison, double %3, i32 0 # | %4 = load double, ptr %__d.i, align 8 # | %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1 # | %5 = load double, ptr %__d.i, align 8 # | %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2 # | %6 = load double, ptr %__d.i, align 8 # | %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3 # | store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32 # | %7 = load <4 x double>, ptr %.compoundliteral.i, align 32 # | ret <4 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <8 x float>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <8 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3 # | %7 = load float, ptr %__f.i, align 4 # | %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4 # | %8 = load float, ptr %__f.i, align 4 # | %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5 # | %9 = load float, ptr %__f.i, align 4 # | %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6 # | %10 = load float, ptr %__f.i, align 4 # | %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7 # | store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32 # | %11 = load <8 x float>, ptr %.compoundliteral.i, align 32 # | ret <8 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <4 x float>, align 16 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> # | %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> # | ret <8 x float> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <2 x double>, align 16 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> # | %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> # | ret <4 x double> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <2 x i64>, align 16 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <2 x i64>, ptr # | ... # `---data was truncated (10240/21933) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ca4a66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ca4a63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ca4a6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe25ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe25eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe25ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe25ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ca49fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ca49fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ca49e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ca4690e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ca4690b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe25ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe25ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe25ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ca4690a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d008506eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d008503e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d00850762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a90a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a90aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a90a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a90a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d00849cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d00849ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0084818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d008130e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d008130b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a90a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a90a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a90a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d008130a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559121f18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559121f15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559121f1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3912133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f391218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3912133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f391211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559121eaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559121eaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559121e938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559121b42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559121b42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f391211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f391211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f391211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559121b42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf1ac38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf1ac35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf1ac3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc6b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc6b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc6b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc6b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf1abcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf1abcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf1abb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf1a862e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf1a862b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc6b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc6b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc6b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf1a862a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (123 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x # | ... # `---data was truncated (10240/29267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4d0588eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4d0585e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4d058962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a92333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a9238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a92333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a9231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4d051ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4d051ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4d05038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4d01b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4d01b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a9231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a9231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a9231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4d01b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %sr # | ... # `---data was truncated (10240/288111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556910cc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556910cc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556910cca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5746333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f574638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5746333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f574631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556910c5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556910c5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556910c448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569108f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569108f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f574631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f574631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f574631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569108f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b3e9b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b3e9ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b3e9b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf7f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf7f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf7f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf7f231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b3e946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b3e946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b3e92b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b3e5dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b3e5dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf7f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf7f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf7f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b3e5daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af43aa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af43aa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af43aaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f340bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f340bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f340bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f340bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af43a3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af43a3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af43a248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af436d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af436d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f340bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f340bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f340bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af436d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d31af06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d31af03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d31af0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f625ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f625caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f625ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f625ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d31ae9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d31ae9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d31ae818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d31ab30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d31ab30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f625ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f625ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f625ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d31ab30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0dc953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0dc950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0dc95462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c80a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c80aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c80a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c80a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0dc8e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0dc8e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0dc8ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0dc57de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0dc57db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c80a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c80a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c80a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0dc57da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/addv.c (131 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svaddv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.faddv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.faddv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svaddv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.faddv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.faddv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svaddv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.faddv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.faddv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | a # | ... # `---data was truncated (10240/10826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x0000560d1bc4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d1bc48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d1bc4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3353733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f335378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3353733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f335371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d1bbe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d1bbe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d1bbc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d1b875e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d1b875b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f335371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f335371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f335371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d1b875a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2c085ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2c0859e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2c085d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed76905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed7695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed76905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed768ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2c07f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2c07f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2c07d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2c0486e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2c0486b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed768eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed768ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed768ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2c0486a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_l # | ... # `---data was truncated (10240/13585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c76513beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c765138e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c76513c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d5f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d5f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d5f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d5f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7650d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7650d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7650b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c764d65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c764d65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d5f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d5f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d5f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c764d65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (134 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s64( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/134736) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae7a127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae7a124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae7a12862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3f5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3f52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3f5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3f5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae7a0bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae7a0bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae7a0a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae79d51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae79d51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3f5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3f52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3f52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae79d51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 nou # | ... # `---data was truncated (10240/78890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f105167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f105164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f10516862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05a6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05a618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05a6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05a611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1050fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1050fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1050e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f104d91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f104d91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05a611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05a611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05a611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f104d91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function # | ... # `---data was truncated (10240/66322) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fca9a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fca9a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fca9aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9cbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9cbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9cbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9cbaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fca93fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fca93fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fca9248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fca5d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fca5d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9cbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9cbaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9cbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fca5d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebefebbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebefeb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebefebc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f8e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f8e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f8e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f8e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebefe51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebefe51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebefe368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebefae5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebefae5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f8e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f8e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f8e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebefae5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569e4920eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569e491de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569e492162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd503533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd50358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd503533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd50351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569e48b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569e48b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569e489b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569e454ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569e454ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd50351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd50351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd50351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569e454aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ee68e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ee68e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ee68e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff06431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ee687dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ee687da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ee68628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ee6511e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ee6511b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff064330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ee6511a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (141 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %v # | ... # `---data was truncated (10240/11349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4c6d38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4c6d35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4c6d3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e73049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e730a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e73049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e73031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4c6ccebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4c6ccea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4c6cb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4c6962e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4c6962b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e73032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e730330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e730330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4c6962a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fa9d79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fa9d76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fa9d7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facdfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facdfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facdfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facdfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fa9d0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fa9d0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fa9cf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fa99a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fa99a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007facdfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facdfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facdfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fa99a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , al # | ... # `---data was truncated (10240/92370) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559cfa8c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559cfa8c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559cfa8c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5536533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f553658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5536533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f553651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cfa85cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559cfa85ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559cfa8418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559cfa4f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559cfa4f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f553651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f553651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f553651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cfa4f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d371aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d371a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d371ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faceb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faceb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faceb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faceb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d37142bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d37142a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d371278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d36dd6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d36dd6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faceb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faceb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faceb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d36dd6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (145 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000560a35f72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a35f6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a35f7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e97333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e9738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e97333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e9731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a35f08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a35f08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a35eed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a35b9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a35b9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e9731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e9731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e9731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a35b9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ced12a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ced12a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ced12a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc0c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ced123bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ced123ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ced12208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ced0ecfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ced0ecfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bc0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc0c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ced0ecfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5298d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5298d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5298d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f642ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f642ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f642ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f642aced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a52986ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a52986ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5298538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a529502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a529502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f642aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f642acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f642acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a529502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr # | ... # `---data was truncated (10240/27541) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c17b4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c17b48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c17b4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3a4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3a4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3a4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3a4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c17ae1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c17ae1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c17ac68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c17775e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c17775b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3a4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3a4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3a4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c17775a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c6566aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c65667e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c6566b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b55c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b55ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b55c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b55c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c65600bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c65600a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c655e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c65294e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c65294b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b55c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b55c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b55c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c65294a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cc12b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cc12b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cc12b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c9cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c9cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c9cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c9cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc124cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cc124ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cc12318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cc0ee0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cc0ee0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c9cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c9cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c9cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc0ee0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bee09cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bee09c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bee09cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7850849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7850849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7850831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bee0961bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bee0961a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bee09468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bee05f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bee05f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7850832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78508330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bee05f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e9a90ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e9a909e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e9a90d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec97f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec97f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec97f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec97f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e9a8a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e9a8a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e9a8878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e9a536e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e9a536b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec97f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec97f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec97f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e9a536a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632e99f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632e99ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632e99f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f250081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25008725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f250081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2500803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632e9986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632e9986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632e996b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632e961ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632e961ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2500804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25008050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25008050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632e961aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055954104beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559541048e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055954104c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f226ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f226ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f226ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f226ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559540fe1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559540fe1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559540fc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559540c75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559540c75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f226ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f226ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f226ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559540c75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (155 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i) # | %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8> # | store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i) # | %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i) # | %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8> # | store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i) # | %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i) # | %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8> # | store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i) # | %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i) # | %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8> # | store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i) # | %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double> # | %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i) # | %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8> # | store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i) # | %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f64.i = bitcast <8 x i8> %1 # | ... # `---data was truncated (10240/18543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558ed3d62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ed3d5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ed3d6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4801d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4801d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4801d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4801d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ed3cf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ed3cf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ed3cdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ed398ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ed398cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4801d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4801d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4801d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ed398ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clo_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562468a79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562468a76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562468a7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98a4c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98a4c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98a4c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98a4c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562468a0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562468a0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624689f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624686a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624686a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98a4c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98a4c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98a4c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624686a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (157 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr % # | ... # `---data was truncated (10240/11173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005642c2f55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642c2f52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642c2f5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ba4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ba438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ba4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ba431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642c2eebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642c2eeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642c2ed08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642c2b7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642c2b7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ba431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ba431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ba431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642c2b7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588f92e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588f92e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588f92e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6a6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6a62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6a6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6a6231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588f927abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588f927aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588f925f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588f8f0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588f8f0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6a6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6a62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6a62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588f8f0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (160 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_mf8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_bf16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005574a9019eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574a9016e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574a901a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbc9f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbc9f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbc9f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbc9eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574a8fafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574a8fafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574a8f948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574a8c43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574a8c43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbc9eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbc9eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbc9eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574a8c43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b967c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b967c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b967ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1891d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1891d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1891d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1891d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b9675fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b9675fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b967448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b963f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b963f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1891d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1891d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1891d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b963f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (163 of 27910) ******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # | #0 0x000055a07d623eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a07d620e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a07d62462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5a4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5a498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5a4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5a491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a07d5b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a07d5b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a07d59e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a07d24de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a07d24db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5a491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5a491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5a491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a07d24da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce7d230eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce7d22de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce7d23162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f571f01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f571f0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f571f01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f571f003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce7d1c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce7d1c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce7d1ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce7ce5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce7ce5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f571f004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f571f0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f571f0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce7ce5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm64_vcreate.c (166 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind optnone # | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 { # | entry: # | %a1.addr = alloca i64, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <2 x float>, align 8 # | store i64 %a1, ptr %a1.addr, align 8 # | %0 = load i64, ptr %a1.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <2 x float>, ptr %__promote, align 8 # | store <2 x float> %1, ptr %__ret, align 8 # | %2 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %2, ptr %tmp, align 8 # | %3 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %3 # | } # | # | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572ca3cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572ca3c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572ca3cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0e8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0e898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0e8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0e891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572ca361bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572ca361a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572ca3468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572c9ff5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572c9ff5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0e891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0e891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0e891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572c9ff5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (167 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, %6, %7, %8, %9, %10, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 # | ... # `---data was truncated (10240/39820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000565180403eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565180400e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056518040462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f721a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f721a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f721a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f721a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565180399bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565180399a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056518037e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056518002de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056518002db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f721a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f721a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f721a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056518002da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c8bbf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c8bbf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c8bbf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f799e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f799e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f799e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f799e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c8bb8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c8bb8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c8bb728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c8b821e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c8b821b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f799e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f799e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f799e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c8b821a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (170 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvtl_f32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559083d75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559083d72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559083d7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b06333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b0638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b06333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b0631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559083d0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559083d0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559083cf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055908399fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055908399fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b0631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b0631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b0631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055908399fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (171 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_bf16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 t # | ... # `---data was truncated (10240/168193) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x0000557e4b509eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e4b506e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e4b50a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ca9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ca94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ca9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ca9431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e4b49fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e4b49fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e4b4848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e4b133e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e4b133b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ca9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ca94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ca94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e4b133a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/424049) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563530228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563530225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056353022962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635301bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635301bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635301a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056352fe52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056352fe52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056352fe52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c98e1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c98e1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c98e1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc46933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc4698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc46933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc4691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c98db3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c98db3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c98d988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c98a47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c98a47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc4691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc4691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc4691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c98a47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/andv.c (174 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.andv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.andv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.andv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.andv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x00005637cd9eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637cd9e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637cd9ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0711249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07112a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0711249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0711231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637cd982bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637cd982a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637cd9678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637cd616e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637cd616b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0711232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07112330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07112330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637cd616a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @or_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %or = or <32 x i8> %0, %1 # | store <32 x i8> %or, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_ # | ... # `---data was truncated (10240/10440) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf2582aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf25827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf2582b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc291533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc29158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc291533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc29151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf257c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf257c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf257a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf25454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf25454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc29151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc29151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc29151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf25454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-neon-vcadd.c (177 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.3a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i) # | %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i) # | %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i) # | %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %result = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float> # | %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float> # | %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i) # | %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i) # | %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i) # | %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i) # | %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 # | ... # `---data was truncated (10240/13572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # | #0 0x000055fbc1854eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbc1851e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbc185562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec09933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec0998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec09933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec0991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbc17eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbc17eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbc17cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbc147ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbc147eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec0991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec0991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec0991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbc147ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (178 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/81756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558969776eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558969773e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055896977762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d78333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d7838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d78333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d7831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055896970cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055896970ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589696f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589693a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589693a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d7831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d7831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d7831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589693a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (179 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5) # | %7 = extractvalue { i32, <4 x i32> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <4 x i32> } %6, 1 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | # | ... # `---data was truncated (10240/11454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8bf05ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8bf059e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8bf05d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b6131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8beff2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8beff2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8befd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8bec86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8bec86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b6131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8bec86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560770dd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560770dd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560770dd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd325e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd325ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd325e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd325e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560770d6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560770d6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560770d538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560770a02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560770a02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd325e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd325e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd325e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560770a02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (181 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvt.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvtn.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt1_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16( %0) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt2_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr # | ... # `---data was truncated (10240/17058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005619c1351eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619c134ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619c135262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f88d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f88d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f88d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f88ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619c12e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619c12e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619c12cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619c0f7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619c0f7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f88ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f88cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f88cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619c0f7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/66065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559062707eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559062704e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055906270862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f214f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f214f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f214f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f214f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055906269dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055906269da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590626828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559062331e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559062331b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f214f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f214f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f214f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559062331a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581ce5c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581ce5c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581ce5ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0772333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f077238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0772333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f077231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581ce55fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581ce55fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581ce5448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581ce1f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581ce1f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f077231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f077231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f077231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581ce1f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (184 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e92a2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e92a2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e92a2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f997c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f997c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f997c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f997c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e92a254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e92a254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e92a2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e929ee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e929ee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f997c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f997c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f997c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e929ee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3f05abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3f05a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3f05ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f35933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f3598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f35933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f3591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3f0541bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3f0541a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3f05268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3f01d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3f01d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f3591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f3591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f3591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3f01d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ef7d33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ef7d30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ef7d3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ae3705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ae375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ae3705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ae36ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ef7cc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ef7cc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ef7cae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ef795de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ef795db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ae36eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ae36ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ae36ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ef795da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (187 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfirst_b( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pfirst.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pfirst.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005622a1dc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622a1dc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622a1dc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f103f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f103f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f103f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f103f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622a1d5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622a1d5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622a1d418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622a19f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622a19f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f103f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f103f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f103f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622a19f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (188 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.clz.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.clz.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (189 of 27910) ******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc | not grep _foo2 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @bar() #0 { # | entry: # | call void @foo2() # | ret void # | } # | # | declare void @foo2() #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # | #0 0x000055c6c428aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6c4287e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6c428b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e9c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e9c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e9c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e9c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6c4220bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6c4220a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6c42058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6c3eb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6c3eb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e9c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e9c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e9c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6c3eb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: llc # executed command: not grep _foo2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu( %ma # | ... # `---data was truncated (10240/619127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d98b6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d98b6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d98b7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd918f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd918f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd918f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd918f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d98b05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d98b05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d98aea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d98799e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d98799b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd918f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd918f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd918f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d98799a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (191 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %2) # | call void @llvm.aarch64.sve.st2.nxv2i64.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } # | ... # `---data was truncated (10240/45653) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560641fdbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560641fd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560641fdc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eeeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eeeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eeeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eeeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560641f71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560641f71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560641f568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560641c05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560641c05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4eeeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eeeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eeeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560641c05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (192 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm # | ... # `---data was truncated (10240/24404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f6838b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6838b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6838b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc57cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc57cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc57cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc57cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f68384dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f68384da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6838328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6834e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6834e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc57cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc57cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc57cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6834e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (193 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 1) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 3) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 7) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (194 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056263bab9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056263bab6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056263baba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7462333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f746238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7462333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f746231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056263ba4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056263ba4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056263ba348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056263b6e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056263b6e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f746231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f746231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f746231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056263b6e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (195 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_z( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_m( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_x( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555dbf897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555dbf894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555dbf89862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f420c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f420c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f420c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f420c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dbf82dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555dbf82da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555dbf8128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dbf4c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dbf4c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f420c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f420c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f420c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dbf4c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (196 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_3_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ee07e65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee07e62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee07e6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff294733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff29478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff294733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff29471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee07dfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee07dfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee07de08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee07a8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee07a8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff29471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff29471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff29471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee07a8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055876168aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558761687e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055876168b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4090449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4090449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4090431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558761620bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558761620a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587616058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587612b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587612b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4090432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40904330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587612b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (198 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align # | ... # `---data was truncated (10240/127452) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005616f07aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616f07abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616f07af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4889f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4889f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4889f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4889f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616f0744bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616f0744a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616f07298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616f03d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616f03d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4889f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4889f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4889f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616f03d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (199 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(, , ptr # | ... # `---data was truncated (10240/26796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005612487a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612487a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612487a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4240933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f424098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4240933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f424091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056124873abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056124873aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056124871f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612483cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612483ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f424091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f424091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f424091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612483cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (200 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | e # | ... # `---data was truncated (10240/32866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055aa51362eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa5135fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa5136362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b5121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b512725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b5121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b51203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa512f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa512f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa512dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa50f8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa50f8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b51204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b512050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b512050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa50f8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fc5d72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fc5d6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fc5d7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33f8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33f86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33f8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33f8631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fc5d08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fc5d08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fc5ced8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fc599ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fc599cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33f8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33f86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33f86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fc599ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (202 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8f16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr # | ... # `---data was truncated (10240/12880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bc6df9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc6df99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc6df9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf49a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf49aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf49a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf49a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc6df32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc6df32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc6df178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc6dbc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc6dbc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf49a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf49a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf49a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc6dbc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (203 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrinta_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frinta.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frinta.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrinta_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintam_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintm.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frintm.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrintm_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintn_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintn.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn me # | ... # `---data was truncated (10240/17932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562503b04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562503b01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562503b0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b58049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b580a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b58049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b58031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562503a9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562503a9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562503a7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056250372ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056250372eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b58032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b580330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b580330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056250372ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (204 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cd4681ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd46819e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd4681d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcbe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcbe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcbe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcbe831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd467b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd467b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd467978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd46446e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd46446b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcbe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcbe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcbe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd46446a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (205 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (206 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret # | ... # `---data was truncated (10240/58597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005598a941aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598a9417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598a941b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31cf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31cf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31cf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31cf431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598a93b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598a93b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598a93958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598a9044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598a9044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31cf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31cf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31cf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598a9044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b08c55eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b08c55be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b08c55f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95fdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95fdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95fdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95fdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b08c4f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b08c4f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b08c4d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b08c188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b08c188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95fdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95fdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95fdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b08c188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (208 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557a7a725eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a7a722e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a7a72662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85d431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a7a6bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a7a6bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a7a6a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a7a34fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a7a34fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85d431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a7a34fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (209 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(, ptr, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_s32offset( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/16554) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557b78802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b787ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b7880362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59bd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b78798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b78798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b7877d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b7842ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b7842cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b7842ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (210 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <8 x i16> %2, %3 # | store <8 x i16> %mul.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <4 x i32> %2, %3 # | store <4 x i32> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | s # | ... # `---data was truncated (10240/798827) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b63b8caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b63b8c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b63b8cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f632581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63258725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f632581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6325803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b63b860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b63b860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b63b8458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b63b4f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b63b4f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6325804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63258050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63258050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b63b4f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/minv.c (211 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005644bee94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644bee91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644bee9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40b4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644bee2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644bee2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644bee0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644beabee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644beabeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40b4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644beabea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (212 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559e5b5a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e5b5a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e5b5aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8c8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e5b53fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e5b53fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e5b5248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e5b1d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e5b1d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8c8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e5b1d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (213 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | % # | ... # `---data was truncated (10240/74176) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d3fa59ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3fa599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3fa59d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb5af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3fa532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3fa532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3fa5178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3fa1c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3fa1c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3fa1c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005655388afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005655388ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005655388b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18dd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18dd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18dd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18dd231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565538845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565538845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056553882a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005655384d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005655384d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18dd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18dd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18dd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655384d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (215 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvt.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvt.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvt.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_u32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_s32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcvt_f32_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, p # | ... # `---data was truncated (10240/39207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056057fae5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056057fae2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056057fae662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3f0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3f0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3f0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3f0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056057fa7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056057fa7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056057fa608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056057f70fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056057f70fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff3f0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3f0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3f0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056057f70fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (216 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svminnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560879f5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560879f5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560879f5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0725d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0725d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0725d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0725d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560879ef4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560879ef4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560879ed98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560879b88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560879b88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0725d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0725d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0725d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560879b88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (217 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0) # | ret { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (218 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bb98a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558bb98a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558bb98aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8361933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f836198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8361933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f836191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bb983fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558bb983fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558bb98248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bb94d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bb94d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f836191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f836191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f836191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bb94d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (220 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/15264) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005557d2361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557d235ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557d236262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda1eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda1eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda1eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda1eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557d22f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557d22f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557d22dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557d1f8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557d1f8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda1eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda1eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda1eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557d1f8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (221 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (222 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svldr_zt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svstr_zt(ptr noundef %base) #2 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) } # | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f18fff7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f18fff4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f18fff862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4349c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4349ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4349c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4349c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f18ff8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f18ff8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f18ff728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f18fc21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f18fc21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4349c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4349c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4349c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f18fc21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (223 of 27910) ******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7s-apple-darwin" # | # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, ptr %__p0.addr.i1, align 8 # | store <8 x i8> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %8, ptr %__ret.i3, align 8 # | %9 = load <8 x i8>, ptr %__ret.i3, align 8 # | %add.i = add <8 x i8> %3, %9 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x i16>, align 8 # | %__p1.addr.i2 = alloca <4 x i16>, align 8 # | %__ret.i3 = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %5 = load <4 x i16>, ptr %__p2.addr.i, align 8 # | store <4 x i16> %4, ptr %__p0.addr.i1, align 8 # | store <4 x i16> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16> # | %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16> # | %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i) # | %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %8, ptr %__ret.i3, align 8 # | %9 = load <4 x i16>, ptr %__ret.i3, align 8 # | %add.i = add <4 x i16> %3, %9 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %10 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <2 x i32>, align 8 # | %__p1.addr.i2 = alloca <2 x i32>, align 8 # | %__ret.i3 = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x i32>, ptr %__p2.addr.i, align 8 # | store <2 x i32> %4, ptr %__p0.addr.i1, align 8 # | store <2 x i32> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32> # | %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32> # | %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i) # | %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %8, ptr %__ret.i3, align 8 # | %9 = load <2 x i32>, ptr %__ret.i3, align 8 # | %add.i = add <2 x i32> %3, %9 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %10 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, pt # | ... # `---data was truncated (10240/2159854) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055738dfa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055738dfa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055738dfaa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7896849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7896849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7896831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055738df3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055738df3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055738df248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055738dbd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055738dbd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7896832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055738dbd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (224 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splat # | ... # `---data was truncated (10240/24132) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559c73899eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c73896e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c7389a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febba505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febba55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febba505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febba4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c7382fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c7382fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c738148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c734c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c734c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febba4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febba4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febba4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c734c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (225 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562daf8a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562daf89fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562daf8a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1095049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1095049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1095031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562daf838bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562daf838a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562daf81d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562daf4cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562daf4ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1095032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10950330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562daf4cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (226 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_x( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtnt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_m( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f60671beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f606718e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f60671c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeadd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeadd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeadd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeadd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6066b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6066b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6066968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f606345e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f606345b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feeadd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeadd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeadd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f606345a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632d85cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632d85cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632d85ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb99249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb99249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb99231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632d8563bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632d8563a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632d85488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632d81f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632d81f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb99232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb992330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632d81f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (228 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brkb.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkb.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005629cd58feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629cd58ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629cd59062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d53049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d530a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d53049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d53031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629cd525bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629cd525a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629cd50a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629cd1b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629cd1b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d53032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d530330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d530330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629cd1b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (229 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c2af768eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2af765e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2af76962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa42049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa420a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa42049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa42031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2af6febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2af6fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2af6e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2af392e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2af392b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa42032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa420330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa420330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2af392a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (230 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005611954b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611954b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611954b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcae4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcae478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcae4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcae471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056119544cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056119544ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611954318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611950e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611950e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcae471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcae471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcae471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611950e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (231 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %and = and <8 x i8> %2, %3 # | store <8 x i8> %and, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %and = and <8 x i64> %0, %1 # | store <8 x i64> %and, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619b161ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619b1619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619b161d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35bb81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35bb8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35bb81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35bb803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619b15b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619b15b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619b15978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619b1246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619b1246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35bb804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35bb8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35bb8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619b1246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c89dc13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c89dc10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c89dc1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f204b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f204b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f204b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f204b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c89dba9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c89dba9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c89db8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c89d83de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c89d83db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f204b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f204b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f204b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c89d83da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (235 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560c2cb15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c2cb12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c2cb1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bd9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bd918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bd9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bd911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c2caabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c2caaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c2ca908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c2c73fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c2c73fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bd911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bd911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bd911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2c73fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (236 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 2) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8f16( %0, i32 4) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8f16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4f32( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4f32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2f64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2f64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8bf16( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8bf16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055600a610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055600a60de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055600a61162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe372e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe372ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe372e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe372e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055600a5a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055600a5a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055600a58b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055600a23ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055600a23ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe372e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe372e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe372e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055600a23aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (237 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056224b578eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056224b575e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056224b57962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb46e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb46e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb46e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb46e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056224b50ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056224b50ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056224b4f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056224b1a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056224b1a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb46e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb46e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb46e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056224b1a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store targ # | ... # `---data was truncated (10240/14667) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b6babaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b6bab7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b6babb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7ccd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7ccd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7ccd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7ccd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b6ba50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b6ba50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b6ba358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b6b6e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b6b6e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7ccd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7ccd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7ccd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b6b6e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (239 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.neg.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f1b1a5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1b1a59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1b1a5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec5f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec5f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec5f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec5f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1b19f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1b19f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1b19d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1b1686e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1b1686b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec5f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec5f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec5f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1b1686a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dacae65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dacae62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dacae6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba92b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dacadfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dacadfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dacade08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dacaa8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dacaa8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dacaa8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (241 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005635517f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635517efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635517f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fade1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fade178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fade1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fade171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563551788bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563551788a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056355176d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056355141ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056355141cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fade171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fade171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fade171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056355141ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce03d5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce03d59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce03d5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1edb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1edb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1edb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1edaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce03cf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce03cf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce03cd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce03986e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce03986b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1edaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1edaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1edaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce03986a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (243 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/46416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561960d39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561960d36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561960d3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7922a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7922aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7922a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7922a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561960ccfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561960ccfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561960cb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561960963e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561960963b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7922a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7922a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7922a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561960963a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (244 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_mf8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_bf16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599a65aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599a65a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599a65ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3aecf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3aecf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3aecf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3aecf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599a6540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599a6540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599a65258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599a61d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599a61d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3aecf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3aecf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3aecf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599a61d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9c7a23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9c7a20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9c7a2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9753133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f975318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9753133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f975311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9c79b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9c79b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9c799e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9c764de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9c764db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f975311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f975311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f975311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9c764da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/14493) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaeeceeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eaeecebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eaeecef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efebc305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efebc35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efebc305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efebc2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaeec84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eaeec84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eaeec698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eaee918e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eaee918b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efebc2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efebc2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efebc2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaee918a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de0452aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de04527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de0452b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6999249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6999249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6999231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de044c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de044c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de044a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de04154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de04154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6999232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69992330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de04154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (249 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2665aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2665a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2665ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f239cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f239cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f239cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f239cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e266542bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e266542a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2665278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2661d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2661d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f239cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f239cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f239cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2661d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f13f48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f13f45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f13f4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98c141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98c14725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98c141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98c1403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f13edebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f13edea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f13ec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f13b72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f13b72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98c1404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98c14050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98c14050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f13b72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (251 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1) # | store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1) # | store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca double, align 8 # | %ref.tmp.i = alloca double, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1) # | store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8 # | %2 = load double, ptr %ref.tmp.i, align 8 # | store double %2, ptr %__ret.i, align 8 # | %3 = load double, ptr %__ret.i, align 8 # | ret double %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16> # | %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3) # | store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32> # | %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9) # | store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %2, ptr %__ret, align 8 # | %3 = load <4 x i16>, p # | ... # `---data was truncated (10240/770739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005648754bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648754bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648754be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a8f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a8f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a8f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a8f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564875453bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564875453a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648754388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648750e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648750e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a8f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a8f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a8f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648750e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (252 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557a371edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a371eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a371ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb786f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb786f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb786f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb786eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a37183bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a37183a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a371688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a36e17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a36e17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb786eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb786eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb786eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a36e17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056267bf60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056267bf5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056267bf6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b8dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b8dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b8dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b8dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056267bef6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056267bef6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056267bedb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056267bb8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056267bb8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b8dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b8dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b8dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056267bb8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (255 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559b81a72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b81a6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b81a7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4af4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4af4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4af4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4af4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b81a08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b81a08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b819ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b8169ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b8169cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4af4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4af4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4af4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b8169ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (256 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za16_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za32_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055701a3c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055701a3c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055701a3c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaeab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaeab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaeab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaeab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055701a35abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055701a35aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055701a33f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557019feee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557019feeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaeab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaeab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaeab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557019feea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cfb7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cfb7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cfb7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf26f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf26f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf26f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf26f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cfb791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cfb791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cfb7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cfb425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cfb425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf26f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf26f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf26f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cfb425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (258 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556df0442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556df043fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556df044362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f110c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f110c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f110c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f110c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556df03d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556df03d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556df03bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556df006ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556df006cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f110c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f110c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f110c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556df006ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (261 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000565436cf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565436cf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565436cf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa5981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa598725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa5981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa59803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565436c8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565436c8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565436c728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565436921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565436921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa59804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa598050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa598050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565436921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (262 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/11908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bcafe39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcafe36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcafe3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f843ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f843ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f843ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f843ee03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcafdcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcafdcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcafdb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcafa63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcafa63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f843ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f843ee050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f843ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcafa63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (263 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 13, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 29, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b21afffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b21affce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b21b00062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb85649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb85649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb85631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b21af95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b21af95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b21af7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b21ac29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b21ac29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb85632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb856330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b21ac29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (264 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055965e838eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055965e835e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055965e83962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd959333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd95938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd959333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd95931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055965e7cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055965e7cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055965e7b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055965e462e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055965e462b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd95931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd95931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd95931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055965e462a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vr # | ... # `---data was truncated (10240/96265) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b96113eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b96110e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b9611462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81b4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81b458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81b4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81b451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b960a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b960a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b9608e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b95d3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b95d3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81b451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81b451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81b451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b95d3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (266 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca < # | ... # `---data was truncated (10240/107144) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055af088f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af088f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af088f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe120849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1208a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe120849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe120831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af0888abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af0888aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af0886f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af0851ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af0851eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe120832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1208330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1208330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af0851ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a62a8dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a62a8d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a62a8dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e61533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e6158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e61533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e6151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a62a872bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a62a872a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a62a8578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a62a506e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a62a506b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e6151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e6151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e6151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a62a506a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.brev8.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @zip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.zip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @unzip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.unzip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.brev8.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.zip.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.unzip.i32(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629dd69feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629dd69ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629dd6a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2af7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2af778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2af7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2af771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629dd635bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629dd635a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629dd61a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629dd2c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629dd2c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2af771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2af771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2af771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629dd2c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (269 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_s32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_s64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_u32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_u64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056396e7a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056396e7a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056396e7a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d02d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d02d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d02d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d02d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056396e73ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056396e73ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056396e7238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056396e3d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056396e3d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d02d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d02d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d02d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056396e3d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (270 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056328529ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563285299e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056328529d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5b403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563285232bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563285232a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632852178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563284ec6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563284ec6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f5b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563284ec6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (271 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %10) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (272 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005602790d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602790d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602790d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23c9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23c96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23c9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23c9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056027906ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056027906ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602790538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560278d02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560278d02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23c9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23c96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23c96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560278d02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (273 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 29, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 30, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b72b88ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b72b889e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b72b88d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b74333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b7438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b74333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b7431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b72b822bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b72b822a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b72b8078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b72b4b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b72b4b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b7431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b7431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b7431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b72b4b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bafbd7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bafbd78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bafbd7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a43e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a43ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a43e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a43e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bafbd11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bafbd11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bafbcf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bafb9a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bafb9a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a43e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a43e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a43e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bafb9a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (275 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005593cabfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593cabf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593cabfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02a5e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02a5e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02a5e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02a5e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593cab91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593cab91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593cab768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593ca825e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593ca825b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02a5e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02a5e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02a5e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593ca825a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/add.c (276 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %add.i = add <16 x i8> %2, %3 # | store <16 x i8> %add.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %add.i = add <8 x i16> %2, %3 # | store <8 x i16> %add.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b # | ... # `---data was truncated (10240/221881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055943a389eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055943a386e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055943a38a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d5c41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d5c4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d5c41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d5c403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055943a31fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055943a31fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055943a3048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559439fb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559439fb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d5c404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d5c4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d5c4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559439fb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570d05b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570d05b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570d05ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe86af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe86af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe86af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe86af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570d054fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570d054fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570d05348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570d01e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570d01e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe86af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe86af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe86af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570d01e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (278 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (279 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x000055fa125cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa125cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa125d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a81b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a81b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a81b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a81b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa12565bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa12565a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa1254a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa121f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa121f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a81b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a81b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a81b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa121f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (280 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564e29e9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e29e98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e29e9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ea7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ea76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ea7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ea7631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e29e31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e29e31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e29e168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e29ac5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e29ac5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ea7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ea76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ea76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e29ac5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (281 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (282 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c93de1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c93de1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c93de1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41f1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41f138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41f1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41f131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c93ddb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c93ddb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c93dd988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c93da47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c93da47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41f131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41f131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41f131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c93da47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (283 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562107921eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056210791ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056210792262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b9981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b998725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b9981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b99803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621078b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621078b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056210789c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056210754be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056210754bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b99804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b998050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b998050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056210754ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (285 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fc3e7deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc3e7dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc3e7df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69d4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69d46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69d4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69d4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc3e774bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc3e774a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc3e7598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc3e408e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc3e408b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69d4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69d46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69d46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc3e408a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/148020) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f17cc5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f17cc2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f17cc662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f359b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f359b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f359b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f359b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f17c5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f17c5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f17c408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f178efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f178efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f359b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f359b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f359b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f178efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (288 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, % # | ... # `---data was truncated (10240/93831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000559c109daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c109d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c109db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe148249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe148249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe148231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c10970bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c10970a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c109558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c10604e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c10604b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe148232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1482330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c10604a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (289 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056139007ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561390079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056139007d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02d5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02d595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02d5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02d58ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561390012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561390012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056138fff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056138fca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056138fca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02d58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02d58ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02d58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056138fca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/load.c (290 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %0, align 2 # | store <8 x half> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %2, ptr %__ret, align 16 # | %3 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %3, ptr %tmp, align 16 # | %4 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x float>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %0, align 4 # | store <4 x float> %1, ptr %ref.tmp, align 16 # | %2 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %2, ptr %__ret, align 16 # | %3 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %3, ptr %tmp, align 16 # | %4 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <2 x double>, ptr %0, align 8 # | store <2 x double> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %2, ptr %__ret, align 16 # | %3 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %3, ptr %tmp, align 16 # | %4 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load <2 x i64>, ptr %0, align 8 # | store <2 x i64> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %2, ptr %__ret, align 16 # | %3 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %3, ptr %tmp, align 16 # | %4 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store ptr %a # | ... # `---data was truncated (10240/415795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055a600189eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a600186e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a60018a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac7d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac7d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac7d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac7d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a60011fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a60011fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6001048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5ffdb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5ffdb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac7d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac7d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac7d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5ffdb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (291 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s8_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s16_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s32_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s64_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svclamp_single_s8_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561111f1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561111f1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561111f1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8abb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8abb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8abb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8abb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561111eb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561111eb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561111e988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561111b47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561111b47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8abb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8abb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8abb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561111b47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (293 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.lane.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx3( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx7( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 7) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564be3fc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564be3fc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564be3fc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bde333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bde38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bde333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bde31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be3f5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564be3f5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564be3f3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564be3beee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564be3beeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4bde31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bde31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bde31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be3beea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576de33eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576de33be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576de33f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b90249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b902a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b90249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b90231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576de2d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576de2d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576de2b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576ddf68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576ddf68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b90232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b902330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b902330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576ddf68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (295 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561e1983beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e19838e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e1983c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f124bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f124bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e197d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e197d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e197b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e19465e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e19465b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f124bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e19465a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa6a321eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa6a31ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa6a32262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3044333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f304438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3044333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f304431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa6a2b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa6a2b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa6a29c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa69f4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa69f4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f304431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f304431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f304431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa69f4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (297 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/75656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000557226e12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557226e0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557226e1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba3981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba398725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba3981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba39803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557226da8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557226da8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557226d8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557226a3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557226a3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba39804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba398050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba398050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557226a3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (298 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlastb_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lastb.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lastb.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlastb_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lastb.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lastb.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlastb_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lastb.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lastb.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlastb_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563a12036eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a12033e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a1203762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19d0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19d00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19d0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19d0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a11fccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a11fcca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a11fb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a11c60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a11c60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19d0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19d00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19d00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a11c60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (299 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/64727) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562369915eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562369912e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056236991662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa8ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa8eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa8ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa8ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623698abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623698aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623698908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056236953fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056236953fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa8ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa8ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa8ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056236953fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (300 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (301 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ff035b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff035b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff035b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4f491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff0354cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff0354ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff035318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff031e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff031e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4f491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff031e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (302 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555bf37b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bf37b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bf37b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a33849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a338a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a33849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a33831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bf374ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bf374ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bf37338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bf33e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bf33e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a33832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a338330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a338330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bf33e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (303 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563234637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563234634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056323463862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c0f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c0f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c0f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c0f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632345cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632345cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632345b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563234261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563234261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c0f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c0f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c0f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563234261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm_acle_swp.c (304 of 27910) ******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7m-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret i32 %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566a21a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566a21a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566a21a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91dd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91dd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91dd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91dd6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566a213bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566a213ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566a21208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566a1dcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566a1dcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91dd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91dd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91dd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566a1dcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (305 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2i64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2f64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %3) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !" # | ... # `---data was truncated (10240/10573) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056000e34deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056000e34ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056000e34e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a41705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a4175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a41705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a416ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056000e2e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056000e2e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056000e2c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056000df77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056000df77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a416eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a416ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a416ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056000df77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (306 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 8) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 16) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 32) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 64) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %1, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, # | ... # `---data was truncated (10240/14353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005555f97a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555f97a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555f97a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb951849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb951849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb951831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555f9739bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555f9739a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555f971e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555f93cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555f93cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb951832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9518330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555f93cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (307 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557999520eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055799951de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055799952162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72a4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72a4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72a4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72a4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579994b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579994b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055799949b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055799914ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055799914ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f72a4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72a4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72a4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055799914aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (308 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cc38bf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc38bf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc38bf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb723649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7236a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb723649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb723631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc38b8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc38b8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc38b738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc38822e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc38822b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb723632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7236330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7236330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc38822a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (309 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s8_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (310 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { < # | ... # `---data was truncated (10240/50499) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000565098649eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565098646e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056509864a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8050133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f805018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8050133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f805011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650985dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005650985dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650985c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565098273e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565098273b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f805011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f805011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f805011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565098273a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (311 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc9ae13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc9ae10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc9ae1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f937d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f937d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f937d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f937d603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc9ada9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc9ada9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc9ad8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc9aa3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc9aa3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f937d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f937d6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f937d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc9aa3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (312 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (313 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558834e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558834e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558834e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5928333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f592838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5928333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f592831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558834d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558834d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558834d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558834a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558834a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f592831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f592831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f592831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558834a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (314 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceb6c2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ceb6c28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ceb6c2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8d2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8d2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8d2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8d2eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceb6bc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ceb6bc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ceb6ba68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ceb6855e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ceb6855b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8d2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8d2eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8d2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceb6855a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (316 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.abs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005579c7224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579c7221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579c722562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b7c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b7c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b7c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b7c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579c71babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579c71baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579c719f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579c6e4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579c6e4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b7c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b7c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b7c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579c6e4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/len.c (317 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vscale.i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000564bd7d2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564bd7d2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564bd7d3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b49533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b4958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b49533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b4951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bd7cc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564bd7cc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564bd7caa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564bd7959e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564bd7959b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b4951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b4951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b4951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bd7959a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (318 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055dbadff0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbadfede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbadff162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfd3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfd36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfd3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfd3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbadf86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbadf86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbadf6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbadc1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbadc1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfd3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfd36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfd36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbadc1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (319 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfalse_b() #0 { # | entry: # | ret zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005652f932feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652f932ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652f933062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f81c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f81ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f81c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f81c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652f92c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652f92c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652f92aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652f8f59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652f8f59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f81c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f81c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f81c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652f8f59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (320 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/183423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562995033eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562995030e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056299503462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51dee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51deea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51dee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51dee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562994fc9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562994fc9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562994fae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562994c5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562994c5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51dee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51dee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51dee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562994c5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (321 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f16_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f32_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f64_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f16_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %op2.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f32_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr # | ... # `---data was truncated (10240/37349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005611f69fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611f69f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611f69fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8de081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8de08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8de081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8de0803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611f6992bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611f6992a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611f69778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611f6626e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611f6626b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8de0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8de08050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8de08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611f6626a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (323 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c91b15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c91b12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c91b1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03bde31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c91aabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c91aaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c91a908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c9173fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c9173fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03bde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c9173fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (324 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea7f8ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dea7f89e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dea7f8d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6e9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6e9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6e9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6e9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea7f22bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dea7f22a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dea7f078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dea7bb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dea7bb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb6e9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6e9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6e9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea7bb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (325 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlasta_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lasta.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lasta.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlasta_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lasta.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lasta.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlasta_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lasta.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lasta.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlasta_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e232347eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e232344e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e23234862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbb4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbb478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbb4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbb471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2322ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2322dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2322c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e231f71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e231f71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbb471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbb471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbb471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e231f71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (326 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpklo.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpklo.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c705722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c70571fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c70572362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc68f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc68f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc68f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc68f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7056b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7056b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c70569d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c70534ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c70534cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc68f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc68f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc68f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c70534ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (327 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f32( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (328 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, %val.coerce0, %val.coerce1, %val.coerce2, %val.coerce3) #0 { # | entry: # | %val = alloca { , , , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %val.coerce0, 0 # | %1 = insertvalue { , , , } %0, %val.coerce1, 1 # | %2 = insertvalue { , , , } %1, %val.coerce2, 2 # | %3 = insertvalue { , , , } %2, %val.coerce3, 3 # | store { , , , } %3, ptr %val, align 16 # | %val1 = load { , , , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , , , } %val1, ptr %val.addr, align 16 # | %4 = load i32, ptr %base.addr, align 4 # | %5 = load { , , , }, ptr %val.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (329 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c707dc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c707dbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c707dc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9046449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9046449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9046431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c707d57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c707d57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c707d3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7079ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7079ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9046432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90464330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7079eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (330 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb436f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb436f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb436f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8749e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8749ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8749e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8749e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb4368cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb4368ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb436718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb43320e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb43320b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8749e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8749e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8749e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb43320a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560dd9865eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560dd9862e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560dd986662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd34d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd34d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd34d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd34d831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dd97fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560dd97fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560dd97e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560dd948fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560dd948fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd34d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd34d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd34d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dd948fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (332 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (333 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svzero_zt() #0 { # | entry: # | call void @llvm.aarch64.sme.zero.zt(i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005613edb47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613edb44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613edb4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb181049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1810a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb181049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb181031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613edaddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613edadda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613edac28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613ed771e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613ed771b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb181032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1810330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1810330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613ed771a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (334 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.not.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.not.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (335 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/76635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bae8661eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bae865ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bae866262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49a0a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49a0a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49a0a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49a0a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bae85f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bae85f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bae85dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bae828be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bae828bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49a0a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49a0a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49a0a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bae828ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (338 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a14babceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a14bab9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a14babd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d01249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d012a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d01249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d01231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a14ba52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a14ba52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a14ba378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a14b6e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a14b6e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d01232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d012330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d012330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a14b6e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (339 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_812 = alloca <4 x float>, align 16 # | %__s0_812 = alloca <4 x float>, align 16 # | %__s1_812 = alloca <8 x bfloat>, align 16 # | %__s2_812 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <4 x float>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp2 = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0_812, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1_812, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <8 x bfloat> %2, ptr %__s2_812, align 16 # | %3 = load <4 x float>, ptr %__s0_812, align 16 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 16 # | %5 = load <4 x float>, ptr %__s2_812, align 16 # | store <4 x float> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 16 # | %8 = load <4 x float>, ptr %ref.tmp1, align 16 # | store <4 x float> %8, ptr %__ret, align 16 # | %9 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %9, ptr %tmp, align 16 # | %10 = load <4 x float>, ptr %tmp, align 16 # | store <4 x float> %10, ptr %ref.tmp, align 16 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <4 x float> %3, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %15, ptr %__ret.i, align 16 # | %16 = load <4 x float>, ptr %__ret.i, align 16 # | store <4 x float> %16, ptr %__ret_812, align 16 # | %17 = load <4 x float>, ptr %__ret_812, align 16 # | store <4 x float> %17, ptr %tmp2, align 16 # | %18 = load <4 x float>, ptr %tmp2, align 16 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, # | ... # `---data was truncated (10240/54685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558c77c43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c77c40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c77c4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9ef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9ef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9ef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9ef71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c77bd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c77bd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c77bbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c7786de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c7786db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9ef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9ef71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9ef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c7786da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (340 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579a2bbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579a2bbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579a2bc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e3b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e3b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e3b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e3b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579a2b55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579a2b55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579a2b3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579a27e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579a27e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e3b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e3b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e3b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579a27e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (341 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f16( %pg, %op1, half noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005608d93feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608d93fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608d93ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9609333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f960938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9609333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f960931b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608d9394bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608d9394a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608d93798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608d9028e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608d9028b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f960931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f960931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f960931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608d9028a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (342 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bef000feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bef000ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bef001062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf02049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf020a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf02049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf02031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055beeffa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055beeffa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055beeff8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055beefc39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055beefc39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf02032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf020330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf020330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055beefc39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (343 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dd232a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd232a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd232a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5d7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5d718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5d7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5d711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd2323dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd2323da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd232228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd22ed1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd22ed1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5d711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5d711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5d711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd22ed1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (344 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local half @subscript_float16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x half>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x half> %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x float>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32( %a.coerce, i64 0) # | store <16 x float> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x float>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x double>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64( %a.coerce, i64 0) # | store <8 x double> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x double>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000564694bfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564694bf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564694bfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bc0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bc02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bc0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bc0231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564694b91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564694b91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564694b768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564694825e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564694825b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bc0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bc02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bc02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564694825a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (345 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f01983eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f01983be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f01983f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16b7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16b718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16b7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16b711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0197d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0197d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0197b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f019468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f019468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16b711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16b711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16b711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f019468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (347 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load ptr, ptr %carry.addr, align 4 # | %4 = load i32, ptr %3, align 4 # | %5 = shl i32 %4, 29 # | %6 = load i16, ptr %p.addr, align 2 # | %7 = zext i16 %6 to i32 # | %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7) # | %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8) # | %10 = extractvalue { <4 x i32>, i32 } %9, 1 # | %11 = lshr i32 %10, 29 # | %12 = and i32 1, %11 # | store i32 %12, ptr %3, align 4 # | %13 = extractvalue { <4 x i32>, i32 } %9, 0 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, # | ... # `---data was truncated (10240/14775) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055609b794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055609b791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055609b79562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17f481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17f48725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17f481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17f4803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055609b72abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055609b72aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055609b70f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055609b3bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055609b3beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17f4804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17f48050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17f48050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055609b3bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb71855eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb71852e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb7185662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2e8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2e8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2e8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2e8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb717ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb717eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb717d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb7147fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb7147fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2e8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2e8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2e8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb7147fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (349 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_ra # | ... # `---data was truncated (10240/35066) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x00005628b03cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628b03c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628b03cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c88733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c8878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c88733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c8871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628b0361bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628b0361a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628b03468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628afff5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628afff5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c8871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c8871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c8871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628afff5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (350 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cdc4aadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cdc4aaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cdc4aae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f897921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89792725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f897921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8979203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdc4a43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cdc4a43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cdc4a288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cdc46d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cdc46d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8979204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89792050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89792050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdc46d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (351 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (353 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (354 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562f2094ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f20949e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f2094d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0265049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02650a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0265049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0265031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f208e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f208e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f208c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f20576e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f20576b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0265032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02650330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02650330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f20576a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (355 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpkhi.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpkhi.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563632022eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056363201fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056363202362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ec381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ec38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ec381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ec3803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563631fb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563631fb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563631f9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563631c4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563631c4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ec3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ec38050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ec38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563631c4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (356 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (357 of 27910) ******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default,default' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.wrapper = type { %struct.task } # | %struct.task = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" } # | %"struct.std::coroutine_handle.0" = type { ptr } # | %"struct.task::promise_type" = type { i8 } # | %"struct.std::suspend_always" = type { i8 } # | # | $_ZN4task12promise_type17get_return_objectEv = comdat any # | # | $_ZN4task12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN4task12promise_type11return_voidEv = comdat any # | # | $_ZN4task12promise_type13final_suspendEv = comdat any # | # | $_ZN7wrapperC1EO4task = comdat any # | # | $_ZN4taskD1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZN7wrapperC2EO4task = comdat any # | # | $_ZN4taskC1EOS_ = comdat any # | # | $_ZN4taskC2EOS_ = comdat any # | # | $_ZNSt16coroutine_handleIvEaSEDn = comdat any # | # | $_ZN4taskD2Ev = comdat any # | # | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any # | # | ; Function Attrs: mustprogress nounwind presplitcoroutine # | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %gro.active = alloca i1, align 1 # | %__promise = alloca %"struct.task::promise_type", align 1 # | %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6 # | %ref.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %ref.tmp2 = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1 # | store ptr %agg.result, ptr %result.ptr, align 8 # | %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null) # | %1 = call i1 @llvm.coro.alloc(token %0) # | br i1 %1, label %coro.alloc, label %coro.init # | # | coro.alloc: ; preds = %entry # | %2 = call i64 @llvm.coro.size.i64() # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14 # | br label %coro.init # | # | coro.init: ; preds = %coro.alloc, %entry # | %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ] # | %4 = call ptr @llvm.coro.begin(token %0, ptr %3) # | store i1 false, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %__promise) #9 # | call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9 # | call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | store i1 true, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9 # | call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br i1 %call1, label %init.ready, label %init.suspend # | # | init.suspend: ; preds = %coro.init # | %5 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9 # | %6 = call i8 @llvm.coro.suspend(token %5, i1 false) # | switch i8 %6, label %pre.gvo.conv [ # | i8 0, label %init.ready # | i8 1, label %init.cleanup # | ] # | # | init.cleanup: ; preds = %init.suspend # | br label %cleanup # | # | init.ready: ; preds = %init.suspend, %coro.init # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br label %cleanup # | # | cleanup: ; preds = %init.ready, %init.cleanup # | %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9 # | switch i32 %cleanup.dest.slot.0, label %unreachable [ # | i32 0, label %cleanup.cont # | i32 2, label %coro.cleanup # | ] # | # | cleanup.cont: ; preds = %cleanup # | call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | br label %coro.final # | # | coro.final: ; preds = %cleanup.cont # | call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9 # | call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br i1 %call4, label %final.ready, label %final.suspend # | # | final.suspend: ; preds = %coro.final # | %7 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9 # | %8 = call i8 @llvm.coro.suspend(token %7, i1 true) # | switch i8 %8, label %pre.gvo.conv [ # | i8 0, label %final.ready # | i8 1, label %final.cleanup # | ] # | # | final.cleanup: ; preds = %final.suspend # | br label %cleanup5 # | # | final.ready: ; preds = %final.suspend, %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br label %cleanup5 # | # | cleanup5: ; preds = %final.ready, %final.cleanup # | %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9 # | switch i32 %cleanup.dest.slot.1, label %unreachable [ # | i32 0, label %pre.gvo.conv # | i32 2, label %coro.cleanup # | ] # | # | pre.gvo.conv: ; preds = %cleanup5, %final.suspend, %init.suspend # | %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ] # | %InRamp = call i1 @llvm.coro.is_in_ramp() # | br i1 %InRamp, label %gro.conv, label %after.gro.conv # | # | gro.conv: ; preds = %pre.gvo.conv # | call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9 # | %cleanup.is_active = load i1, ptr %gro.active, align 1 # | br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done # | # | cleanup.action: ; preds = %gro.conv # | call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9 # | br label %cleanup.done # | # | cleanup.done: ; preds = %cleanup.action, %gro.conv # | br label %after.gro.conv # | # | after.gro.conv: ; preds = %cleanup.done, %pre.gvo.conv # | br i1 %9, label %cleanup.cont7, label %coro.ret # | # | cleanup.cont7: ; preds = %after.gro.conv # | br label %coro.cleanup # | # | coro.cleanup: ; preds = %cleanup.cont7, %cleanup5, %cleanup # | call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9 # | call void @llvm.lifetime.end.p0(ptr %__promise) #9 # | %10 = call ptr @llvm.coro.free(token %0, ptr %4) # | %11 = icmp ne ptr %10, null # | br i1 %11, label %coro.free, label %after.coro.free # | # | coro.free: ; preds = %coro.cleanup # | %12 = call i64 @llvm.coro.size.i64() # | call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9 # | br label %after.coro.free # | # | after.coro.free: ; preds = %coro.cleanup, %coro.free # | call void @llvm.coro.dead(ptr %4) # | br label %coro.ret # | # | coro.ret: ; preds = %after.coro.free, %after.gro.conv # | call void @llvm.coro.end(ptr null, i1 false, token none) # | ret void # | # | unreachable: ; preds = %cleanup5, %cleanup # | unreachable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1 # | # | ; Function Attrs: nounwind memory(none) # | declare i1 @llvm.coro.alloc(token) #2 # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #3 # | # | ; Function Attrs: nounwind memory(none) # | declare i64 @llvm.coro.size.i64() #2 # | # | ; Function Attrs: nounwind memory(argmem: readwrite) # | declare ptr @llvm.coro.begin(token, ptr writeonly) #4 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5 # | # | ; Function Attrs: mustprogress nounwind # | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %this.addr = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | store ptr %agg.result, ptr %result.ptr, align 8 # | store ptr %this, ptr %this.addr, align 8, !tbaa !7 # | %this1 = load ptr, ptr %this.addr, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"s # | ... # `---data was truncated (10240/31146) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default,default' -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default,default -S # | #0 0x000055b967658eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b967655e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b96765962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f10333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f1038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f10333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f1031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9675eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9675eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9675d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b967282e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b967282b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f1031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f1031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f1031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b967282a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (358 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.rdffr() # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr_z( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call @llvm.aarch64.sve.rdffr.z( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr.z() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000564eae3f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eae3f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eae3f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b4941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b494725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b4941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b49403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eae38bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eae38ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eae3708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564eae01fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564eae01fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b49404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b494050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b494050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eae01fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (359 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, , , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | ... # `---data was truncated (10240/24605) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055dd4a3aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd4a3a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd4a3ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f888f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f888f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f888f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f888f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd4a340bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd4a340a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd4a3258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd49fd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd49fd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f888f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f888f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f888f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd49fd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (360 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563a15ef4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a15ef1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a15ef562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efccbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efccbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efccbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efccbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a15e8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a15e8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a15e6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a15b1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a15b1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efccbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efccbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efccbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a15b1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (361 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564b83d2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b83d2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b83d3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f5c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f5c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f5c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f5c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b83cc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b83cc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b83caa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b83959e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b83959b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f5c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f5c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f5c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b83959a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (363 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005627e3be4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627e3be1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627e3be562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dd2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dd2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dd2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dd2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627e3b7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627e3b7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627e3b5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627e380ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627e380eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dd2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dd2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dd2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627e380ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (364 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store # | ... # `---data was truncated (10240/17826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557228224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557228221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055722822562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f989df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f989df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f989df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f989df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572281babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572281baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055722819f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557227e4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557227e4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f989df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f989df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f989df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557227e4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (365 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4b7bfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4b7bf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4b7bfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99bc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4b7b92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4b7b92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4b7b778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4b7826e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4b7826b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4b7826a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (367 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (368 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055673454aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556734547e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055673454b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed3c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed3c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed3c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed3c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567344e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567344e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567344c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556734174e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556734174b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed3c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed3c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed3c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556734174a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (370 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f54a9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f54a9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f54a9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7ae649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7ae6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7ae649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7ae631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f54a33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f54a33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f54a188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f546c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f546c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7ae632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7ae6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7ae6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f546c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (371 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005595a6d64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595a6d61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595a6d6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0cfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0cfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0cfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0cfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595a6cfabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595a6cfaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595a6cdf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595a698ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595a698eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0cfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0cfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0cfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595a698ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (372 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv. # | ... # `---data was truncated (10240/17879) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5419f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5419f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5419f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f164d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f164d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f164d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f164d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e54198cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e54198ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5419718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e541620e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e541620b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f164d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f164d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f164d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e541620a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (373 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 0 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555572919eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555572916e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055557291a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f404ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f404ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f404ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f404ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555728afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555728afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555728948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555572543e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555572543b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f404ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f404ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f404ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555572543a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (374 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalb_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005652b7299eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652b7296e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652b729a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f622bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f622bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f622bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f622bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652b722fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652b722fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652b72148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652b6ec3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652b6ec3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f622bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f622bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f622bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652b6ec3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (375 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae65d2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae65d2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae65d3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9201b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9201b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9201b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9201b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae65cc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae65cc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae65caa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae65959e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae65959b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9201b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9201b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9201b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae65959a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (376 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (377 of 27910) ******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | %struct.S = type { ptr, ptr } # | %struct.T = type { [2 x ptr] } # | %struct.SS = type { ptr } # | # | @__hip_cuid_ = addrspace(1) global i8 0 # | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4 # | %1 = load i32, ptr %0, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 { # | entry: # | %x.addr = alloca ptr addrspace(2), align 8, addrspace(5) # | %y.addr = alloca ptr addrspace(1), align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr # | store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8 # | store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8 # | %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0 # | %1 = load i32, ptr addrspace(2) %arrayidx, align 4 # | %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8 # | %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0 # | store i32 %1, ptr addrspace(1) %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline nounwind # | define dso_local void @_Z4funcPi(ptr noundef %x) #1 { # | entry: # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr %x, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 { # | entry: # | %s = alloca %struct.S, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %s.ascast = addrspacecast ptr addrspace(5) %s to ptr # | %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1 # | %3 = load ptr, ptr %y, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %4, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 { # | entry: # | %s = alloca ptr, align 8, addrspace(5) # | %s.addr = alloca ptr, align 8, addrspace(5) # | %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr # | store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8 # | %s1 = load ptr, ptr addrspace(5) %s, align 8 # | store ptr %s1, ptr %s.addr.ascast, align 8 # | %0 = load ptr, ptr %s.addr.ascast, align 8 # | %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %3 = load ptr, ptr %s.addr.ascast, align 8 # | %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1 # | %4 = load ptr, ptr %y, align 8 # | %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0 # | %5 = load float, ptr %arrayidx2, align 4 # | %add = fadd contract float %5, 1.000000e+00 # | store float %add, ptr %arrayidx2, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 { # | entry: # | %t = alloca %struct.T, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %t.ascast = addrspacecast ptr addrspace(5) %t to ptr # | %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0 # | %1 = load ptr, ptr %arrayidx, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0 # | %2 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %2, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1 # | %3 = load ptr, ptr %arrayidx3, align 8 # | %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx4, align 4 # | %add5 = fadd contract float %4, 2.000000e+00 # | store float %add5, ptr %arrayidx4, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 { # | entry: # | %a = alloca %struct.SS, align 8, addrspace(5) # | %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0 # | store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8 # | %a.ascast = addrspacecast ptr addrspace(5) %a to ptr # | %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0 # | %0 = load ptr, ptr %x, align 8 # | %1 = load float, ptr %0, align 4 # | %add = fadd contract float %1, 3.000000e+00 # | store float %add, ptr %0, align 4 # | ret void # | } # | # | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !2 = !{!"clang version 24.0.0"} # | !3 = !{} # | !4 = !{i64 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x000055e24d923eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e24d920e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e24d92462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c1e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c1e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c1e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c1e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e24d8b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e24d8b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e24d89e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e24d54de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e24d54db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c1e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c1e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c1e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e24d54da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (378 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (379 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/16804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556a0cda3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a0cda0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a0cda462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8352c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8352ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8352c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8352c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a0cd39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a0cd39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a0cd1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a0c9cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a0c9cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8352c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8352c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8352c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a0c9cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (380 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb4b8aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb4b8abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb4b8af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7143933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f714398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7143933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f714391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb4b844bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb4b844a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb4b8298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb4b4d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb4b4d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f714391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f714391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f714391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb4b4d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (381 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (382 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %2, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | # | ... # `---data was truncated (10240/178306) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f8a567aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8a5677e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8a567b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa432533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa43258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa432533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa43251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8a5610bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8a5610a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8a55f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8a52a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8a52a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa43251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa43251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa43251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8a52a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (383 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b8( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.vector.reverse.nxv16i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b16( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b32( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b64( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8bf16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005608372edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608372eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608372ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe378a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe378aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe378a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe378a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560837283bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560837283a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608372688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560836f17e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560836f17b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe378a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe378a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe378a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560836f17a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (384 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, # | ... # `---data was truncated (10240/69839) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561050332eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056105032fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056105033362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ca421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ca42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ca421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ca4203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610502c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610502c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610502ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056104ff5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056104ff5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ca4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ca42050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ca42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056104ff5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmac # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055799c3c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055799c3c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055799c3c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc5c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc5c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc5c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc5c603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055799c35dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055799c35da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055799c3428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055799bff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055799bff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc5c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc5c6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc5c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055799bff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (386 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/135111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7602b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7602b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7602b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2afa81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2afa8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2afa81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2afa803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d76024dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d76024da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7602328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d75fee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d75fee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2afa804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2afa8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2afa8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d75fee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load < # | ... # `---data was truncated (10240/14421) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6379c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6379bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6379c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1828333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f182838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1828333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f182831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a637957bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a637957a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a63793c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6375ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6375ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f182831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f182831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f182831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6375eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (388 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (389 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 4) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 5) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4f32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2f64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8bf16( %0, %1, i32 6) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, # | ... # `---data was truncated (10240/11061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005579f5fdfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579f5fdce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579f5fe062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f893321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89332725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f893321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8933203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579f5f75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579f5f75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579f5f5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579f5c09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579f5c09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8933204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89332050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89332050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579f5c09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (390 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.ad # | ... # `---data was truncated (10240/17434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055559443beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555594438e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055559443c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ad261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ad26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ad261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ad2603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555943d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555943d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555943b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555594065e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555594065b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ad2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ad26050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ad26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555594065a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (391 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005562b6c18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562b6c15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562b6c1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60fba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60fba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60fba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60fba03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562b6baebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562b6baea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562b6b938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562b6842e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562b6842b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60fba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60fba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60fba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562b6842a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (392 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , # | ... # `---data was truncated (10240/93119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560db8fe7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560db8fe4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560db8fe862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560db8f7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560db8f7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560db8f628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560db8c11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560db8c11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febf411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560db8c11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (393 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c330167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c330164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c33016862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa480333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa48038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa480333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa48031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3300fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3300fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3300e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c32fd91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c32fd91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa48031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa48031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa48031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c32fd91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (394 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s16_s16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u16_u16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (395 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055b5db412eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5db40fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5db41362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6788d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6788d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6788d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6788d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5db3a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5db3a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5db38d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5db03ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5db03cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6788d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6788d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6788d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5db03ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nof # | ... # `---data was truncated (10240/11966) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f20170eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f2016de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f2017162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2648f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2648f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2648f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2648f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f20106bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f20106a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f200eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f1fd9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f1fd9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2648f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2648f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2648f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f1fd9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-fma.c (397 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %sub.i = fsub <4 x float> %3, %mul.i # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %sub.i = fsub <2 x float> %3, %mul.i # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_68 = alloca <2 x float>, align 8 # | %__s0_68 = alloca <2 x float>, align 8 # | %__s1_68 = alloca <2 x float>, align 8 # | %__s2_68 = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp1 = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0_68, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_68, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_68, align 8 # | %3 = load <2 x float>, ptr %__s0_68, align 8 # | %4 = load <2 x float>, ptr %__s1_68, align 8 # | %5 = load <2 x float>, ptr %__s2_68, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | %mul = fmul <2 x float> %4, %10 # | %add = fadd <2 x float> %3, %mul # | store <2 x float> %add, ptr %__ret_68, align 8 # | %11 = load <2 x float>, ptr %__ret_68, align 8 # | store <2 x float> %11, ptr %tmp1, align 8 # | %12 = load <2 x float>, ptr %tmp1, align 8 # | ret <2 x float> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_58 = alloca <4 x float>, align 16 # | %__s0_58 = alloca <4 x float>, align 16 # | %__s1_58 = alloca <4 x float>, align 16 # | %__s2_58 = alloca <2 x float>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp1 = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__s0_58, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_58, align 16 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_58, align 8 # | %3 = load <4 x float>, ptr %__s0_58, align 16 # | %4 = load <4 x float>, ptr %__s1_58, align 16 # | %5 = load <2 x float>, ptr %__s2_58, align 8 # | store <2 x f # | ... # `---data was truncated (10240/44730) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561ccaee5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ccaee2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ccaee662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f989b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f989b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f989b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f989b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ccae7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ccae7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ccae608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ccab0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ccab0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f989b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f989b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f989b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ccab0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (399 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_mf8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_bf16() #0 { # | entry: # | ret undef # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564b35143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b35140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b3514462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54bb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54bb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54bb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54bb831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b350d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b350d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b350be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b34d6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b34d6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54bb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54bb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54bb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b34d6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (400 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005631152a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056311529fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631152a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44f2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44f278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44f2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44f271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563115238bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563115238a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056311521d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563114ecce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563114eccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44f271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44f271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44f271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563114ecca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (401 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628496b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628496afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628496b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cd5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cd5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cd5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cd5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562849648bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562849648a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056284962d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628492dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628492dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cd5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cd5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cd5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628492dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (402 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e11f857eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e11f854e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e11f85862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6da905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6da95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6da905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6da8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e11f7edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e11f7eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e11f7d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e11f481e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e11f481b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6da8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6da8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6da8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e11f481a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (403 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ef7fcf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef7fcefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef7fcf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9d9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9d94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9d9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9d9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef7fc88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef7fc88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef7fc6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef7f91ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef7f91cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9d9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9d94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9d94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef7f91ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (404 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (405 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f93cec5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f93cec2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f93cec662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9828a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9828a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9828a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9828a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f93ce5bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f93ce5ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f93ce408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f93caefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f93caefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9828a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9828a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9828a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f93caefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (406 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560173972eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056017396fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056017397362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d8aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d8aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d8aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d8aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560173908bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560173908a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601738ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056017359ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056017359cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d8aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d8aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d8aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056017359ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.v # | ... # `---data was truncated (10240/58683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652243f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652243f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652243f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa28401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2840725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa28401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa284003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056522438ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056522438ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652243738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565224022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565224022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa284004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2840050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2840050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565224022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (408 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564754ad0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564754acde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564754ad162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f804d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f804d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f804d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f804d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564754a66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564754a66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564754a4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647546fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647546fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f804d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f804d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f804d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647546faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2 # | ... # `---data was truncated (10240/94673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626f131deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626f131ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626f131e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc81da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc81da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc81da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc81da03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626f12b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626f12b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626f12988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626f0f47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626f0f47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc81da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc81da050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc81da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626f0f47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (410 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (411 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/54480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056167f935eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056167f932e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056167f93662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d7f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d7f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d7f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d7f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056167f8cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056167f8cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056167f8b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056167f55fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056167f55fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d7f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d7f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d7f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056167f55fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (412 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562139114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562139111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056213911562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ef3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ef395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ef3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ef38ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621390aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621390aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056213908f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562138d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562138d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ef38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ef38ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ef38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562138d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (413 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 # | ... # `---data was truncated (10240/14429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f88f529eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f88f526e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f88f52a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabc7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabc7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabc7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabc7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f88f4bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f88f4bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f88f4a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f88f153e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f88f153b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fabc7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabc7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabc7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f88f153a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (414 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | d # | ... # `---data was truncated (10240/14679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556b754ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b754cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b754cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc34933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc3498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc34933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc3491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b75464bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b75464a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b754498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b750f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b750f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc3491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc3491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc3491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b750f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (415 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (416 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_int16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_uint16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_int32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_uint32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_int64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_uint64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @subscript_float16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @subscript_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @subscript_float64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecins = insertelement %1, float 1.000000e+00, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %2 = load , ptr %a.addr, align 16 # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_read_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecext = extractelement %1, i64 %0 # | %add = fadd float %vecext, 1.000000e+00 # | %2 = load , ptr %a.addr, align 16 # | %vecins = insertelement %2, float %add, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %3 = load , ptr %a.addr, align 16 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000563d083eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d083ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d083ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13cc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13cc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13cc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13cc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d08384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d08384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d083698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d08018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d08018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13cc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13cc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13cc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d08018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (417 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, al # | ... # `---data was truncated (10240/12168) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560c1f3f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c1f3f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c1f3f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58d5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58d5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58d5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58d5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c1f38ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c1f38ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c1f3738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c1f022e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c1f022b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58d5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58d5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58d5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c1f022a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (418 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f3a6710eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3a670de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3a671162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4651f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4651f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4651f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4651eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3a66a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3a66a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3a668b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3a633ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3a633ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4651eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4651eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4651eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3a633aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (420 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563fc51e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fc51dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fc51e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa598b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa598b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa598b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa598b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fc5176bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fc5176a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fc515b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fc4e0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fc4e0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa598b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa598b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa598b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fc4e0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (421 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__p2.addr.i3 = alloca <4 x half>, align 8 # | %__ret.i4 = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i1, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8 # | store <4 x half> %5, ptr %__p2.addr.i3, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %13, ptr %__ret.i4, align 8 # | %14 = load <4 x half>, ptr %__ret.i4, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__p1.addr.i2 = alloca <8 x half>, align 16 # | %__p2.addr.i3 = alloca <8 x half>, align 16 # | %__ret.i4 = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i1, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16 # | store <8 x half> %5, ptr %__p2.addr.i3, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %13, ptr %__ret.i4, align 16 # | %14 = load <8 x half>, ptr %__ret.i4, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <4 x half>, ptr %__s0, align 8 # | %4 = load <4 x half>, ptr %__s1, align 8 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <4 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %9 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %3, ptr %__p0.addr.i, align 8 # | store <4 x half> %4, ptr %__p1.addr.i, align 8 # | store <4 x half> %9, ptr %__p2.addr.i, align 8 # | %10 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %13 = bitcast <8 x i8> %10 to <4 x half> # | %14 = bitcast <8 x i8> %11 to <4 x half> # | %15 = bitcast <8 x i8> %12 to <4 x half> # | %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13) # | store <4 x half> %16, ptr %ref.tmp.i, align 8 # | %17 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %17, ptr %__ret.i, align 8 # | %18 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %18, ptr %__ret, align 8 # | %19 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %19, ptr %tmp, align 8 # | %20 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %20 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store half %c, ptr %c.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <8 x half>, ptr %__s0, align 16 # | %4 = load <8 x half>, ptr %__s1, align 16 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <8 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3 # | %9 = load half, ptr %__s2, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4 # | %10 = load half, ptr %__s2, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5 # | %11 = load half, ptr %__s2, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6 # | %12 = load half, ptr %__s2, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %13 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %3, ptr %__p0.addr.i, align 16 # | store <8 x half> %4, ptr %__p1.addr.i, align 16 # | store <8 x half> %13, ptr %__p2.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %15 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %16 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %17 = bitcast <16 x i8> %14 to <8 x half> # | %18 = bitcast <16 x i8> %15 to <8 x half> # | %19 = bitcast <16 x i8> %16 to <8 x half> # | %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17) # | store <8 x half> %20, ptr %ref.tmp.i, align 16 # | %21 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %21, ptr %__ret.i, align 16 # | %22 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %22, ptr %__ret, align 16 # | %23 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %23, ptr %tmp, align 16 # | %24 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half # | ... # `---data was truncated (10240/31903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f6ac6e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6ac6e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6ac6ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0d521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0d52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0d521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0d5203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6ac67fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6ac67fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6ac6648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6ac313e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6ac313b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0d5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0d52050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0d52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6ac313a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (422 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b075e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b075e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b075ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b0757fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b0757fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b075648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b07213e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b07213b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6f1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b07213a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (423 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d9d0ef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9d0eefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9d0ef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f24933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f2498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f24933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f2491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9d0e88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9d0e88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9d0e6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9d0b1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9d0b1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f2491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f2491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f2491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9d0b1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/48385) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561679146eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561679143e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056167914762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb52221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5222725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb52221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb522203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616790dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616790dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616790c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561678d70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561678d70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb522204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5222050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5222050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561678d70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (425 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005589248daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589248d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589248db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e55c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e55c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e55c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e55c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558924870bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558924870a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589248558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558924504e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558924504b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e55c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e55c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e55c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558924504a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (426 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb.lane(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt.lane(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fdd57e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdd57e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdd57e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf45a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf45aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf45a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf45a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdd577dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdd577da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdd57628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdd5411e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdd5411b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf45a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf45a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf45a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdd5411a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (427 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb857bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb857bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb857c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83f1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83f16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83f1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83f1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb85755bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb85755a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb8573a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb853e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb853e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83f1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83f16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83f16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb853e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (429 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | d # | ... # `---data was truncated (10240/75038) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561d575edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d575eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d575ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22fc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22fc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22fc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22fc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d57583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d57583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d575688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d57217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d57217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22fc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22fc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22fc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d57217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (430 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e9c1d51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9c1d4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9c1d5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7bc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7bc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7bc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7bc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9c1ce7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9c1ce7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9c1ccc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9c197be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9c197bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7bc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7bc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7bc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9c197ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (432 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde # | ... # `---data was truncated (10240/16083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a0a60deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a0a60ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a0a60e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f140301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14030725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f140301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1403003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a0a5a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a0a5a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a0a5888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a0a237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a0a237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1403004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14030050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14030050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a0a237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (433 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # | #0 0x000055f7207d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7207d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7207d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa21249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa21249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa21231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f72076abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f72076aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f72074f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7203fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7203feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa21232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa212330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7203fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (434 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u8_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s8_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s16_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u32_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s32_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u64_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f16_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_bf16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f32_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u64( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s64( %v) #2 { # | entry: # | % # | ... # `---data was truncated (10240/13584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bfa8cf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfa8cf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfa8cfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87d8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87d80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87d8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87d8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfa8c8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfa8c8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfa8c748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfa8923e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfa8923b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87d8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87d80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87d80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfa8923a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (435 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.i32f16( %0, %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (436 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055673a302eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055673a2ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055673a30362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8476d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8476d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8476d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8476d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055673a298bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055673a298a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055673a27d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556739f2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556739f2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8476d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8476d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8476d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556739f2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (437 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa8aa14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa8aa11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa8aa1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14d2e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14d2e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14d2e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14d2e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa8a9aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa8a9aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa8a98f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa8a63ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa8a63eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14d2e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14d2e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14d2e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa8a63ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv # | ... # `---data was truncated (10240/83637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616dabeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616dabe9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616dabed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecf1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecf16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecf1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecf1631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616dab82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616dab82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616dab678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616da816e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616da816b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecf1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecf16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecf16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616da816a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (441 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005612491d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612491d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612491d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44a4705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44a475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44a4705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44a46ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056124916abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056124916aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056124914f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561248dfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561248dfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44a46eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44a46ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44a46ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561248dfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (442 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl.i = bitcast <8 x i8> %3 to <4 x i16> # | %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16> # | %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16> # | %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <4 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <4 x i16> %6, %vbsl2.i # | %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <4 x i16> %vbsl5.i to <4 x half> # | store <4 x half> %7, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbsl.i = bitcast <16 x i8> %3 to <8 x i16> # | %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16> # | %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16> # | %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <8 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <8 x i16> %6, %vbsl2.i # | %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <8 x i16> %vbsl5.i to <8 x half> # | store <8 x half> %7, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef # | ... # `---data was truncated (10240/31986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056156aac9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056156aac6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056156aaca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2771e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2771ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2771e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2771e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056156aa5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056156aa5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056156aa448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056156a6f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056156a6f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2771e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2771e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2771e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056156a6f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c1840aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c18407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c1840b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3536249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35362a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3536249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3536231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c183a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c183a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c183858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c18034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c18034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3536232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35362330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35362330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c18034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (445 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (446 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055afd3203eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afd3200e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afd320462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fbdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fbdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fbdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fbdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afd3199bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afd3199a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afd317e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afd2e2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afd2e2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5fbdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fbdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fbdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afd2e2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (447 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055df50a67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df50a64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df50a6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcd4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcd44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcd4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcd4431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df509fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df509fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df509e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df50691e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df50691b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcd4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcd44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcd44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df50691a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (448 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b1f40a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1f40a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1f40a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4c3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4c36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4c3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4c3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1f4039bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1f4039a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1f401e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1f3ccde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1f3ccdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4c3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4c36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4c36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1f3ccda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e9c580eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e9c57de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e9c58162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49ae449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49ae4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49ae449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49ae431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e9c516bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e9c516a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e9c4fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e9c1aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e9c1aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49ae432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49ae4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49ae4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e9c1aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (450 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_f16_f16( # | ... # `---data was truncated (10240/27272) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056272708beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562727088e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056272708c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27d4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27d4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27d4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27d4eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562727021bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562727021a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627270068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562726cb5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562726cb5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27d4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27d4eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27d4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562726cb5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (451 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d5f300feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5f300ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5f301062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7761533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f776158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7761533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f776151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5f2fa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5f2fa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5f2f8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5f2c39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5f2c39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f776151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f776151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f776151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5f2c39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0abe76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0abe73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0abe7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44b4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44b4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44b4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44b4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0abe0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0abe0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0abdf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0abaa0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0abaa0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44b4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44b4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44b4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0abaa0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (453 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba58117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba58114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba5811862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc05e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc05e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc05e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc05e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba580adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba580ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba580928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba57d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba57d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc05e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc05e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc05e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba57d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (454 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_0( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_1( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564ef5ac3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ef5ac0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ef5ac462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa64d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa64d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa64d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa64ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef5a59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ef5a59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ef5a3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ef56ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ef56edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa64ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa64cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa64cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef56eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (455 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d5722f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5722f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5722f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5fb305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5fb35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5fb305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5fb2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d57228abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d57228aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d57226f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d571f1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d571f1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff5fb2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5fb2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5fb2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d571f1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (456 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eff8c7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eff8c78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eff8c7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2840105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f284015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2840105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28400ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eff8c11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eff8c11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eff8bf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eff88a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eff88a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28400eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28400ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28400ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eff88a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (457 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd9c7a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd9c79fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd9c7a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd909849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9098a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd909849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd909831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd9c738bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd9c738a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd9c71d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd9c3cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd9c3ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd909832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9098330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9098330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd9c3cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (458 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_bf16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptra # | ... # `---data was truncated (10240/10361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560b5157eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b5157be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b5157f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b2b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b2b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b2b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b2b231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b51514bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b51514a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b514f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b511a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b511a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b2b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b2b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b2b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b511a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (459 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_u8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s16_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (460 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (462 of 27910) ******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x half> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x float> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x double> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x bfloat> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000555d97733eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d97730e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d9773462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2842449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2842449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2842431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d976c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d976c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d976ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d9735de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d9735db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2842432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28424330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d9735da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (463 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a5543a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5543a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5543aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a57831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a55433fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a55433fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5543248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a553fd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a553fd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a553fd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (464 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603d5137eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603d5134e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603d513862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feacf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feacf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feacf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feacf831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603d50cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603d50cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603d50b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603d4d61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603d4d61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feacf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feacf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feacf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603d4d61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (465 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000564276cb2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564276cafe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564276cb362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfd6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfd6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfd6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfd6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564276c48bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564276c48a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564276c2d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642768dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642768dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfd6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfd6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfd6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642768dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (466 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a616fe7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a616fe4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a616fe862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9326533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f932658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9326533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f932651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a616f7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a616f7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a616f628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a616c11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a616c11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f932651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f932651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f932651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a616c11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c33ff91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c33ff8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c33ff9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb97bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb97bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb97bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb97bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c33ff27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c33ff27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c33ff0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c33fbbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c33fbbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb97bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb97bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb97bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c33fbbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (468 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592402c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592402bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592402c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87f0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87f04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87f0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87f0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559240257bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559240257a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055924023c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055923feebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055923feebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f87f0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87f04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87f04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055923feeba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i # | ... # `---data was truncated (10240/14788) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cb8f3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cb8f37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cb8f3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1673c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1673ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1673c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1673c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cb8ed0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cb8ed0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cb8eb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cb8b64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cb8b64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1673c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1673c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1673c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cb8b64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (470 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055adef225eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055adef222e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055adef22662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb540049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5400a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb540049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb540031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adef1bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055adef1bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055adef1a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055adeee4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055adeee4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb540032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5400330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5400330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adeee4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llv # | ... # `---data was truncated (10240/59779) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559734afeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559734afbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559734aff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f903ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f903ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f903ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f903ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559734a94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559734a94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559734a798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559734728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559734728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f903ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f903ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f903ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559734728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/424041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c80bc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c80bbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c80bc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9d0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c80b57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c80b57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c80b3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c807ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c807ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c807eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (473 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/recps.c (474 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000563719abdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563719abae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563719abe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f690df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f690df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f690df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f690df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563719a53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563719a53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563719a388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637196e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637196e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f690df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f690df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f690df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637196e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (475 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to double # | %7 = bitcast <8 x i8> %4 to double # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %extract = extractelement <2 x double> %8, i32 0 # | %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | %10 = bitcast double %9 to <1 x double> # | store <1 x double> %10, ptr %ref.tmp, align 8 # | %11 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %11, ptr %__ret, align 8 # | %12 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %12, ptr %tmp, align 8 # | %13 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %13 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__s0, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1, align 16 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> # | %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %9, ptr %ref.tmp, align 16 # | %10 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %10, ptr %__ret, align 16 # | %11 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %11, ptr %tmp, align 16 # | %12 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load float, ptr %__s0, align 4 # | %4 = load float, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %5, i32 1 # | %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store float %6, ptr %ref.tmp, align 4 # | %7 = load float, ptr %ref.tmp, align 4 # | store float %7, ptr %__ret, align 4 # | %8 = load float, ptr %__ret, align 4 # | store float %8, ptr %tmp, align 4 # | %9 = load float, ptr %tmp, align 4 # | ret float %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055597dc44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055597dc41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055597dc4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa178849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa178849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa178831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055597dbdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055597dbdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055597dbbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055597d86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055597d86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa178832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1788330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055597d86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (476 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpa_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpa.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpa.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563982c79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563982c76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563982c7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2735c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2735c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2735c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2735c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563982c0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563982c0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563982bf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639828a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639828a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2735c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2735c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2735c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639828a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (477 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/65883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635e1abfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635e1abce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635e1ac062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d01249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d012a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d01249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d01231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635e1a55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635e1a55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635e1a3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635e16e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635e16e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d01232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d012330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d012330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635e16e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 nou # | ... # `---data was truncated (10240/27442) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056125344beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561253448e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056125344c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbdb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbdb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbdb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbdb831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612533e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612533e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612533c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561253075e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561253075b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbdb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbdb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbdb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561253075a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (479 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fd450eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fd450be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fd450f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a6ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a6ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a6ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a6ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fd44a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fd44a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fd44898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fd4138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fd4138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a6ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a6ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a6ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fd4138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (480 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv8f16(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cbdef61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbdef5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbdef6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febe5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febe56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febe5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febe5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbdeef7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbdeef7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbdeedc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbdeb8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbdeb8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febe5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febe56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febe56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbdeb8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/nand.c (481 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnand_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nand.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nand.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000555583830eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055558382de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055558383162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc43bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc43bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc43bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc43bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555837c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555837c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555837ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055558345ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055558345ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc43bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc43bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc43bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055558345aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/perm.c (482 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, # | ... # `---data was truncated (10240/231562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055b520144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b520141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b52014562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0a5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0a518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0a5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0a511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5200dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5200daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5200bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b51fd6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b51fd6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0a511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0a511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0a511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b51fd6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/builtins-riscv.c (483 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 10, ptr %res, align 4 # | store volatile i32 11, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f7d9abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f7d9a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f7d9ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90ec449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90ec4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90ec449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90ec431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f7d941bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f7d941a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f7d9268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f7d5d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f7d5d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90ec432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90ec4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90ec4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f7d5d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (484 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6) # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <4 x float> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load <4 x float>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 16 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %10, ptr %__ret.i, align 16 # | %11 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %c.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6) # | store <2 x double> %9, ptr %ref.tmp.i, align 16 # | %10 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %10, ptr %__ret.i, align 16 # | %11 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x float> # | %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> # | %fmla = bitcast <8 x i8> %4 to <2 x float> # | %fmla1 = bitcast <8 x i8> %3 to <2 x float> # | %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1) # | store <2 x float> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Functio # | ... # `---data was truncated (10240/80179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055aa537dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa537d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa537dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f332981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33298725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f332981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3329803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa53771bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa53771a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa537568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa53405e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa53405b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3329804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33298050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33298050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa53405a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (485 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_scatter_u32base_s32( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(, , , i64) # # | ... # `---data was truncated (10240/43213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055cba4e5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cba4e59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cba4e5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f878f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f878f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f878f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f878f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cba4df2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cba4df2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cba4dd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cba4a86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cba4a86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f878f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f878f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f878f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cba4a86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630f0ef2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630f0eefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630f0ef362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe94d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe94d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe94d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe94d631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630f0e88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630f0e88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630f0e6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630f0b1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630f0b1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe94d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe94d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe94d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630f0b1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (487 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (488 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_72 = alloca <4 x i16>, align 8 # | %__s0_72 = alloca <4 x i16>, align 8 # | %__s1_72 = alloca <4 x i16>, align 8 # | %__s2_72 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_72, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_72, align 8 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_72, align 8 # | %3 = load <4 x i16>, ptr %__s0_72, align 8 # | %4 = load <4 x i16>, ptr %__s1_72, align 8 # | %5 = load <4 x i16>, ptr %__s2_72, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_72, align 8 # | %11 = load <4 x i16>, ptr %__ret_72, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_62 = alloca <8 x i16>, align 16 # | %__s0_62 = alloca <8 x i16>, align 16 # | %__s1_62 = alloca <8 x i16>, align 16 # | %__s2_62 = alloca <4 x i16>, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_62, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_62, align 16 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_62, align 8 # | %3 = load <8 x i16>, ptr %__s0_62, align 16 # | %4 = load <8 x i16>, ptr %__s1_62, align 16 # | %5 = load <4 x i16>, ptr %__s2_62, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | %mul = mul <8 x i16> %4, %10 # | %add = add <8 x i16> %3, %mul # | store <8 x i16> %add, ptr %__ret_62, align 16 # | %11 = load <8 x i16>, ptr %__ret_62, align 16 # | store <8 x i16> %11, ptr %tmp1, align 16 # | %12 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_70 = alloca <2 x i32>, align 8 # | %__s0_70 = alloca <2 x i32>, align 8 # | %__s1_70 = alloca <2 x i32>, align 8 # | %__s2_70 = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_70, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_70, align 8 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_70, align 8 # | %3 = load <2 x i32>, ptr %__s0_70, align 8 # | %4 = load <2 x i32>, ptr %__s1_70, align 8 # | %5 = load <2 x i32>, ptr %__s2_70, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | %mul = mul <2 x i32> %4, %10 # | %add = add <2 x i32> %3, %mul # | store <2 x i32> %add, ptr %__ret_70, align 8 # | %11 = load <2 x i32>, ptr %__ret_70, align 8 # | store <2 x i32> %11, ptr %tmp1, align 8 # | %12 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_60 = alloca <4 x i32>, align 16 # | %__s0_60 = alloca <4 x i32>, align 16 # | %__s1_60 = alloca <4 x i32>, align 16 # | %__s2_60 = alloca <2 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_60, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1_60, align 16 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_60, align 8 # | %3 = load <4 x i32>, ptr %__s0_60, align 16 # | %4 = load <4 x i32>, ptr %__s1_60, align 16 # | %5 = load <2 x i32>, ptr %__s2_60, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> # | store <4 x i32> %lane, ptr %ref.tmp, align 16 # | %8 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %8, ptr %__ret, align 16 # | %9 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %9, ptr %tmp, align 16 # | %10 = load <4 x i32>, ptr %tmp, align 16 # | %mul = mul <4 x i32> %4, %10 # | %add = add <4 x i32> %3, %mul # | store <4 x i32> %add, ptr %__ret_60, align 16 # | %11 = load <4 x i32>, ptr %__ret_60, align 16 # | store <4 x i32> %11, ptr %tmp1, align 16 # | %12 = load <4 x i32>, ptr %tmp1, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_482 = alloca <4 x i16>, align 8 # | %__s0_482 = alloca <4 x i16>, align 8 # | %__s1_482 = alloca <4 x i16>, align 8 # | %__s2_482 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_482, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_482, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_482, align 16 # | %3 = load <4 x i16>, ptr %__s0_482, align 8 # | %4 = load <4 x i16>, ptr %__s1_482, align 8 # | %5 = load <8 x i16>, ptr %__s2_482, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_482, align 8 # | %11 = load <4 x i16>, ptr %__ret_482, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_472 = alloca <8 x i16>, align 16 # | %__s0_472 = alloca <8 x i16>, align 16 # | %__s1_472 = alloca <8 # | ... # `---data was truncated (10240/857511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056084b726eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056084b723e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056084b72762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd59601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5960725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd59601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd596003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056084b6bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056084b6bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056084b6a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056084b350e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056084b350b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd596004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5960050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5960050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084b350a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (489 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005595aeffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595aeff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595aeffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1dde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1ddea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1dde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1dde31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595aef91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595aef91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595aef768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595aec25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595aec25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1dde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1dde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1dde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595aec25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (490 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055ff054ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff054fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff0550062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3a2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3a218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3a2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3a211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff05495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff05495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff0547a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff05129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff05129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3a211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3a211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3a211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff05129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (491 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 3, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 4, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555edbb56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555edbb53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555edbb5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa26fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa26fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa26fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa26fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555edbaecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555edbaeca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555edbad18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555edb780e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555edb780b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa26fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa26fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa26fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555edb780a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (492 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000559f70014eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f70011e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f7001562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad01b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad01b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad01b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad01aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6ffaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f6ffaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f6ff8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f6fc3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f6fc3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad01aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad01aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad01aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f6fc3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557607068eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557607065e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055760706962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b3d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b3d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b3d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b3d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557606ffebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557606ffea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557606fe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557606c92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557606c92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b3d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b3d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b3d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557606c92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (494 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056552275eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056552275be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056552275f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56e4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56e4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56e4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56e4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005655226f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005655226f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005655226d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565522388e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565522388b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56e4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56e4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56e4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565522388a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/nor.c (495 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnor_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nor.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nor.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055b3e2b91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b3e2b8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3e2b9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6bc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3e2b27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b3e2b27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3e2b0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3e27bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3e27bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6bc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3e27bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (496 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call # | ... # `---data was truncated (10240/48703) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d566142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d56613fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d56614362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2696d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2696d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2696d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2696d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5660d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5660d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5660bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d565d6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d565d6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2696d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2696d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2696d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d565d6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (497 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056333cd34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056333cd31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056333cd3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc838133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc83818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc838133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc83811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056333cccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056333cccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056333ccaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056333c95ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056333c95eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc83811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc83811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc83811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056333c95ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (499 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 8) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t( %dest, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 8) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c30dc3aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c30dc37e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c30dc3b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1129a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1129aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1129a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1129a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c30dbd0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c30dbd0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c30dbb58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c30d864e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c30d864b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1129a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1129a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1129a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c30d864a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (501 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca # | ... # `---data was truncated (10240/124506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641aae3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641aae39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641aae3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dd7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dd76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dd7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dd7631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641aadd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641aadd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641aadb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641aaa66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641aaa66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4dd7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dd76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dd76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641aaa66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (502 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d4fc45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d4fc42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d4fc4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a57533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a5758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a57533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a5751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d4fbdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d4fbdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d4fbc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d4f86fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d4f86fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a5751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a5751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a5751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d4f86fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (504 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/63749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005584af7c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584af7bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584af7c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bea049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bea0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bea049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bea031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584af756bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584af756a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584af73b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584af3eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584af3eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bea032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bea0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bea0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584af3eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (505 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b36c48beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b36c488e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b36c48c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0cb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0cb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0cb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0cb831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b36c421bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b36c421a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b36c4068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b36c0b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b36c0b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0cb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0cb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0cb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b36c0b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (506 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ef886eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ef886be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ef886f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaa6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaa6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaa6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaa6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef8804bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ef8804a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ef87e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ef8498e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ef8498b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaa6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaa6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaa6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef8498a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (507 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1cac3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1cac3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1cac3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62d4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62d4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62d4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62d4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1cabd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1cabd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1cabb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1ca868e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1ca868b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62d4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62d4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62d4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1ca868a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm64_vcopy.c (508 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_336 = alloca <16 x i8>, align 16 # | %__s0_336 = alloca <16 x i8>, align 16 # | %__s2_336 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_336, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_336, align 16 # | %2 = load <16 x i8>, ptr %__s2_336, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_336, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_336, align 16 # | %13 = load <16 x i8>, ptr %__ret_336, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_328 = alloca <16 x i8>, align 16 # | %__s0_328 = alloca <16 x i8>, align 16 # | %__s2_328 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_328, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_328, align 16 # | %2 = load <16 x i8>, ptr %__s2_328, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_328, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_328, align 16 # | %13 = load <16 x i8>, ptr %__ret_328, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_346 = alloca <8 x i16>, align 16 # | %__s0_346 = alloca <8 x i16>, align 16 # | %__s2_346 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_346, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_346, align 16 # | %2 = load <8 x i16>, ptr %__s2_346, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_346, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_346, align 16 # | %13 = load <8 x i16>, ptr %__ret_346, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_334 = alloca <8 x i16>, align 16 # | %__s0_334 = alloca <8 x i16>, align 16 # | %__s2_334 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_334, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_334, align 16 # | %2 = load <8 x i16>, ptr %__s2_334, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_334, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_334, align 16 # | %13 = load <8 x i16>, ptr %__ret_334, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <4 x i32>, align 16 # | %a2.addr = alloca <4 x i32>, align 16 # | %__ret_340 = alloca <4 x i32>, align 16 # | %__s0_340 = alloca <4 x i32>, align 16 # | %__s2_340 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca i32, align 4 # | %__ret1 = alloca i32, align 4 # | %__s02 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp3 = alloca <4 x i32>, align 16 # | %tmp4 = alloca <4 x i32>, align 16 # | %tmp5 = alloca <4 x i32>, align 16 # | store <4 x i32> %a1, ptr %a1.addr, align 16 # | store <4 x i32> %a2, ptr %a2.addr, align 16 # | %0 = load <4 x i32>, ptr %a1.addr, align 16 # | store <4 x i32> %0, ptr %__s0_340, align 16 # | %1 = load <4 x i32>, ptr %a2.addr, align 16 # | store <4 x i32> %1, ptr %__s2_340, align 16 # | %2 = load <4 x i32>, ptr %__s2_340, align 16 # | store <4 x i32> %2, ptr %__s02, align 16 # | %3 = load <4 x i32>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <4 x i32> %3, i32 3 # | store i32 %vgetq_lane, ptr %ref.tmp, align 4 # | %4 = load i32, ptr %ref.tmp, align 4 # | store i32 %4, ptr %__ret1, align 4 # | %5 = load i32, ptr %__ret1, align 4 # | store i32 %5, ptr %tmp, align 4 # | %6 = load i32, ptr %tmp, align 4 # | store i32 %6, ptr %__s0, align 4 # | %7 = load <4 x i32> # | ... # `---data was truncated (10240/22011) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556c21c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556c21bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556c21c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7af3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7af3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7af3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7af3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556c2157bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556c2157a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556c213c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556c1debe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556c1debb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7af3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7af3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7af3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556c1deba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (509 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1c7dafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1c7dace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1c7db062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd58281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5828725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd58281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd582803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1c7d45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1c7d45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1c7d2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1c79d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1c79d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd582804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5828050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5828050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1c79d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (510 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb3673beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb36738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb3673c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff30f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff30f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff30f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff30f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb366d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb366d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb366b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb36365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb36365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff30f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff30f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff30f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb36365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (511 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1 # | ... # `---data was truncated (10240/37926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562b96a37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b96a34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b96a3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ee9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ee92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ee9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ee9231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b969cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b969cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b969b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b96661e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b96661b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ee9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ee92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ee92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b96661a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (512 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_b( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055852ff1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055852ff1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055852ff1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa56cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa56cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa56cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa56cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055852feb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055852feb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055852fe988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055852fb47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055852fb47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa56cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa56cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa56cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055852fb47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (513 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2f7a85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2f7a82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2f7a8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2fb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2fb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2fb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2fb231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2f7a1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2f7a1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2f7a008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2f76afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2f76afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd2fb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2fb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2fb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2f76afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/dup.c (514 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f16(half noundef %op) #0 { # | entry: # | %op.addr = alloca half, align 2 # | store half %op, ptr %op.addr, align 2 # | %0 = load half, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8f16(half %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8f16(half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f32(float noundef %op) #0 { # | entry: # | %op.addr = alloca float, align 4 # | store float %op, ptr %op.addr, align 4 # | %0 = load float, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4f32(float %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4f32(float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f64(double noundef %op) #0 { # | entry: # | %op.addr = alloca double, align 8 # | store double %op, ptr %op.addr, align 8 # | %0 = load double, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2f64(double %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2f64(double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b8(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | ret %.splat # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b16(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b32(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b64(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_bf16(bfloat noundef %op) #0 { # | entry: # | %op.addr = alloca bfloat, align 2 # | store bfloat %op, ptr %op.addr, align 2 # | %0 = load bfloat, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8_z( %pg, i8 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i8, align 1 # | store %pg, ptr %pg.addr, align 2 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i8, ptr %op.addr, align 1 # | %2 = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.nxv16i8(, , i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16_z( %pg, i16 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i16, ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (515 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fccae45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fccae42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fccae4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe16d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe16d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe16d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe16d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fccaddbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fccaddba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fccadc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fccaa6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fccaa6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe16d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe16d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe16d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fccaa6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (516 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_any( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_first( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_last( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056074b28feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056074b28ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056074b29062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9513f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9513f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9513f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9513f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056074b225bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056074b225a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056074b20a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056074aeb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056074aeb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9513f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9513f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9513f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056074aeb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (517 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | sto # | ... # `---data was truncated (10240/102864) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ced5da2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ced5d9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ced5da362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44f2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44f278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44f2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44f271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ced5d38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ced5d38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ced5d1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ced59cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ced59ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44f271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44f271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44f271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ced59cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (518 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (519 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %4, ptr %__ret.i, align 16 # | %5 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %5, ptr %__ret.i, align 16 # | %6 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i # | ... # `---data was truncated (10240/23350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000557af3b91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557af3b8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557af3b9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7e7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7e78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7e7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7e7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557af3b27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557af3b27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557af3b0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557af37bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557af37bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7e7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7e78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7e78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557af37bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orv.c (520 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.orv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.orv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.orv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.orv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005608a8a68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608a8a65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608a8a6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e9d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e9d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e9d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e9d0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608a89febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608a89fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608a89e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608a8692e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608a8692b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e9d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e9d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e9d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608a8692a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (521 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562049bbeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562049bbbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562049bbf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0f8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0f82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0f8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0f8231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562049b54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562049b54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562049b398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620497e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620497e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0f8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0f82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0f82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620497e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (522 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563563dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563563dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563563dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f18249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f182a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f18249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f18231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563563d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563563d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563563d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635639f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635639f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f18232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f182330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f182330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635639f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (523 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8f16(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (524 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bc2d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bc2d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bc2d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77afd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77afd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77afd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77afd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bc2cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bc2cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bc2cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bc2969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bc2969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77afd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77afd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77afd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bc2969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (525 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (526 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (527 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.x2.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_x2( %op1, %op2, half noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store half %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load half, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync no # | ... # `---data was truncated (10240/10512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ef2f2b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef2f2afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef2f2b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa22e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa22e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa22e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa22e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef2f248bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef2f248a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef2f22d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef2eedce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef2eedcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa22e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa22e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa22e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef2eedca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (528 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32( %0, %1, %2, i32 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ac69194eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac69191e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac6919562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a5dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac6912abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac6912aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac6910f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac68dbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac68dbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac68dbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563598e4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563598e4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563598e4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b54b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b54b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b54b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b54b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563598de4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563598de4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563598dc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563598a78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563598a78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b54b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b54b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b54b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563598a78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (530 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (531 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056368940eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056368940be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056368940f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdb2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdb215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdb2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdb20ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636893a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636893a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636893898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563689038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563689038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efdb20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdb20ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdb20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563689038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (532 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbo # | ... # `---data was truncated (10240/21216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056285c3f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056285c3f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056285c3f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa4ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa4eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa4ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa4ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056285c38bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056285c38ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056285c3708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056285c01fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056285c01fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa4ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa4ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa4ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056285c01fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (533 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (534 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bc900f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc900f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc900f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef38133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef3818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef38133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef3811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc9008abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc9008aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc9006f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc8fd1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc8fd1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef3811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef3811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef3811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc8fd1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (535 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d55557eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d55554e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d5555862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a36449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a36449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a36431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d554edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d554eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d554d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d55181e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d55181b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a36432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d55181a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (536 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (537 of 27910) ******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z9cond_boolu10__SVBool_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ult %0, %1 # | %2 = load , ptr %a.addr, align 2 # | %3 = load , ptr %b.addr, align 2 # | %vector_select = select %cmp, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_i8u10__SVInt8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_u8u11__SVUint8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i16u11__SVInt16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u16u12__SVUint16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i32u11__SVInt32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u32u12__SVUint32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i64u11__SVInt64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u64u12__SVUint64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f16u13__SVFloat16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f32u13__SVFloat32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (538 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f64( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dca0ab6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dca0ab3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dca0ab762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd360933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd36098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd360933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd36091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dca0a4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dca0a4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dca0a318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dca06e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dca06e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd36091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd36091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd36091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dca06e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (539 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (540 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_bf16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005586c5d59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586c5d56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586c5d5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0852449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0852449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0852431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586c5cefbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586c5cefa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586c5cd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586c5983e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586c5983b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0852432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08524330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586c5983a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (541 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f5c61bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5c61b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5c61bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf97d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf97d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf97d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf97d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5c6152bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5c6152a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5c61378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5c5de6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5c5de6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf97d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf97d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf97d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5c5de6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (542 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6) # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6) # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__p1.addr.i.i = alloca <4 x half>, align 8 # | %__p2.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8 # | store <4 x half> %5, ptr %__p2.addr.i.i, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %13, ptr %__ret.i.i, align 8 # | %14 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <8 x half>, align 16 # | %__p1.addr.i.i = alloca <8 x half>, align 16 # | %__p2.addr.i.i = alloca <8 x half>, align 16 # | %__ret.i.i = alloca <8 x half>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i.i, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16 # | store <8 x half> %5, ptr %__p2.addr.i.i, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16 # | store <8 x half> %13, ptr %__ret.i.i, align 16 # | %14 = load <8 x half>, ptr %__ret.i.i, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1) # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1 # | ... # `---data was truncated (10240/42739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559288fcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559288fc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559288fcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc63d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc63d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc63d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc63d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559288f61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559288f61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559288f468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559288bf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559288bf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc63d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc63d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc63d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559288bf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (543 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtn.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvtn.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvtn.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_loc # | ... # `---data was truncated (10240/17734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563bd2065eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bd2062e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bd206662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feea4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feea4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feea4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feea4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bd1ffbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bd1ffba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bd1fe08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bd1c8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bd1c8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feea4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feea4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feea4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bd1c8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (544 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (545 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nounwind } # | attributes #2 = { nounwind memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da8106deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da8106ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da8106e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f640d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f640d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f640d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f640d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da81003bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da81003a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da80fe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da80c97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da80c97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f640d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f640d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f640d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da80c97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (546 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056202cb98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056202cb95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056202cb9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f774e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f774e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f774e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f774e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056202cb2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056202cb2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056202cb138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056202c7c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056202c7c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f774e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f774e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f774e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056202c7c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e2eed3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e2eed0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e2eed462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f934b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f934b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f934b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f934b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e2ee69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e2ee69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e2ee4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e2eafde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e2eafdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f934b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f934b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f934b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e2eafda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (548 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055e36f361eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e36f35ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e36f36262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1ab733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1ab78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1ab733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1ab71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e36f2f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e36f2f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e36f2dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e36ef8be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e36ef8bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1ab71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1ab71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1ab71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e36ef8ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (549 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 0) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_1() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 1) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_2() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 2) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_3() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 3) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_4() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 4) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_5() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 5) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_6() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 6) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_7() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 7) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 8) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_9() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 9) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_10() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_11() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_12() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 12) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_13() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 13) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_14() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 29) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_15() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 30) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 1) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 2) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eab98eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eab98e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eab98ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3a6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3a60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3a6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3a6031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eab9882bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eab9882a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eab98678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eab9516e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eab9516b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3a6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3a60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3a60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eab9516a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (550 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bd26c00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd26bfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd26c0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4591b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4591b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4591b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4591b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd26b96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd26b96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd26b7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd2682ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd2682ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4591b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4591b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4591b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd2682aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (551 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fe66c5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe66c5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe66c5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53f3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53f30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53f3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53f3031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe66bf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe66bf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe66bd98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe66888e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe66888b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53f3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53f30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53f30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe66888a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (552 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_rsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %1, i64 0 # | %splat.splat = shufflevector %splat.splatinsert, poison, zeroinitializer # | %shl = shl %0, %splat.splat # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_lsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %0, i64 0 # | %splat.splat # | ... # `---data was truncated (10240/32491) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055a6ae0e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6ae0e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6ae0e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1c8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6ae07abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6ae07aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6ae05f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6add0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6add0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1c8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6add0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (553 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0, align 8 # | %1 = load <4 x bfloat>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x bfloat> %1, i32 1 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0, align 16 # | %1 = load <8 x bfloat>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x bfloat> %1, i32 7 # | store bfloat %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_48 = alloca <4 x bfloat>, align 8 # | %__s0_48 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_48, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_48, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_48, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_48, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_46 = alloca <8 x bfloat>, align 16 # | %__s0_46 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_46, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_46, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_46, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_46, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_52 = alloca <4 x bfloat>, align 8 # | %__s0_52 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_52, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_52, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_52, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_52, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_50 = alloca <8 x bfloat>, align 16 # | %__s0_50 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_50, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_50, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_50, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_50, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %.compoundliteral.i = alloca <4 x bfloat>, align 8 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8 # | store <4 x bfloat> %5, ptr %__ret.i, align 8 # | %6 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %.compoundliteral.i = alloca <8 x bfloat>, align 16 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | %5 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4 # | %6 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5 # | %7 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6 # | %8 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7 # | store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16 # | %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/13833) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ec76673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec76670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec7667462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d7db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d7db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d7db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d7db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec76609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec76609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec765ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec7629de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec7629db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d7db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d7db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d7db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec7629da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (554 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv32i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv32i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/121927) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576ad148eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576ad145e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576ad14962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9691c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9691ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9691c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9691c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576ad0debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576ad0dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576ad0c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576acd72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576acd72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9691c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9691c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9691c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576acd72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (555 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f799227eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f799224e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f79922862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29d8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29d895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29d8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29d88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7991bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7991bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7991a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f798e51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f798e51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29d88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29d88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29d88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f798e51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (557 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055adb46fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055adb46fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055adb46fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f021821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02182725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f021821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0218203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adb4693bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055adb4693a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055adb46788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055adb4327e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055adb4327b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0218204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02182050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02182050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adb4327a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (558 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmaxnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005559a7076eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559a7073e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559a707762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff775049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff775049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff775031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559a700cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559a700ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559a6ff18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559a6ca0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559a6ca0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff775032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7750330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559a6ca0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (559 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056194bab4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056194bab1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056194bab562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d53e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d53e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d53e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d53e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056194ba4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056194ba4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056194ba2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056194b6dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056194b6deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d53e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d53e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d53e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056194b6dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (560 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (561 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractva # | ... # `---data was truncated (10240/22708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631f44a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631f44a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631f44a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce45f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce45f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce45f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce45f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631f443abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631f443aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631f441f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631f40cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631f40ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce45f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce45f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce45f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631f40cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (562 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (564 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b49c6c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b49c6c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b49c6c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec9fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec9faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec9fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec9fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b49c659bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b49c659a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b49c63e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b49c2ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b49c2edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec9fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec9fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec9fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b49c2eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (565 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (566 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (567 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/97240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2c5f38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2c5f35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2c5f3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f906d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f906d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f906d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f906d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2c5ecebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2c5ecea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2c5eb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2c5b62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2c5b62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f906d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f906d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f906d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2c5b62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f7c633eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f7c630e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f7c63462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab5bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab5bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab5bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab5bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f7c5c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f7c5c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f7c5ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f7c25de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f7c25db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab5bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab5bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab5bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f7c25da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (569 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv2f64( undef, %2, %1) # | # | ... # `---data was truncated (10240/23662) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cf22612eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf2260fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf2261362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f351e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f351e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f351e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f351e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf225a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf225a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf2258d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf2223ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf2223cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f351e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f351e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f351e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf2223ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (570 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s64( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (571 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/53158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555814b0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555814b0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555814b1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3129733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f312978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3129733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f312971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555814aa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555814aa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555814a8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555814739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555814739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f312971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f312971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f312971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555814739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (572 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dfb7c1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfb7c19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfb7c1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5da0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5da00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5da0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5da0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfb7bb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfb7bb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfb7b978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfb7846e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfb7846b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5da0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5da00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5da00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfb7846a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (573 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_f16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e47701eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e476fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e4770262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff725a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff725aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff725a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff725a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e47697bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e47697a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e4767c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e4732be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e4732bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff725a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff725a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff725a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e4732ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-vld.c (575 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float16x4x3_t, ptr %retval, align 8 # | ret %struct.float16x4x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float16x4x4_t, ptr %retval, align 8 # | ret %struct.float16x4x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float32x2x2_t, ptr %retval, align 8 # | ret %struct.float32x2x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float32x2x3_t, ptr %retval, align 8 # | ret %struct.float32x2x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float32x2x4_t, ptr %retval, align 8 # | ret %struct.float32x2x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0) # | store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.poly16x4x2_t, ptr %retval, align 8 # | ret %struct.poly16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16 # | ... # `---data was truncated (10240/109928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563665c27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563665c24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563665c2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9c0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9c00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9c0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9c0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563665bbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563665bbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563665ba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563665851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563665851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9c0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9c00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9c00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563665851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (576 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000056021e80aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056021e807e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056021e80b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f987de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f987de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f987de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f987de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056021e7a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056021e7a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056021e7858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056021e434e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056021e434b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f987de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f987de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f987de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056021e434a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (577 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005648dac78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648dac75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648dac7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1da4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1da4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1da4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1da4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648dac0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648dac0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648dabf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648da8a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648da8a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1da4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1da4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1da4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648da8a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (578 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cee6c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cee6c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cee6c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0290e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0290e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0290e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0290e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cee65abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cee65aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cee63f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cee2eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cee2eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0290e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0290e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0290e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cee2eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (579 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (580 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a0eaf42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0eaf3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0eaf4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f007cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f007cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f007cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f007cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0eaed8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0eaed8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0eaebd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0eab6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0eab6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f007cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f007cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f007cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0eab6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (581 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (582 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005555efa48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555efa45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555efa4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5332133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f533218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5332133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f533211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555ef9debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555ef9dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555ef9c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555ef672e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555ef672b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f533211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f533211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f533211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555ef672a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (583 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563246bbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563246bb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563246bbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04cd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04cd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04cd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04cd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563246b51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563246b51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563246b368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632467e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632467e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04cd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04cd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04cd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632467e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (584 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a18d9d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a18d9d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a18d9da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23b1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23b16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23b1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23b1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a18d96fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a18d96fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a18d9548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a18d603e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a18d603b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23b1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23b16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23b16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a18d603a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (585 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bf16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055638c11feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055638c11ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055638c12062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52a4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52a458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52a4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52a451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638c0b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055638c0b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055638c09a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055638bd49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055638bd49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52a451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52a451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52a451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055638bd49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (586 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557168559eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557168556e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055716855a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecb7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecb7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecb7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecb7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571684efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571684efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571684d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557168183e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557168183b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecb7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecb7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecb7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557168183a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align # | ... # `---data was truncated (10240/39416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2fde3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2fde3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2fde3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb765705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb76575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb765705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7656ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2fddd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2fddd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2fddb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2fda67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2fda67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7656eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7656ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7656ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2fda67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613033a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056130339ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613033a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff940133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff94018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff940133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff94011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561303337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561303337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056130331c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561302fcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561302fcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff94011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff94011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff94011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561302fcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , al # | ... # `---data was truncated (10240/13263) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d51e32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d51e2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d51e3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9714449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9714449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9714431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d51dc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d51dc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d51dad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d51a5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d51a5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9714432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97144330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d51a5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (590 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrffr( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | call void @llvm.aarch64.sve.wrffr( %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.wrffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005601e67c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601e67bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601e67c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8898649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88986a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8898649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8898631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601e6758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601e6758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601e673d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601e63ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601e63ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8898632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88986330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88986330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601e63eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (591 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.smmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smmla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_u32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.ummla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ummla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usmmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usmmla.nxv4i32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bf882b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf882ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf882b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff436649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff436649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff436631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf88246bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf88246a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf8822b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf87edae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf87edab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff436632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4366330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf87edaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (592 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592c7089eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592c7086e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592c708a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0ba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0ba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0ba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0ba51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592c701fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592c701fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592c70048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592c6cb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592c6cb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0ba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0ba51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0ba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592c6cb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (593 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563a42a40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a42a3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a42a4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbed933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbed98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbed933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbed91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a429d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a429d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a429bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a4266ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a4266ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbed91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbed91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbed91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a4266aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (594 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056068b32deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056068b32ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056068b32e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d41533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d4158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d41533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d4151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056068b2c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056068b2c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056068b2a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056068af57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056068af57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d4151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d4151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d4151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056068af57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (595 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/22483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005655465b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005655465b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005655465b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06cce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06ccea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06cce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06cce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056554654abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056554654aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056554652f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005655461dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005655461deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06cce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06cce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06cce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655461dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (596 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv8f16(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_1( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_2( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 180) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_3( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 270) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv4f32( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv4f32(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv2f64( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv2f64(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (597 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { < # | ... # `---data was truncated (10240/50724) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560f420b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f420b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f420b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed5911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f4204bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f4204ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f420308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f41cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f41cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed5911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f41cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (598 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055799e02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055799e027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055799e02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5aec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5aeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5aec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5aec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055799dfc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055799dfc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055799dfa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055799dc54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055799dc54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff5aec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5aec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5aec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055799dc54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ef8c86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ef8c83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ef8c8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9942b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9942b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9942b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9942b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ef8c1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ef8c1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ef8c018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ef88b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ef88b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9942b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9942b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9942b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ef88b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/poly128.c (600 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | ret i128 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__s1 = alloca i128, align 16 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | store i128 %4, ptr %__s1, align 16 # | %5 = load ptr, ptr %ptr.addr, align 8 # | %add.ptr = getelementptr inbounds i128, ptr %5, i64 1 # | %6 = load i128, ptr %__s1, align 16 # | store i128 %6, ptr %add.ptr, align 16 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca i128, align 16 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load i64, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3) # | %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128 # | store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16 # | %4 = load i128, ptr %ref.tmp.i, align 16 # | store i128 %4, ptr %__ret.i, align 16 # | %5 = load i128, ptr %__ret.i, align 16 # | ret i128 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { # | entry: # | %__p0.addr.i3 = alloca <2 x i64>, align 16 # | %__ret.i4 = alloca <1 x i64>, align 8 # | %__p0.addr.i1 = alloca <2 x i64>, align 16 # | %__ret.i2 = alloca <1 x i64>, align 8 # | %__p0.addr.i.i = alloca i64, align 8 # | %__p1.addr.i.i = alloca i64, align 8 # | %__ret.i.i = alloca i128, align 16 # | %ref.tmp.i.i = alloca i128, align 16 # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %ref.tmp1.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %2, ptr %__p0.addr.i3, align 16 # | %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> # | store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8 # | %5 = load <1 x i64>, ptr %__ret.i4, align 8 # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load i64, ptr %ref.tmp.i, align 8 # | %7 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | store <2 x i64> %7, ptr %__p0.addr.i1, align 16 # | %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8 # | %10 = load <1 x i64>, ptr %__ret.i2, align 8 # | store <1 x i64> %10, ptr %ref.tmp1.i, align 8 # | %11 = load i64, ptr %ref.tmp1.i, align 8 # | store i64 %6, ptr %__p0.addr.i.i, align 8 # | store i64 %11, ptr %__p1.addr.i.i, align 8 # | %12 = load i64, ptr %__p0.addr.i.i, align 8 # | %13 = load i64, ptr %__p1.addr.i.i, align 8 # | %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13) # | %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128 # | store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16 # | %14 = load i128, ptr %ref.tmp.i.i, align 16 # | store i128 %14, ptr %__ret.i.i, align 16 # | %15 = load i128, ptr %__ret.i.i, align 16 # | store i128 %15, ptr %__ret.i, align 16 # | %16 = load i128, ptr %__ret.i, align 16 # | ret i128 %16 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.ad # | ... # `---data was truncated (10240/19795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f0a96bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0a96b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0a96bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e04249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e042a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e04249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e04231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0a9652bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0a9652a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0a96378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0a92e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0a92e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e04232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e042330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e042330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0a92e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (601 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vdot1.i = bitcast <8 x i8> %4 to <4 x half> # | %vdot2.i = bitcast <8 x i8> %5 to <4 x half> # | %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i) # | store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vdot1.i = bitcast <16 x i8> %4 to <8 x half> # | %vdot2.i = bitcast <16 x i8> %5 to <8 x half> # | %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i) # | store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane) # | store <4 x float> %vdot2, ptr %ref.tmp, align 16 # | %7 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %7, ptr %__ret, align 16 # | %8 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %8, ptr %tmp, align 16 # | %9 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aa # | ... # `---data was truncated (10240/11256) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000558f91a4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f91a48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f91a4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ea2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ea2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ea2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ea2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f919e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f919e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f919c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f91675e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f91675b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ea2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ea2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ea2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f91675a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (602 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ddd24beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ddd24bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ddd24bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe780d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe780d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe780d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe780d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddd2454bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ddd2454a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ddd24398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ddd20e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ddd20e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe780d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe780d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe780d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddd20e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef # | ... # `---data was truncated (10240/78336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563491246eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563491243e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056349124762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f701f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f701f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f701f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f701f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634911dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634911dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634911c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563490e70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563490e70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f701f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f701f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f701f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563490e70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f97d21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f97d1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f97d2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2299f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2299f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2299f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2299f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f97cb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f97cb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f97c9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f9794be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f9794bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2299f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2299f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2299f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f9794ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (605 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005638d86b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005638d86b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005638d86b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9828733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f982878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9828733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f982871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638d864cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638d864ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638d86318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005638d82e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005638d82e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f982871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f982871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f982871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638d82e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055693fcb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055693fcb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055693fcb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62f3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62f36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62f3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62f3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055693fc4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055693fc4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055693fc308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055693f8dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055693f8dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62f3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62f36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62f36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055693f8dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (607 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619b4be7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619b4be4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619b4be862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f120a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f120a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f120a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f120a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619b4b7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619b4b7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619b4b628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619b4811e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619b4811b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f120a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f120a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f120a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619b4811a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561533c3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561533c3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561533c3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4899249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48992a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4899249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4899231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561533bd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561533bd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561533bb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561533867e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561533867b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4899232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48992330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48992330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561533867a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a0adcbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a0adc8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a0adcc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb86431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a0ad61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a0ad61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a0ad468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a0a9f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a0a9f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a0a9f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (610 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (611 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brka.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brka.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556101e07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556101e04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556101e0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4ee31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556101d9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556101d9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556101d828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556101a31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556101a31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556101a31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (612 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555c2c7a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c2c7a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c2c7aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f645d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f645d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f645d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f645d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c2c73fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c2c73fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c2c7248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c2c3d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c2c3d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f645d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f645d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f645d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c2c3d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be28959eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be28956e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be2895a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48d161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48d16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48d161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48d1603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be288efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be288efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be288d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be28583e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be28583b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f48d1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48d16050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48d16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be28583a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (614 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000561b09c23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b09c20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b09c2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd699a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd699aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd699a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd699a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b09bb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b09bb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b09b9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b0984de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b0984db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd699a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd699a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd699a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b0984da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (615 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b76dbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b76db9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b76dbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe158d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe158d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe158d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe158d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b76d52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b76d52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b76d378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b769e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b769e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe158d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe158d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe158d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b769e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (617 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc2b500eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc2b4fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc2b50162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84fc01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84fc0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84fc01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84fc003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc2b496bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc2b496a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc2b47b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc2b12ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc2b12ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84fc004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84fc0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84fc0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc2b12aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572b2fe7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572b2fe4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572b2fe862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3eae21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3eae2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3eae21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3eae203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572b2f7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572b2f7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572b2f628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572b2c11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572b2c11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3eae204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3eae2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3eae2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572b2c11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a60c34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a60c31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a60c3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0368333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f036838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0368333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f036831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a60bcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a60bcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a60baf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a6085ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a6085eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f036831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f036831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f036831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a6085ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (620 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056277f2caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056277f2c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056277f2cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f446cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f446cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f446cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f446cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056277f260bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056277f260a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056277f2458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056277eef4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056277eef4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f446cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f446cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f446cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056277eef4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (621 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556d9bf1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d9bf17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d9bf1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e9e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e9e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e9e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e9e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d9beb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d9beb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d9be958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d9bb44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d9bb44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e9e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e9e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e9e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d9bb44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (622 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560924b3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560924b38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560924b3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b99933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b9998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b99933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b9991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560924ad1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560924ad1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560924ab68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560924765e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560924765b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b9991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b9991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b9991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560924765a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (624 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.a # | ... # `---data was truncated (10240/174713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559da63abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559da63a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559da63ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdbb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdbb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdbb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdbb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559da6341bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559da6341a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559da63268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559da5fd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559da5fd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbdbb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdbb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdbb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559da5fd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (625 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, # | ... # `---data was truncated (10240/142319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f6c75deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f6c75ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f6c75e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f641ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f641eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f641ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f641ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f6c6f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f6c6f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f6c6d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f6c387e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f6c387b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f641ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f641ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f641ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f6c387a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (626 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055772f372eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055772f36fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055772f37362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d16933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d1698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d16933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d1691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055772f308bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055772f308a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055772f2ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055772ef9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055772ef9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d1691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d1691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d1691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055772ef9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (627 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cls.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/11769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561fb3dcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fb3dcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fb3dce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7e0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7e04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7e0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7e0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fb3d63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fb3d63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fb3d488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fb39f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fb39f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7e0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7e04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7e04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fb39f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (628 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (629 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560f3d457eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f3d454e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f3d45862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1692f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1692f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1692f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1692eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f3d3edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f3d3eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f3d3d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f3d081e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f3d081b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1692eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1692eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1692eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f3d081a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (630 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_v # | ... # `---data was truncated (10240/29273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f371c04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f371c01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f371c0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdbb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdbb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdbb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdbb431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f371b9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f371b9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f371b7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f37182ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f37182eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efdbb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdbb4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdbb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f37182ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c81289feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c81289ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8128a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0f5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0f5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0f5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0f5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c812835bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c812835a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c81281a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8124c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8124c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0f5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0f5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0f5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8124c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (632 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("risc # | ... # `---data was truncated (10240/14659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8861f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8861f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8861f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa57d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa57d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa57d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa57d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f88618dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f88618da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8861728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f885e21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f885e21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa57d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa57d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa57d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f885e21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (633 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca # | ... # `---data was truncated (10240/97514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625f4350eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625f434de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625f435162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8876849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88768a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8876849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8876831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625f42e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625f42e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625f42cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625f3f7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625f3f7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8876832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88768330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88768330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625f3f7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (634 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561a8b873eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a8b870e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a8b87462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37c5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37c5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37c5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37c5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a8b809bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a8b809a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a8b7ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a8b49de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a8b49db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37c5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37c5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37c5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a8b49da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (635 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbe3b88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbe3b85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbe3b8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0bf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0bf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0bf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0bf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbe3b1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbe3b1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbe3b038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbe37b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbe37b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0bf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0bf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0bf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbe37b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056499952beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564999528e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056499952c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3308c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3308ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3308c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3308c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649994c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649994c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649994a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564999155e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564999155b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3308c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3308c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3308c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564999155a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (637 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557db1304eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557db1301e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557db130562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd87a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd87a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd87a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd87a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557db129abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557db129aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557db127f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557db0f2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557db0f2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd87a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd87a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd87a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557db0f2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (638 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/77120) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557c55f83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c55f80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c55f8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3bbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3bbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3bbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3bbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c55f19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c55f19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c55efe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c55bade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c55badb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3bbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3bbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3bbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c55bada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (639 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf5ce31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf5ce2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf5ce3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f432d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f432d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f432d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f432d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf5cdc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf5cdc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf5cdac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf5ca5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf5ca5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f432d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f432d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f432d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf5ca5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fc3c90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fc3c8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fc3c9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a4c505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a4c55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a4c505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a4c4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fc3c26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fc3c26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fc3c0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fc38bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fc38bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a4c4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a4c4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a4c4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fc38baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (641 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d337ce1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d337cdee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d337ce262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62f4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62f415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62f4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62f40ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d337c77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d337c77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d337c5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d33790be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d33790bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62f40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62f40ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62f40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d33790ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfa # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c33ac89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c33ac86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c33ac8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7edd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7edd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7edd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7edd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c33ac1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c33ac1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c33ac048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c33a8b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c33a8b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7edd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7edd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7edd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c33a8b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0c79b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0c79ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0c79b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97d7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97d778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97d7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97d771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0c7946bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0c7946a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0c792b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0c75dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0c75dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97d771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97d771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97d771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0c75daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (644 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f8ed25beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8ed258e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8ed25c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc17f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc17f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc17f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc17f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8ed1f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8ed1f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8ed1d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8ece85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8ece85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc17f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc17f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc17f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8ece85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv # | ... # `---data was truncated (10240/53548) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ba1812eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ba180fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ba181362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d58105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d5815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d58105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d580ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ba17a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ba17a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ba178d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ba143ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ba143cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d580eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d580ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d580ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ba143ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592530daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592530d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592530db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6b2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6b2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6b2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6b2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559253070bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559253070a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592530558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559252d04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559252d04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6b2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6b2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6b2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559252d04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/78328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557942152eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055794214fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055794215362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ffe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ffe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ffe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ffe31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579420e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579420e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579420cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557941d7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557941d7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ffe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ffe31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ffe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557941d7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (648 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557b295deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557b295ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557b295e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd727105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd727105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7270ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557b28f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557b28f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557b28d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557b2587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557b2587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7270eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7270ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7270ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557b2587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (649 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp eq %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ne %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | stor # | ... # `---data was truncated (10240/44453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005617bcb69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617bcb66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617bcb6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a88a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617bcaffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617bcaffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617bcae48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617bc793e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617bc793b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a88a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617bc793a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633c5bfbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633c5bf8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633c5bfc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa06f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa06f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa06f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa06f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633c5b91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633c5b91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633c5b768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633c5825e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633c5825b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa06f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa06f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa06f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633c5825a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (652 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/33353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f5ca0e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5ca0dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5ca0e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5592b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5592b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5592b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5592b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5ca077bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5ca077a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5ca05c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5c9d0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5c9d0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5592b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5592b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5592b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5c9d0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (653 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055aa67954eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa67951e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa6795562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8767849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8767849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8767831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa678eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa678eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa678cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa6757ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa6757eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8767832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87678330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa6757ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (654 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (655 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557797028eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557797025e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055779702962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd43049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd430a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd43049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd43031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557796fbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557796fbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557796fa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557796c52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557796c52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd43032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd430330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd430330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557796c52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601f66c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601f66c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601f66c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f163f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f163f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f163f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f163f231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601f665bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601f665ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601f66408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601f62efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601f62efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f163f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f163f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f163f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601f62efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (657 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ec65baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ec65b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ec65bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49df933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49df98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49df933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49df91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ec6550bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ec6550a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ec65358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ec61e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ec61e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f49df91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49df91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49df91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ec61e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (658 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <16 x i8> %2, %3 # | store <16 x i8> %sub.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <8 x i16> %2, %3 # | store <8 x i16> %sub.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <4 x i32> %2, %3 # | store <4 x i32> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | store <1 x i64> %v2, ptr %v2.addr, align 8 # | %0 = load <1 x i64>, ptr %v1.addr, align 8 # | %1 = load <1 x i64>, ptr %v2.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <1 x i64> %2, %3 # | store <1 x i64> %sub.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v1.addr = alloca <2 x i64>, align 16 # | %v2.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %v1, ptr %v1.addr, align 16 # | store <2 x i64> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x i64>, ptr %v1.addr, align 16 # | %1 = load <2 x i64>, ptr %v2.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <2 x i64> %2, %3 # | store <2 x i64> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | # | ... # `---data was truncated (10240/170019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055b25a41aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b25a417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b25a41b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c3c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c3c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c3c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c3c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b25a3b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b25a3b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b25a3958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b25a044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b25a044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c3c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c3c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c3c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b25a044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/12381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056000decdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056000decae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056000dece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c71249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c71249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c71231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056000de63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056000de63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056000de488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056000daf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056000daf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c71232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c712330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056000daf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c414d51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c414d4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c414d5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cf2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cf2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cf2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cf2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c414ce7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c414ce7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c414ccc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c41497be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c41497bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cf2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cf2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cf2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c41497ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fc220feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fc220ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fc221062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d49849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d49849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d49831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fc21a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fc21a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fc218a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fc1e39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fc1e39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d49832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d498330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fc1e39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (662 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/77062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643a8c9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643a8c98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643a8c9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc983449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc983449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc983431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643a8c31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643a8c31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643a8c168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643a88c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643a88c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc983432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9834330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643a88c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586b58f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586b58f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586b58f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8141933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f814198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8141933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f814191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586b588cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586b588ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586b58718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586b5520e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586b5520b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f814191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f814191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f814191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586b5520a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (664 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116957) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5cfaafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5cfaace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5cfab062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01df505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01df55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01df505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01df4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5cfa45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5cfa45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5cfa2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5cf6d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5cf6d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01df4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01df4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01df4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5cf6d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (665 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/98581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b33ce71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b33ce6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b33ce7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e0a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e0a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e0a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e0a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b33ce07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b33ce07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b33cdec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b33ca9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b33ca9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e0a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e0a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e0a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b33ca9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (667 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-cde-vec.c (668 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 { # | entry: # | %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %acc, ptr %acc.addr, align 8 # | %0 = load <4 x i32>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113) # | %3 = bitcast <16 x i8> %2 to <4 x i32> # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 { # | entry: # | %n.addr = alloca <8 x half>, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | %0 = load <8 x half>, ptr %n.addr, align 8 # | %1 = bitcast <8 x half> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 { # | entry: # | %n.addr = alloca <4 x float>, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %n.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112) # | %3 = bitcast <16 x i8> %2 to <4 x float> # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <2 x i64>, align 8 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = load <2 x i64>, ptr %n.addr, align 8 # | %3 = bitcast <2 x i64> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113) # | %5 = bitcast <16 x i8> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 { # | entry: # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x i32> %m, ptr %m.addr, align 8 # | %0 = load <8 x i16>, ptr %n.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <16 x i8> # | %2 = load <4 x i32>, ptr %m.addr, align 8 # | %3 = bitcast <4 x i32> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %n.addr = alloca <2 x i64>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <2 x i64>, ptr %n.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %2 = load <4 x float>, ptr %m.addr, align 8 # | %3 = bitcast <4 x float> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12) # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load <8 x i16>, ptr %n.addr, align 8 # | %2 = bitcast <8 x i16> %1 to <16 x i8> # | %3 = load <4 x float>, ptr %m.addr, align 8 # | %4 = bitcast <4 x float> %3 to <16 x i8> # | %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %n.addr, align 8 # | %2 = bitcast <4 x float> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = load <8 x half>, ptr %n.addr, align 8 # | %2 = bitcast <8 x half> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %m.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | ... # `---data was truncated (10240/13030) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c3d8afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c3d8ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c3d8b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdefbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdefbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdefbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdefbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c3d845bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c3d845a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c3d82a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c3d4d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c3d4d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdefbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdefbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdefbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c3d4d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (669 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (670 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac3c550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac3c54de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac3c55162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c95f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c95f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c95f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c95f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac3c4e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac3c4e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac3c4cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac3c17ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac3c17ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c95f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c95f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c95f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac3c17aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ade1dcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ade1dc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ade1dcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5d7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5d758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5d7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5d751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ade1d60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ade1d60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ade1d458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ade19f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ade19f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5d751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5d751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5d751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ade19f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde # | ... # `---data was truncated (10240/31748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602f1b0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602f1b0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602f1b0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0a9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0a9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0a9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0a9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602f1aa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602f1aa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602f1a888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602f1737e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602f1737b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0a9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0a9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0a9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602f1737a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (673 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = fneg <8 x half> %1 # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = fneg <4 x float> %1 # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %c, ptr %c.addr, align 2 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = mul <8 x i16> %0, %.splat # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = add <8 x i16> %2, %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i32 %c, ptr %c.addr, align 4 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = mul <4 x i32> %0, %.splat # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = add <4 x i32> %2, %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, ali # | ... # `---data was truncated (10240/60411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055bedf3deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bedf3dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bedf3df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6af849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6af8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6af849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6af831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bedf374bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bedf374a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bedf3598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bedf008e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bedf008b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6af832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6af8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6af8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bedf008a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (674 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_bf16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_f16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnb_f8_f32( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtnb.nxv4f32( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_f8_f32( %zd, %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zd.addr = alloca , align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store %zd, ptr %zd.addr, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load , ptr %zd.addr, align 16 # | %3 = load { , }, ptr %zn_zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | %7 = call @llvm.aarch64.sve.fp8.cvtnt.nxv4f32( %2, %4, %5) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f58815eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f58815be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f58815f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff862449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff862449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff862431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5880f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5880f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5880d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f587d88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f587d88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff862432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f587d88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (675 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640cfbf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640cfbf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640cfbfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f07649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f076a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f07649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f07631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640cfb8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640cfb8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640cfb748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640cf823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640cf823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f07632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f076330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f076330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640cf823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c1b224eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c1b221e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c1b22562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0aab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0aab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0aab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0aaaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c1b1babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c1b1baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c1b19f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c1ae4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c1ae4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0aaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0aaaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0aaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c1ae4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7c3d8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7c3d8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7c3d8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f053b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f053b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f053b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f053b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7c3d24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7c3d24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7c3d098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7c39b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7c39b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f053b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f053b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f053b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7c39b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (678 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrga # | ... # `---data was truncated (10240/28435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585884e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585884dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585884e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8189333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f818938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8189333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f818931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558588477bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558588477a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055858845c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055858810be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055858810bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f818931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f818931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f818931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055858810ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (679 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__ret.i, align 8 # | %2 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__ret.i, align 8 # | %2 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__ret.i, align 8 # | %2 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__ret.i, align 16 # | %2 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__ret.i, align 16 # | %2 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__ret.i, align 16 # | %2 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 { # | entry: # | # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055adabf29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055adabf26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055adabf2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbac6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbac6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbac6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbac6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adabebfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055adabebfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055adabea48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055adabb53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055adabb53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbac6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbac6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbac6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adabb53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (680 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = # | ... # `---data was truncated (10240/15126) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557aed6beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557aed6bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557aed6bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9423533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f942358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9423533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f942351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aed654bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557aed654a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557aed6398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557aed2e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557aed2e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f942351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f942351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f942351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aed2e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (681 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_f64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr # | ... # `---data was truncated (10240/12466) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b455148eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b455145e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b45514962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27f8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27f8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27f8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27f8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4550debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4550dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4550c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b454d72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b454d72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27f8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27f8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27f8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b454d72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (682 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f334f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f334f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f334fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea45b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea45b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea45b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea45b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f3348fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f3348fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f334748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f33123e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f33123b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea45b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea45b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea45b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f33123a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (683 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055acb6e83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acb6e80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acb6e8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acb6e19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acb6e19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acb6dfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acb6aade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acb6aadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acb6aada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617a7f97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617a7f94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617a7f9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd666533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd66658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd666533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd66651b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617a7f2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617a7f2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617a7f128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617a7bc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617a7bc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd66651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd66651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd66651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617a7bc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (685 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx. # | ... # `---data was truncated (10240/28427) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e414671eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e41466ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e41467262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f273cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f273cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f273cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f273cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e414607bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e414607a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4145ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e41429be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e41429bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f273cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f273cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f273cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e41429ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (686 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7aed83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7aed80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7aed8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc5be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc5bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc5be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc5be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7aed19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7aed19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7aecfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7ae9ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7ae9adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc5be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc5be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc5be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7ae9ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (687 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4f32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2f64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562b05dbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b05db9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b05dbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a2a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a2a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a2a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a2a203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b05d52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b05d52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b05d378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b059e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b059e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a2a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a2a2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a2a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b059e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb60416eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb60413e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb6041762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3147849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31478a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3147849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3147831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb603acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb603aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb603918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb60040e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb60040b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3147832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31478330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31478330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb60040a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (689 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # | #0 0x0000555cb198aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cb1987e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cb198b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a75533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a7558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a75533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a7551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cb1920bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cb1920a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cb19058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cb15b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cb15b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a7551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a7551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a7551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cb15b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589221b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589221b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589221b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f551fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f551fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f551fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f551fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055892214dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055892214da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589221328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558921de1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558921de1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f551fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f551fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f551fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558921de1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625b4f75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625b4f72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625b4f7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f110df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f110df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f110df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f110df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625b4f0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625b4f0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625b4ef08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625b4b9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625b4b9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f110df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f110df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f110df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625b4b9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af7f454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af7f451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af7f45562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff58821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5882725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff58821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff588203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af7f3eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af7f3eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af7f3cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af7f07ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af7f07eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff588204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5882050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5882050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af7f07ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f558caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f558c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f558cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5200533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f520058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5200533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f520051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f55860bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f55860a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f558458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f554f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f554f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f520051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f520051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f520051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f554f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (694 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4743b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4743b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4743ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feabc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feabc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feabc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feabc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e47434fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e47434fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4743348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e473fe3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e473fe3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feabc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feabc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feabc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e473fe3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/68141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562141c31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562141c2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562141c3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc102733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc10278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc102733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc10271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562141bc7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562141bc7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562141bac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056214185be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056214185bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc10271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc10271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc10271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056214185ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (696 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000565014e82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565014e7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565014e8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fed733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fed78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fed733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fed71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565014e18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565014e18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565014dfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565014aace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565014aacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fed71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fed71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fed71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565014aaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586b7d2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586b7d27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586b7d2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce0ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce0ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce0ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce0aced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586b7cc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586b7cc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586b7ca58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586b7954e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586b7954b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce0aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce0acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce0acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586b7954a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (698 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b57c156eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b57c153e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b57c15762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d70933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d7098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d70933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d7091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b57c0ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b57c0eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b57c0d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b57bd80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b57bd80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d7091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d7091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d7091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b57bd80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055946359ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559463599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055946359d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9575533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f957558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9575533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f957551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559463532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559463532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594635178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594631c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594631c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f957551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f957551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f957551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594631c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (700 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555bb2489eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bb2486e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bb248a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1234049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1234049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1234031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bb241fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bb241fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bb24048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bb20b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bb20b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1234032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12340330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bb20b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (701 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | ... # `---data was truncated (10240/34217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a044ba0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a044b9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a044ba162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f846d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f846d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f846d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f846d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a044b36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a044b36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a044b1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0447cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0447cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f846d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f846d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f846d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0447caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (702 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = sub <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fsub <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = sub <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fsub <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005631ad5daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631ad5d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631ad5db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dfe733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dfe78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dfe733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dfe71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631ad570bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631ad570a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631ad5558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631ad204e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631ad204b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4dfe71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dfe71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dfe71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631ad204a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7b481ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7b4819e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7b481d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf7603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7b47b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7b47b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7b47978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7b4446e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7b4446b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cf7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf76050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7b4446a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (704 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vf # | ... # `---data was truncated (10240/117019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f92099eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f92096e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f9209a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff045249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0452a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff045249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff045231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f9202fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f9202fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f920148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f91cc3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f91cc3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff045232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0452330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0452330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f91cc3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (705 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e2ff73ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2ff739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2ff73d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96d731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2ff6d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2ff6d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2ff6b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2ff366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2ff366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96d731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2ff366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (706 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | # | ... # `---data was truncated (10240/31781) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fc55f2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc55f2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc55f2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1517c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1517c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1517c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1517c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc55ec3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc55ec3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc55ea88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc55b57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc55b57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1517c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1517c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1517c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc55b57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a32193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a32190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a3219462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e54a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e54aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e54a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e54a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a32129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a32129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a3210e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a31dbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a31dbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e54a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e54a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e54a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a31dbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d65ec9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d65ec99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d65ec9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4b2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4b2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4b2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4b2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d65ec32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d65ec32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d65ec178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d65e8c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d65e8c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4b2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4b2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4b2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d65e8c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (709 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bca59f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bca59f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bca59f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16c3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bca598cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bca598ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bca59718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bca5620e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bca5620b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bca5620a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055650ac65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055650ac62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055650ac6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d60933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d60933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055650abfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055650abfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055650abe08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055650a88fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055650a88fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d6091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055650a88fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (711 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fb6da6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb6da6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb6da7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb82c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb82c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb82c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb82c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb6da05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb6da05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb6d9ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb6d699e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb6d699b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb82c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb82c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb82c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb6d699a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (712 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/79071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601c6c9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601c6c99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601c6c9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32e4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32e478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32e4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32e471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601c6c32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005601c6c32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601c6c178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005601c68c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005601c68c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32e471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32e471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32e471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601c68c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (713 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align # | ... # `---data was truncated (10240/43617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560232ef6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560232ef3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560232ef762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71d9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71d998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71d9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71d991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560232e8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560232e8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560232e718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560232b20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560232b20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71d991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71d991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71d991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560232b20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (714 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c52747eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c52744e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c5274862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc14f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc14f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc14f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc14eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c526ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c526dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c526c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c52371e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c52371b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc14eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc14eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc14eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c52371a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (715 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056192262beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561922628e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056192262c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ea4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ea46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ea4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ea4631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619225c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619225c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619225a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561922255e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561922255b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ea4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ea46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ea46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561922255a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bde8ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bde8fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bde90062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dff01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dff0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dff01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dff003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bde895bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bde895a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bde87a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bde529e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bde529b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5dff004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dff0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dff0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bde529a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (718 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2, align 8 # | %extract = extractelement <1 x double> %5, i32 0 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.fma.f64(double, double, double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <2 x double>, ptr %__s2, align 16 # | %extract = extractelement <2 x double> %5, i32 1 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret_443 = alloca float, align 4 # | %__s0_443 = alloca float, align 4 # | %__s1_443 = alloca float, align 4 # | %__s2_443 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_443, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1_443, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2_443, align 8 # | %3 = load float, ptr %__s0_443, align 4 # | store float %3, ptr %__s0, align 4 # | %4 = load float, ptr %__s1_443, align 4 # | %fneg = fneg float %4 # | store float %fneg, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2_443, align 8 # | store <2 x float> %5, ptr %__s2, align 8 # | %6 = load float, ptr %__s0, align 4 # | %7 = load float, ptr %__s1, align 4 # | %8 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %8, i32 1 # | %9 = call float @llvm.fma.f32(float %7, float %extract, float %6) # | store float %9, ptr %ref.tmp, align 4 # | %10 = load float, ptr %ref.tmp, align 4 # | store float %10, ptr %__ret, align 4 # | %11 = load float, ptr %__ret, align 4 # | store float %11, ptr %tmp, align 4 # | %12 = load float, ptr %tmp, align 4 # | store float %12, ptr %__ret_443, align 4 # | %13 = load float, ptr %__ret_443, align 4 # | store float %13, ptr %tmp1, align 4 # | %14 = load float, ptr %tmp1, align 4 # | ret float %14 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.fma.f32(float, float, float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret_449 = alloca <1 x double>, align 8 # | %__s0_449 = alloca <1 x double>, align 8 # | %__s1_449 = alloca <1 x double>, align 8 # | %__s2_449 = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | %tmp3 = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0_449, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_449, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2_449, align 8 # | %3 = load <1 x double>, ptr %__s0_449, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s1_449, align 8 # | %fneg = fneg <1 x double> %4 # | store <1 x double> %fneg, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2_449, align 8 # | store <1 x double> %5, ptr %__s2, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = load <8 x i8>, ptr %__s1, align 8 # | %8 = load <8 x i8>, ptr %__s2, align 8 # | %9 = bitcast <8 x i8> %8 to <1 x double> # | %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %7 to <1 x double> # | %fmla1 = bitcast <8 x i8> %6 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %10 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %10, ptr %__ret, align 8 # | %11 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %11, ptr %tmp, align 8 # | %12 = load <1 x double>, ptr %tmp, align 8 # | store <1 x double> %12, ptr %__ret_449, align 8 # | %13 = load <1 x double>, ptr %__ret_449, align 8 # | store <1 x double> %13, ptr %tmp3, align 8 # | %14 = load <1 x double>, ptr %tmp3, align 8 # | ret <1 x double> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret_460 = alloca <1 x double>, align 8 # | %__s0_460 = alloca <1 x double>, align 8 # | %__s1_460 = alloca <1 x double>, align 8 # | %__s2_460 = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %_ # | ... # `---data was truncated (10240/12799) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563851348eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563851345e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056385134962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f311881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31188725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f311881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3118803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638512debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638512dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638512c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563850f72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563850f72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3118804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31188050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31188050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563850f72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (719 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 { # | entry: # | ret target("aarch64.svcount") zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056322b6d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056322b6d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056322b6d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa21bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa21bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa21bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa21bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056322b669bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056322b669a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056322b64e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056322b2fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056322b2fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa21bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa21bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa21bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056322b2fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (721 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s16_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv2i64( %5, %6, %7, %8, i32 16) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv2i64(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/33461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005640fdbb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640fdbb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640fdbb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bdb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bdb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bdb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bdb631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640fdb4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640fdb4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640fdb308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640fd7dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640fd7dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bdb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bdb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bdb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640fd7dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (722 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559a3c7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559a3c7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559a3c7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e8ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e8eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e8ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e8ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559a3c14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559a3c14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559a3bf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559a38a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559a38a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e8ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e8ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e8ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559a38a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556305c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556305c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556305c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f708a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f708a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f708a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f708a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556305c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556305c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556305bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563058a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563058a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f708a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f708a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f708a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563058a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (725 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (726 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557106f46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557106f43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557106f4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7584c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7584c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7584c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7584c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557106edcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557106edca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557106ec18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557106b70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557106b70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7584c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7584c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7584c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557106b70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (727 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.fr # | ... # `---data was truncated (10240/27970) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a204ae1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a204adee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a204ae262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dc3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dc38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dc3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dc3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a204a77bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a204a77a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a204a5c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a20470be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a20470bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dc3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dc38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dc38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a20470ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (728 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625759f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625759f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625759fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1da333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1da38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1da333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1da31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056257598fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056257598fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625759748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562575623e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562575623b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1da31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1da31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1da31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562575623a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (729 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # | #0 0x00005636c113feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636c113ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636c114062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb26ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb26ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb26ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb26ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636c10d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636c10d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636c10ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636c0d69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636c0d69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb26ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb26ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb26ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636c0d69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (730 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <8 x half> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <4 x float> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ef19d89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef19d86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef19d8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b85e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b85ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b85e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b85e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef19d1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef19d1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef19d048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef199b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef199b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b85e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b85e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b85e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef199b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (731 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %p0.addr = alloca <8 x half>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <8 x half> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <8 x half>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e03c8ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e03c8fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e03c90062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe117f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe117f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe117f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe117f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e03c895bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e03c895a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e03c87a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e03c529e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e03c529b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe117f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe117f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe117f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e03c529a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (732 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.rbit.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.rbit.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (733 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (734 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (735 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647a3555eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647a3552e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647a355662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c10133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c1018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c10133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c1011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647a34ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647a34eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647a34d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647a317fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647a317fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c1011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c1011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c1011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647a317fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (737 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055776430deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055776430ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055776430e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bf041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bf04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bf041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bf0403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577642a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577642a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577642888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557763f37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557763f37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bf0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bf04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bf04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557763f37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (738 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svadda_f16( %pg, half noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca half, align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store half %initial, ptr %initial.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load half, ptr %initial.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call half @llvm.aarch64.sve.fadda.nxv8f16( %3, half %1, %2) # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fadda.nxv8f16(, half, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svadda_f32( %pg, float noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca float, align 4 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store float %initial, ptr %initial.addr, align 4 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load float, ptr %initial.addr, align 4 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call float @llvm.aarch64.sve.fadda.nxv4f32( %3, float %1, %2) # | ret float %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fadda.nxv4f32(, float, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svadda_f64( %pg, double noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca double, align 8 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store double %initial, ptr %initial.addr, align 8 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load double, ptr %initial.addr, align 8 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call double @llvm.aarch64.sve.fadda.nxv2f64( %3, double %1, %2) # | ret double %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fadda.nxv2f64(, double, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cc6c4d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc6c4cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc6c4d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b1de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b1de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b1de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b1de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc6c468bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc6c468a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc6c44d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc6c0fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc6c0fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b1de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b1de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b1de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc6c0fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (739 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d1efd27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1efd24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1efd2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8808649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88086a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8808649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8808631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1efcbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1efcbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1efca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1ef951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1ef951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8808632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88086330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88086330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1ef951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (740 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrun_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrun.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e8b43f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8b43f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8b43f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff671249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff671249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff671231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8b438dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8b438da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8b43728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8b4021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8b4021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff671232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6712330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8b4021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (741 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005593cea56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593cea53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593cea5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f34249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f342a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f34249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f34231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593ce9ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593ce9eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593ce9d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593ce680e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593ce680b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f34232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f342330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f342330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593ce680a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (742 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_b( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | %x2.addr = alloca , align 2 # | %x4.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | store %x2, ptr %x2.addr, align 2 # | store %x4, ptr %x4.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = load , ptr %x2.addr, align 2 # | %3 = load , ptr %x4.addr, align 2 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561a53db3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a53db0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a53db462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f073b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f073b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f073b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f073b831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a53d49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a53d49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a53d2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a539dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a539ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f073b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f073b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f073b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a539dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588a703deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588a703ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588a703e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f243fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f243fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f243fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f243fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588a6fd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588a6fd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588a6fb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588a6c67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588a6c67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f243fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f243fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f243fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588a6c67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (744 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu( %maske # | ... # `---data was truncated (10240/75397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a4737feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a4737ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a4738062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aaa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aaa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aaa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aaa431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a47315bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a47315a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a472fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a46fa9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a46fa9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0aaa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aaa4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aaa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a46fa9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (745 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (746 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcb9268eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fcb9265e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fcb926962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f875e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f875e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f875e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f875e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcb91febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fcb91fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fcb91e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fcb8e92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fcb8e92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f875e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f875e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f875e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcb8e92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7a29a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7a29a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7a29a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbed7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbed78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbed7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbed7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7a293ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7a293ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7a29238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7a25d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7a25d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbed7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbed78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbed78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7a25d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (748 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16() #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b4ec856eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4ec853e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4ec85762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f88e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f88e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f88e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f88e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4ec7ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4ec7eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4ec7d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4ec480e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4ec480b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f88e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f88e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f88e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4ec480a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (749 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e34d953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e34d950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e34d95462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a30733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a3078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a30733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a3071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e34d8e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e34d8e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e34d8ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e34d57de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e34d57db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a3071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a3071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a3071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e34d57da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606eca57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005606eca54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005606eca5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4232249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4232249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4232231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606ec9edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005606ec9eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606ec9d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606ec681e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606ec681b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4232232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42322330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606ec681a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (751 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005598aac79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598aac76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598aac7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f695a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f695a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f695a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f695a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598aac0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598aac0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598aabf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598aa8a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598aa8a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f695a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f695a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f695a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598aa8a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/22375) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654515e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654515e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654515e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa515f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa515f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa515f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa515f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565451579bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565451579a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056545155e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056545120de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056545120db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa515f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa515f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa515f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056545120da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (753 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6e2459eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6e2456e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6e245a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c00733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c0078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c00733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c0071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6e23efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6e23efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6e23d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6e2083e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6e2083b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c0071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c0071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c0071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6e2083a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (754 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b081250eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b08124de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b08125162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb3ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb3ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb3ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb3ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0811e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0811e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0811cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b080e7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b080e7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb3ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb3ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb3ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b080e7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (755 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556502c79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556502c76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556502c7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffab6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffab658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffab6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffab651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556502c0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556502c0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556502bf48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565028a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565028a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffab651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffab651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffab651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565028a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, a # | ... # `---data was truncated (10240/81515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f320d21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f320d1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f320d2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb06133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb0618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb06133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb0611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f320cb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f320cb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f320c9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f32094be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f32094bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb0611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb0611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb0611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f32094ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (758 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.a # | ... # `---data was truncated (10240/28771) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005632278c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632278c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632278c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f749b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f749b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f749b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f749b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056322785abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056322785aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056322783f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632274eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632274eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f749b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f749b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f749b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632274eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aac282eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558aac27fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558aac28362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c47049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c470a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c47049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c47031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aac218bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558aac218a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558aac1fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558aabeace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558aabeacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c47032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c470330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c470330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aabeaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (760 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 3 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 2 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_374 = alloca <4 x bfloat>, align 8 # | %__s0_374 = alloca <4 x bfloat>, align 8 # | %__s2_374 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.add # | ... # `---data was truncated (10240/18871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c8748eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c8748be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c8748f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7ea705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7ea75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7ea705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7ea6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c87424bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c87424a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c874098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c870b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c870b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7ea6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7ea6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7ea6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c870b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , flo # | ... # `---data was truncated (10240/34773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591f2a51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591f2a4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591f2a5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9345333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f934538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9345333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f934531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591f29e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591f29e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591f29cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591f267be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591f267bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f934531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f934531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f934531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591f267ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edaeebceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055edaeeb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055edaeebd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81d9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81d9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81d9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81d9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edaee52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055edaee52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055edaee378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055edaeae6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055edaeae6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81d9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81d9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81d9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edaeae6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9a3080eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9a307de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9a308162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa57e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa57e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa57e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa57e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9a3016bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9a3016a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9a2ffb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9a2caae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9a2caab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa57e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa57e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa57e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9a2caaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (764 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , # | ... # `---data was truncated (10240/154207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561416467eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561416464e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056141646862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbfed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbfed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbfed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbfeced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614163fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614163fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614163e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561416091e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561416091b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdbfeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbfecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbfecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561416091a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (765 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2561c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2561c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2561c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bfab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bfab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bfab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bfab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e25615dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e25615da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2561428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e255df1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e255df1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bfab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bfab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bfab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e255df1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a42481eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a4247ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4248262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dc2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dc278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dc2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dc271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a42417bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a42417a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a423fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a420abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a420abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8dc271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dc271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dc271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a420aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (767 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561f8c7cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f8c7cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f8c7ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feefcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feefcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feefcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feefcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f8c763bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f8c763a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f8c7488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f8c3f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f8c3f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feefcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feefcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feefcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f8c3f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (768 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055cd4a9daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd4a9d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd4a9db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bab533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bab58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bab533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bab51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd4a970bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd4a970a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd4a9558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd4a604e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd4a604b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bab51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bab51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bab51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd4a604a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583131e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583131dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583131e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7474a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7474aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7474a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7474a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558313177bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558313177a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055831315c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558312e0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558312e0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7474a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7474a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7474a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558312e0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv64i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr # | ... # `---data was truncated (10240/26240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055914f7d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055914f7d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055914f7d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3600f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3600f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3600f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3600f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055914f76ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055914f76ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055914f7538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055914f402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055914f402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3600f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3600f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3600f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055914f402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (771 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005596aeae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596aeae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596aeaea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f440a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f440a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f440a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f440a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596aea7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596aea7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596aea648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596ae713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596ae713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f440a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f440a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f440a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596ae713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (772 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c25524eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c25521e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c2552562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bfa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bfa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bfa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bfa831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c254babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c254baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c2549f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c2514ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c2514eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bfa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bfa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bfa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c2514ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (773 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559bf5e72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bf5e6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bf5e7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c49249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c492a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c49249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c49231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bf5e08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bf5e08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bf5ded8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bf5a9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bf5a9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c49232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c492330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c492330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bf5a9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (774 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cae6c1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cae6c18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cae6c1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91d8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91d8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91d8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91d8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cae6bb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cae6bb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cae6b968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cae6845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cae6845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91d8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91d8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91d8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cae6845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (775 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (776 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_s64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(, , , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_u64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(, , ptr, ) #4 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_u64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a6d6f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a6d6efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a6d6f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd997733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd99778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd997733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd99771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a6d688bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a6d688a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a6d66d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a6d31ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a6d31cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd99771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd99771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd99771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a6d31ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (778 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055bc555ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc555e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc555ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0cd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0cd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0cd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0cd831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc55581bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc55581a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc555668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc55215e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc55215b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0cd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0cd8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0cd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc55215a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603bc5edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603bc5eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603bc5ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfbcf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfbcf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfbcf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfbceed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603bc583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603bc583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603bc5688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603bc217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603bc217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfbceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfbceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfbceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603bc217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6d6a19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6d6a16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6d6a1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a25c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a25ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a25c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a25c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6d69afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6d69afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6d69948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6d6643e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6d6643b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a25c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a25c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a25c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6d6643a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (781 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (782 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x half>, align 16 # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca <32 x half>, align 16 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %b.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store <32 x half> %b, ptr %b.addr, align 16 # | %0 = load <32 x ha # | ... # `---data was truncated (10240/161192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000561e36038eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e36035e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e3603962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0531f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0531f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0531f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0531f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e35fcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e35fcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e35fb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e35c62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e35c62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0531f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0531f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0531f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e35c62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dfd570eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dfd56de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dfd57162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2f0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2f0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2f0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2f0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dfd506bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dfd506a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dfd4eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dfd19ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dfd19ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2f0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2f0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2f0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dfd19aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (784 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfadc8aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfadc87e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfadc8b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6072249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6072249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6072231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfadc20bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfadc20a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfadc058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfad8b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfad8b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6072232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60722330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfad8b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (785 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005565dbd8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565dbd88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565dbd8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdda4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdda438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdda4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdda431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565dbd21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565dbd21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565dbd068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565db9b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565db9b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdda431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdda431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdda431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565db9b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (786 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_s8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn1.coerce3, 3 # | store { , , , } %3, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %4 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zn2.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zn2.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zn2.coerce3, 3 # | store { , , , } %7, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %9 = load { , , , }, ptr %zn1.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zn2.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | %19 = call { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret { , , , } %19 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_u8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %zn3.addr = alloca { , , , }, align 16 # | %zn4.addr = alloca { , , , }, align 16 # | %2 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %3 = insertvalue { , , , } %2, %zn1.coerce1, 1 # | %4 = insertvalue { , , , } %3, %zn1.coerce2, 2 # | %5 = insertvalue { , , , } %4, %zn1.coerce3, 3 # | store { , , , } %5, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %6 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %7 = insertvalue { , , , } %6, %zn2.coerce1, 1 # | %8 = insertvalue { , , , } %7, %zn2.coerce2, 2 # | %9 = insertvalue { , , , } %8, %zn2.coerce3, 3 # | store { , , , } %9, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | %zn3 = load { , , , }, ptr %0, align 16 # | %zn4 = load { , , , }, ptr %1, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | store { , , , } %zn3, ptr %zn3.addr, align 16 # | store { , , , } %zn4, ptr %zn4.addr, align 16 # | %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %11 = load { , , , }, ptr %zn1.addr, align 16 # | %12 = extractvalue { , , , } %11, 0 # | %13 = extractvalue { , , , } %11, 1 # | %14 = extractvalue { , , , } %11, 2 # | %15 = extractvalue { , , , } %11, 3 # | %16 = load { , , , }, ptr %zn2.addr, align 16 # | %17 = extractvalue { , , , } %16, 0 # | %18 = extractvalue { , , , } %16, 1 # | %19 = extractvalue { , , , } %16, 2 # | %20 = extractvalue { , , , } %16, 3 # | %21 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (787 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (788 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , < # | ... # `---data was truncated (10240/117389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612b1f5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612b1f5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612b1f5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1fba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1fbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1fba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1fba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612b1ef3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612b1ef3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612b1ed88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612b1b87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612b1b87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1fba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1fba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1fba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612b1b87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (789 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/134744) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e34593beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e345938e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e34593c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8428049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84280a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8428049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8428031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3458d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3458d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3458b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e345565e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e345565b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8428032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84280330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84280330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e345565a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (790 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff45f9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff45f9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff45fa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe602449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe602449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe602431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff45f35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff45f35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff45f1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff45bc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff45bc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe602432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6024330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff45bc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (791 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005576cea5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576cea5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576cea6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8647733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f864778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8647733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f864771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576ce9f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576ce9f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576ce9da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576ce689e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576ce689b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f864771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f864771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f864771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576ce689a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (792 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/100952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055faf9404eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faf9401e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faf940562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fd6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fd6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fd6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fd6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faf939abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faf939aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faf937f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055faf902ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055faf902eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fd6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fd6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fd6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faf902ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (793 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/151245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e4bab8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e4bab5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e4bab962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9de6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9de6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9de6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9de6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e4ba4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e4ba4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e4ba338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e4b6e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e4b6e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9de6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9de6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9de6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e4b6e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557133283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557133280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055713328462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52ef649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52ef6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52ef649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52ef631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557133219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557133219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571331fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557132eade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557132eadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52ef632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52ef6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52ef6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557132eada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (795 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 16 # | %__s0_827 = alloca <4 x i32>, align 16 # | %__s1_827 = alloca <16 x i8>, align 16 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp2 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_827, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1_827, align 16 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 16 # | %4 = load <16 x i8>, ptr %__s1_827, align 16 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__ # | ... # `---data was truncated (10240/29862) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x0000564c75703eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c75700e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c7570462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a34c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a34ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a34c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a34c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c75699bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c75699a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c7567e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c7532de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c7532db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a34c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a34c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a34c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c7532da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (797 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561345504eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561345501e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056134550562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6877b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6877b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6877b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6877aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056134549abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056134549aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056134547f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056134512ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056134512eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6877aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6877aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6877aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056134512ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (798 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = # | ... # `---data was truncated (10240/19190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653a540beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653a5408e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653a540c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f708f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f708f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f708f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f708f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653a53a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653a53a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653a53868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653a5035e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653a5035b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f708f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f708f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f708f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653a5035a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (799 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bf9e53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bf9e50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bf9e5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d6b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d6b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d6b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d6b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bf9de9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bf9de9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bf9dce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bf9a7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bf9a7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d6b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d6b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d6b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bf9a7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d362b93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d362b90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d362b9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ea8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ea86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ea8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ea8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d362b29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d362b29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d362b0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3627bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3627bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ea8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ea86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ea86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3627bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (802 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634312c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634312c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634312c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc026b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc026b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc026b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc026b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056343125ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056343125ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634312438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563430ef2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563430ef2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc026b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc026b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc026b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563430ef2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (803 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005581f2cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581f2cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581f2cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda6e61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda6e6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda6e61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda6e603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581f2c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581f2c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581f2c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581f2906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581f2906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda6e604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda6e6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda6e6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581f2906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub # | ... # `---data was truncated (10240/84979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056135c015eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056135c012e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056135c01662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1411049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14110a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1411049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1411031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056135bfabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056135bfaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056135bf908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056135bc3fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056135bc3fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1411032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14110330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14110330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056135bc3fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/thinlto_backend.ll (805 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # | #0 0x000055a39b992eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a39b98fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a39b99362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9255649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9255649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9255631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a39b928bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a39b928a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a39b90d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a39b5bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a39b5bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9255632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92556330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a39b5bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562688a80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562688a7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562688a8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e47f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e47f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e47f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e47f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562688a16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562688a16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626889fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626886aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626886aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e47f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e47f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e47f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626886aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr % # | ... # `---data was truncated (10240/66087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055902f56ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055902f569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055902f56d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab04533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab0458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab04533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab0451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055902f502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055902f502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055902f4e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055902f196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055902f196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab0451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab0451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab0451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055902f196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (808 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d3e05feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d3e05ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d3e06062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68e0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68e0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68e0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68e0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d3dff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d3dff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d3dfda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d3dc89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d3dc89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f68e0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68e0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68e0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d3dc89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056409d6f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056409d6f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056409d6f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfd4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfd40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfd4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfd4031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056409d68dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056409d68da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056409d6728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056409d321e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056409d321b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfd4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfd40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfd40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056409d321a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (810 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b53877eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b53874e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b5387862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f801c305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f801c35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f801c305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f801c2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b5380dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b5380da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b537f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b534a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b534a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f801c2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f801c2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f801c2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b534a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (811 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561e8e019eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e8e016e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e8e01a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feea5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feea5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feea5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feea5aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e8dfafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e8dfafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e8df948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e8dc43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e8dc43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feea5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feea5aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feea5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e8dc43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af40dfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af40dfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af40dfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cd9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cd9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cd9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cd9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af40d93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af40d93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af40d788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af40a27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af40a27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cd9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cd9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cd9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af40a27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (814 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp sge <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp uge <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp sge <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055729ecb0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055729ecade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055729ecb162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdea8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdea8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdea8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdea8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055729ec46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055729ec46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055729ec2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055729e8dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055729e8dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdea8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdea8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdea8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055729e8daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (815 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z_1( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 270) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv2f64(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.ad # | ... # `---data was truncated (10240/12234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ca4ad3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca4ad3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca4ad3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee48649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee486a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee48649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee48631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca4acd3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca4acd3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca4acb88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca4a967e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca4a967b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee48632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee486330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee486330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca4a967a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/246614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e283bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e283bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e283c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34acd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34acd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34acd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34acd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e28355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e28355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e2833a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e27fe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e27fe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34acd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34acd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34acd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e27fe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (817 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556906c4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556906c4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556906c5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80d971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556906be5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556906be5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556906bca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556906879e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556906879b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80d971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556906879a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (818 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9ec88aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9ec887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9ec88b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60ce933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60ce98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60ce933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60ce91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9ec820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9ec820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9ec8058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9ec4b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9ec4b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60ce91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60ce91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60ce91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9ec4b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (819 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a13999eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a13996e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a1399a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f17831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a1392fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a1392fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a139148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a135c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a135c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a135c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (820 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611c73d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611c73d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611c73d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bda849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bda8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bda849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bda831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611c736dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611c736da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611c73528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611c7001e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611c7001b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7bda832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bda8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bda8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611c7001a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e921f7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e921f7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e921f7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff719a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff719aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff719a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff719a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e921f14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e921f14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e921ef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e921ba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e921ba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff719a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff719a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff719a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e921ba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3d59cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3d59cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3d59ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d98105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d9815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d98105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d980ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d5963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3d5963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3d59488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3d55f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3d55f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d980eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d980ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d980ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d55f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (823 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6306e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6306e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6306ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb5d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb5d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb5d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb5d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b63067fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b63067fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6306648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b630313e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b630313b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb5d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb5d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb5d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b630313a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b6d29aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b6d297e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b6d29b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f9d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f9d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f9d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f9d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b6d230bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b6d230a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b6d2158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b6cec4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b6cec4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f9d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f9d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f9d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b6cec4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593691b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593691afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593691b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94d6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94d615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94d6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94d60ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559369148bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559369148a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055936912d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559368ddce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559368ddcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94d60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94d60ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94d60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559368ddca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (826 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | call void @llvm.aarch64.sve.st3.nxv16i8.p0( %6, %7, %8, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %3) # | call void @llvm.aarch64.sve.st3.nxv8i16.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %3) # | call void @llvm.aarch64.sve.st3.nxv4i32.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %3) # | call void @llvm.aarch64.sve.st3.nxv2i64.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = al # | ... # `---data was truncated (10240/58378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a115567eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a115564e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a11556862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcf3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcf38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcf3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcf3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1154fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1154fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1154e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a115191e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a115191b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcf3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcf38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcf38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a115191a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (827 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 { # | entry: # | %cnt.addr = alloca target("aarch64.svcount"), align 2 # | store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2 # | %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount( %0) # | ret target("aarch64.svcount") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556068c15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556068c12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556068c1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fb9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fb9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fb9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fb9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556068babbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556068baba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556068b908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055606883fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055606883fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fb9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fb9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fb9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055606883fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (828 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d234defeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d234dece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d234df062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f338c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f338c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f338c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f338c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d234d85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d234d85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d234d6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d234a19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d234a19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f338c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f338c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f338c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d234a19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (829 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta # | ... # `---data was truncated (10240/10820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f3019c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3019c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3019c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3a831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f30195ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f30195ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3019438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3015f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3015f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3a831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3015f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (830 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed19231eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed1922ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed1923262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f343d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f343d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f343d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f343d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed191c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed191c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed191ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed18e5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed18e5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f343d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f343d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f343d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed18e5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a214cd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a214ccfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a214cd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d7cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d7cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d7cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d7cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a214c68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a214c68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a214c4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2148fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2148fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d7cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d7cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d7cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2148fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (832 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603e4e85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603e4e82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603e4e8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc704049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7040a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc704049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc704031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603e4e1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603e4e1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603e4e008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603e4aafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603e4aafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc704032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7040330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7040330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603e4aafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (833 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @xor_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (834 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %cmp = icmp eq <8 x i8> %2, %3 # | %sext = sext <8 x i1> %cmp to <8 x i8> # | store <8 x i8> %sext, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i32> # | store <16 x i32> %sext, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %cmp = icmp eq <8 x i64> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i64> # | store <8 x i64> %sext, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x # | ... # `---data was truncated (10240/78785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055d4c353feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4c353ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4c354062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4086733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f408678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4086733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f408671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4c34d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4c34d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4c34ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4c3169e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4c3169b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f408671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f408671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f408671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4c3169a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (835 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6ffe2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6ffe2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6ffe2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe59e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe59e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe59e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe59e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6ffdc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6ffdc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6ffda98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6ffa58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6ffa58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe59e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe59e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe59e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6ffa58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579950c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579950bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579950c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd781049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7810a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd781049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd781031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557995058bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557995058a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055799503d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557994cece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557994cecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd781032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7810330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7810330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557994ceca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsm # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d5ced4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d5ced1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d5ced562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f80733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f8078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f80733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f8071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d5ce6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d5ce6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d5ce4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d5cafee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d5cafeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f8071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f8071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f8071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d5cafea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641bf5dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641bf5dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641bf5e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cdf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cdf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cdf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cdf831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641bf575bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641bf575a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641bf55a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641bf209e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641bf209b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cdf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cdf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cdf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641bf209a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (840 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (841 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsetffr() #0 { # | entry: # | call void @llvm.aarch64.sve.setffr() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.setffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005614077d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614077d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614077d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe429c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe429ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe429c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe429c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056140776cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056140776ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614077518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561407400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561407400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe429c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe429c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe429c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561407400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (842 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | call void @llvm.aarch64.sve.st4.nxv16i8.p0( %7, %8, %9, %10, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %4) # | call void @llvm.aarch64.sve.st4.nxv8i16.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %4) # | call void @llvm.aarch64.sve.st4.nxv4i32.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %da # | ... # `---data was truncated (10240/73307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c9408e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9408e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9408e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b04133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b0418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b04133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b0411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c94087abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c94087aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c94085f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c94050ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c94050eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b0411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b0411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b0411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c94050ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (843 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055777675aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557776757e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055777675b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc81b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc81b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc81b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc81b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577766f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577766f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577766d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557776384e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557776384b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc81b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc81b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc81b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557776384a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (844 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <8 x i8>, ptr %__promote, align 8 # | store <8 x i8> %1, ptr %__ret, align 8 # | %2 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %2, ptr %tmp, align 8 # | %3 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <8 x i8>, align 8 # | %.compoundliteral.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> # | %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> # | %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> # | %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> # | %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> # | %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> # | %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> # | %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> # | %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> # | store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8 # | %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8 # | store <8 x i8> %9, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <16 x i8>, align 16 # | %.compoundliteral.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> # | %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> # | %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> # | %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> # | %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> # | %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> # | %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> # | %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> # | %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> # | %9 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> # | %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (845 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d61bedeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d61beae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d61bee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fb4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fb42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fb4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fb4231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d61b83bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d61b83a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d61b688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d61817e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d61817b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5fb4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fb42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fb42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d61817a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a386eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a386e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a386ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f871e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f871e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f871e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f871e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a38682bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a38682a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a386678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a38316e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a38316b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f871e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f871e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f871e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a38316a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (847 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 { # | entry: # | %__p0_824.addr.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8 # | store <4 x i16> %1, ptr %__s0.i, align 8 # | %2 = load <8 x i8>, ptr %__s0.i, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | %4 = zext <4 x i16> %3 to <4 x i32> # | %vshll_n.i = shl <4 x i32> %4, splat (i32 16) # | store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16 # | %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %5, ptr %__ret.i, align 16 # | %6 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %6, ptr %tmp.i, align 16 # | %7 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %7, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret_824.i, align 16 # | %9 = load <4 x float>, ptr %__ret_824.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | store <4 x bfloat> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8 # | store <4 x bfloat> %4, ptr %__ret.i, align 8 # | %5 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> # | store <8 x bfloat> %4, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %inactive.addr = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <8 x bfloat> %inactive, ptr %inactive.addr, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %inactive.addr, align 16 # | %1 = load <4 x float>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x bfloat> # | %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = fptrunc <4 x float> %6 to <4 x bfloat> # | %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> # | store <8 x bfloat> %8, ptr %ref.tmp.i, align 16 # | %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca bfloat, align 2 # | %ref.tmp.i = alloca bfloat, align 2 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | store bfloat %2, ptr %ref.tmp.i, align 2 # | %3 = load bfloat, ptr %ref.tmp.i, align 2 # | store bfloat %3, ptr %__ret.i, align 2 # | %4 = load bfloat, ptr %__ret.i, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca i32, align 4 # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load # | ... # `---data was truncated (10240/10974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561507312eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056150730fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056150731362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f663dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f663dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f663dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f663dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615072a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615072a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056150728d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561506f3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561506f3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f663dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f663dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f663dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561506f3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (848 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ab64456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab64453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab6445762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6522c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6522ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6522c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6522c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab643ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab643eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab643d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab64080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab64080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6522c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6522c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6522c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab64080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (850 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (851 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %.splat, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sudot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055aaab153eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aaab150e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aaab15462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa065c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa065ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa065c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa065c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aaab0e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aaab0e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aaab0ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aaaad7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aaaad7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa065c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa065c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa065c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaaad7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (852 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcba218eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcba215e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcba21962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9a3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9a338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9a3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9a331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcba1aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcba1aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcba1938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcb9e42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcb9e42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9a331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9a331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9a331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcb9e42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (853 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalt_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056390fb3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056390fb3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056390fb4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb19e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb19e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb19e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb19e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056390fad5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056390fad5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056390faba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056390f769e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056390f769b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb19e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb19e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb19e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056390f769a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055862932aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558629327e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055862932b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23ed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23ed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23ed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23ed031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586292c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586292c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586292a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558628f54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558628f54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23ed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23ed0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23ed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558628f54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c52c8aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c52c8a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c52c8ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6075d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6075d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6075d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6075d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c52c840bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c52c840a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c52c8258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c52c4d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c52c4d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6075d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6075d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6075d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c52c4d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (856 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005631b93bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631b93bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631b93c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71dc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71dc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71dc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71dc4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631b9355bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631b9355a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631b933a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631b8fe9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631b8fe9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71dc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71dc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71dc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631b8fe9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647b97c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647b97c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647b97c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefc4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefc4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefc4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefc4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647b975bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647b975ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647b97408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647b93efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647b93efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fefc4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefc4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefc4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647b93efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (858 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556306f06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556306f03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556306f0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc76de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc76dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc76de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc76de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556306e9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556306e9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556306e818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556306b30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556306b30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc76de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc76de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc76de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556306b30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (859 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2f7c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2f7c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2f7c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1abf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2f7c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2f7c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2f7c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2f78b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2f78b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2f78b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (861 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056285d02ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056285d029e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056285d02d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18c6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18c6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18c6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18c6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056285cfc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056285cfc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056285cfa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056285cc56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056285cc56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18c6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18c6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18c6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056285cc56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055570a6e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055570a6e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055570a6e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faae8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faae80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faae8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faae8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055570a67bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055570a67ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055570a6608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055570a30fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055570a30fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faae8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faae80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faae80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055570a30fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558461336eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558461333e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055846133762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1e501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1e50725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1e501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1e5003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584612ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584612cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584612b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558460f60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558460f60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1e5004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1e50050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1e50050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558460f60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (865 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ... # `---data was truncated (10240/69831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8fe95feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8fe95ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8fe96062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0df2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0df2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0df2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0df2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8fe8f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8fe8f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8fe8da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8fe589e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8fe589b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0df2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0df2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0df2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8fe589a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640127e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640127e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640127e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f307e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f307e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f307e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f307e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056401277ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056401277ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640127638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564012412e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564012412b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f307e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f307e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f307e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564012412a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (867 of 27910) ******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # | #0 0x0000556387aaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556387aa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556387aab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff471e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff471ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff471e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff471e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556387a40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556387a40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556387a258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563876d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563876d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff471e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff471e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff471e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563876d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (868 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pnext.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv8i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv8i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv4i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv4i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv2i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv2i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d45fa73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d45fa70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d45fa7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05d9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05d92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05d9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05d9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d45fa09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d45fa09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d45f9ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d45f69de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d45f69db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05d9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05d92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05d92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d45f69da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (869 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606f0b73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005606f0b70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005606f0b7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05c1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05c158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05c1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05c151b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606f0b09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005606f0b09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606f0aee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606f079de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606f079db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05c151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05c151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05c151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606f079da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599e7748eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599e7745e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599e774962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd020d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd020d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd020d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd020d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599e76debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599e76dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599e76c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599e7372e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599e7372b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd020d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd020d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd020d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599e7372a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (874 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fcae4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fcae48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fcae4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dfa905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dfa95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dfa905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dfa8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fcade1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fcade1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fcadc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fcaa75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fcaa75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0dfa8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dfa8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dfa8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fcaa75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (875 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (876 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4759aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4759a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4759ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf86849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf868a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf86849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf86831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e475940bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e475940a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4759258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4755d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4755d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf86832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf868330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf868330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4755d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (877 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv4f32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv2f64(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dc5174aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc51747e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc5174b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15c5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15c52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15c5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15c5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc516e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc516e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc516c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc51374e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc51374b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15c5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15c52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15c52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc51374a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (878 of 27910) ******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # | #0 0x0000556f13fb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f13fb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f13fb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7fe133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7fe18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7fe133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7fe11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f13f4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f13f4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f13f318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f13be0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f13be0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7fe11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7fe11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7fe11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f13be0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588bd73deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588bd73ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588bd73e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ae031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588bd6d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588bd6d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588bd6b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588bd367e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588bd367b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3ae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ae0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588bd367a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (880 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align # | ... # `---data was truncated (10240/39627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056462145aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564621457e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056462145b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfef61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfef6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfef61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfef603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646213f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646213f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646213d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564621084e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564621084b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfef604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfef6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfef6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564621084a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, a # | ... # `---data was truncated (10240/71115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556174f17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556174f14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556174f1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f428e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f428e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f428e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f428e403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556174eadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556174eada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556174e928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556174b41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556174b41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f428e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f428e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f428e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556174b41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (882 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630d9344eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630d9341e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630d934562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83d0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83d0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83d0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83d0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630d92dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630d92daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630d92bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630d8f6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630d8f6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83d0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83d0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83d0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630d8f6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-3v.c (884 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %and.i = and <8 x i16> %2, %3 # | store <8 x i16> %and.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %and.i = and <2 x i32> %2, %3 # | store <2 x i32> %and.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %and.i = and <4 x i32> %2, %3 # | store <4 x i32> %and.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %and.i = and <1 x i64> %2, %3 # | store <1 x i64> %and.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %and.i = and <2 x i64> %2, %3 # | store <2 x i64> %and.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, al # | ... # `---data was truncated (10240/70553) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055787524feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055787524ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055787525062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c48333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c4838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c48333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c4831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578751e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578751e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578751ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557874e79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557874e79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c4831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c4831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c4831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557874e79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/83080) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e71365aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e713657e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e71365b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c14b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c14b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c14b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c14b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7135f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7135f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7135d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e713284e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e713284b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c14b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c14b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c14b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e713284a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ccff5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ccff57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ccff5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f863f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f863f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f863f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f863f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ccfef0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ccfef0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ccfed58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ccfb84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ccfb84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f863f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f863f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f863f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ccfb84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (887 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/39578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056219e5f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056219e5f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056219e5f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3276049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3276049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3276031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056219e58dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056219e58da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056219e5728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056219e221e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056219e221b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3276032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32760330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056219e221a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639f1991eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639f198ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639f199262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf6c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf6c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf6c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf6c231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639f1927bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639f1927a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639f190c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639f15bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639f15bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf6c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf6c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf6c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639f15bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/427567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d92b18aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d92b187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d92b18b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc761849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7618a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc761849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc761831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d92b120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d92b120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d92b1058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d92adb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d92adb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc761832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7618330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7618330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d92adb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, # | ... # `---data was truncated (10240/60217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5de1d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5de1d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5de1d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b70049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b700a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b70049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b70031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5de169bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5de169a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5de14e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5dddfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5dddfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b70032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b700330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b700330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5dddfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (893 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (894 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_790 = alloca <4 x i16>, align 8 # | %__s0_790 = alloca <4 x i16>, align 8 # | %__s1_790 = alloca <4 x i16>, align 8 # | %__s2_790 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_790, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_790, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_790, align 16 # | %3 = load <4 x i16>, ptr %__s0_790, align 8 # | %4 = load <4 x i16>, ptr %__s1_790, align 8 # | %5 = load <8 x i16>, ptr %__s2_790, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_790, align 8 # | %16 = load <4 x i16>, ptr %__ret_790, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_788 = alloca <2 x i32>, align 8 # | %__s0_788 = alloca <2 x i32>, align 8 # | %__s1_788 = alloca <2 x i32>, align 8 # | %__s2_788 = alloca <4 x i32>, align 16 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_788, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_788, align 8 # | %2 = load <4 x i32>, ptr %v.addr, align 16 # | store <4 x i32> %2, ptr %__s2_788, align 16 # | %3 = load <2 x i32>, ptr %__s0_788, align 8 # | %4 = load <2 x i32>, ptr %__s1_788, align 8 # | %5 = load <4 x i32>, ptr %__s2_788, align 16 # | store <4 x i32> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x i32> # | %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <2 x i32> %4, ptr %__p1.addr.i, align 8 # | store <2 x i32> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %14 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %14, ptr %__ret.i, align 8 # | %15 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %15, ptr %__ret_788, align 8 # | %16 = load <2 x i32>, ptr %__ret_788, align 8 # | store <2 x i32> %16, ptr %tmp1, align 8 # | %17 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_786 = alloca <8 x i16>, align 16 # | %__s0_786 = alloca <8 x i16>, align 16 # | %__s1_786 = alloca <8 x i16>, align 16 # | %__s2_786 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_786, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_786, align 16 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_786, align 16 # | %3 = load <8 x i16>, ptr %__s0_786, align 16 # | %4 = load <8 x i16>, ptr %__s1_786, align 16 # | %5 = load <8 x i16>, ptr %__s2_786, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | store <8 x i16> %3, ptr %__p0.addr.i, align 16 # | store <8 x i16> %4, ptr %__p1.addr.i, align 16 # | store <8 x i16> %10, ptr %__p2.addr.i, align 16 # | %11 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %14 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %14, ptr %__ret.i, align 16 # | %15 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %15, ptr %__ret_786, align 16 # | %16 = load <8 x i16>, ptr %__ret_786, align 16 # | store <8 x i16> %16, ptr %tmp1, align 16 # | %17 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_784 = alloca <4 x i32>, align 16 # | %__s0_784 = alloca <4 x i32>, align 16 # | %__s1_784 = alloca <4 x i32>, align 16 # | %__s2_784 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <4 # | ... # `---data was truncated (10240/50621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x000056103cb45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056103cb42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056103cb4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c15449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c154a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c15449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c15431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056103cadbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056103cadba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056103cac08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056103c76fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056103c76fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c15432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c154330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c154330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056103c76fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (895 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.uabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (896 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625b8c1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625b8c1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625b8c2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2185305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f218535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2185305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21852ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625b8bb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005625b8bb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625b8b9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625b8849e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625b8849b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21852eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21852ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21852ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625b8849a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f6efa4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f6efa1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f6efa562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b0f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b0f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b0f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b0f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6ef3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f6ef3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f6ef1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f6ebcee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f6ebceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b0f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b0f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b0f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f6ebcea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (898 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056060c3fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056060c3f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056060c3fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77f2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77f2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77f2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77f2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056060c392bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056060c392a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056060c3778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056060c026e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056060c026b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77f2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77f2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77f2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056060c026a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function # | ... # `---data was truncated (10240/200802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b753f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b753f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b753f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee7bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee7bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee7bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee7bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b75389bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b75389a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b7536e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b7501de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b7501db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee7bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee7bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee7bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b7501da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (900 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_u8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_s8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eabee4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eabee48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eabee4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc00133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc0018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc00133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc0011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eabede1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eabede1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eabedc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eabea75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eabea75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc0011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc0011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc0011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eabea75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (901 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = c # | ... # `---data was truncated (10240/207083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d275adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d275aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d275ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe25f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe25f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe25f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe25f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d27543bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d27543a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d275288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d271d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d271d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe25f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe25f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe25f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d271d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (904 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a837075eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a837072e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a83707662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe693133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe69318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe693133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe69311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a83700bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a83700ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a836ff08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a836c9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a836c9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe69311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe69311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe69311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a836c9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fee88aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fee887e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fee88b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d69733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d6978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d69733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d6971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fee820bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fee820a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fee8058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fee4b4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fee4b4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d6971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d6971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d6971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fee4b4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (906 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p2.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %retval = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %c = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | %coerce4 = alloca <4 x half>, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b1 = load <4 x half>, ptr %b, align 8 # | store <2 x i32> %c.coerce, ptr %c, align 8 # | %c2 = load <4 x half>, ptr %c, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b1, ptr %b.addr, align 8 # | store <4 x half> %c2, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %1, ptr %coerce, align 8 # | %3 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %2, ptr %coerce3, align 8 # | %4 = load <2 x i32>, ptr %coerce3, align 8 # | store <2 x i32> %3, ptr %__p1.i, align 8 # | %__p11.i = load <4 x half>, ptr %__p1.i, align 8 # | store <2 x i32> %4, ptr %__p2.i, align 8 # | %__p22.i = load <4 x half>, ptr %__p2.i, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8 # | store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %7 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %9, ptr %retval.i, align 8 # | %10 = load <2 x i32>, ptr %retval.i, align 8 # | store <2 x i32> %10, ptr %coerce4, align 8 # | %11 = load <4 x half>, ptr %coerce4, align 8 # | store <4 x half> %11, ptr %retval, align 8 # | %12 = load <2 x i32>, ptr %retval, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p2.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %retval = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %c = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | %coerce4 = alloca <8 x half>, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b1 = load <8 x half>, ptr %b, align 16 # | store <4 x i32> %c.coerce, ptr %c, align 16 # | %c2 = load <8 x half>, ptr %c, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b1, ptr %b.addr, align 16 # | store <8 x half> %c2, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %1, ptr %coerce, align 16 # | %3 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %2, ptr %coerce3, align 16 # | %4 = load <4 x i32>, ptr %coerce3, align 16 # | store <4 x i32> %3, ptr %__p1.i, align 16 # | %__p11.i = load <8 x half>, ptr %__p1.i, align 16 # | store <4 x i32> %4, ptr %__p2.i, align 16 # | %__p22.i = load <8 x half>, ptr %__p2.i, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16 # | store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %7 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7) # | store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %9, ptr %retval.i, align 16 # | %10 = load <4 x i32>, ptr %retval.i, align 16 # | store <4 x i32> %10, ptr %coerce4, align 16 # | %11 = load <8 x half>, ptr %coerce4, align 16 # | store <8 x half> %11, ptr %retval, align 16 # | %12 = load <4 x i32>, ptr %retval, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %a = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | store <2 x i32> %a.coerce, ptr %a, align 8 # | %a1 = load <4 x half>, ptr %a, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b2 = load <4 x half>, ptr %b, align 8 # | store <4 x half> %a1, ptr %a.addr, align 8 # | store <4 x half> %b2, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %coerce, align 8 # | %2 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %1, ptr %coerce3, align 8 # | %3 = load <2 x i32>, ptr %coerce3, align 8 # | call void @llvm.experimental.noalias.scope.decl(metadata !3) # | store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3 # | %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3 # | store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3 # | %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3 # | store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3 # | store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3 # | %6 = bitcast <8 x i8> %4 to <4 x i16> # | %7 = bitcast <8 x i8> %5 to <4 x i16> # | %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3 # | %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %a = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | store <4 x i32> %a.coerce, ptr %a, align 16 # | %a1 = load <8 x half>, ptr %a, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b2 = load <8 x half>, ptr %b, align 16 # | store <8 x half> %a1, ptr %a.addr, align 16 # | store <8 x half> %b2, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %coerce, align 16 # | %2 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %1, ptr %coerce3, align 16 # | %3 = load <4 x i32>, ptr %coerce3, align 16 # | call void @llvm.experimental.noalias.scope.decl(metadata !6) # | store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6 # | %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6 # | store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6 # | %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6 # | store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6 # | store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6 # | %6 = bitcast <16 x i8> %4 to <8 x i16> # | %7 = bitcast <16 x i8> %5 to <8 x i16> # | %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6 # | %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef # | ... # `---data was truncated (10240/35874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005578258eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578258ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578258ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1aeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1aeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1aeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1aeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557825884bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557825884a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578258698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557825518e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557825518b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1aeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1aeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1aeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557825518a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (907 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056405ad14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056405ad11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056405ad1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e29049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e290a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e29049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e29031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056405acaabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056405acaaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056405ac8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056405a93ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056405a93eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e29032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e290330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e290330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056405a93ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/orn.c (910 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.orn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055faf0374eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faf0371e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faf037562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65e8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65e84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65e8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65e8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faf030abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faf030aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faf02ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055faeff9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055faeff9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65e8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65e84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65e84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faeff9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (911 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055697bad8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055697bad5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055697bad962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0921849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0921849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0921831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055697ba6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055697ba6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055697ba538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055697b702e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055697b702b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0921832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09218330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055697b702a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (912 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b0ff66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b0ff63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b0ff6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6444449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64444a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6444449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6444431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b0fefcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b0fefca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b0fee18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b0fb90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b0fb90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6444432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64444330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64444330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b0fb90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (913 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055626ef1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055626ef1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055626ef1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0f5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0f5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0f5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0f5c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055626eeb3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055626eeb3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055626ee988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055626eb47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055626eb47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0f5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0f5c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0f5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055626eb47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c65d74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c65d71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c65d7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00f7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c65d0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c65d0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c65cef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c6599ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c6599eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f00f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00f7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c6599ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (915 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2f64( zeroi # | ... # `---data was truncated (10240/32102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005645ae889eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645ae886e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645ae88a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fd1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fd138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fd1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fd131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645ae81fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005645ae81fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005645ae8048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645ae4b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645ae4b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fd131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fd131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fd131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645ae4b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (916 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a3d9caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a3d9c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a3d9cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc33c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc33c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc33c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc33c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a3d960bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a3d960a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a3d9458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a3d5f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a3d5f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc33c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc33c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc33c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a3d5f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfa815eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfa815be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfa815f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6eb7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6eb798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6eb7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6eb791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfa80f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfa80f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfa80d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfa7d88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfa7d88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6eb791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6eb791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6eb791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfa7d88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ab28cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ab28c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ab28cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe085649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe085649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe085631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ab2862bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ab2862a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ab28478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ab24f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ab24f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe085632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0856330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ab24f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561663d1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561663d18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561663d1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e6da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e6daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e6da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e6da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561663cb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561663cb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561663c968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561663945e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561663945b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e6da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e6da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e6da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561663945a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (920 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (921 of 27910) ******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c" # | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128" # | target triple = "i386-apple-darwin10" # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke_copy_to_stack() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 { # | entry: # | %that.addr = alloca ptr, align 4 # | %methodIndex.addr = alloca i32, align 4 # | %paramCount.addr = alloca i32, align 4 # | %params.addr = alloca ptr, align 4 # | store ptr %that, ptr %that.addr, align 4 # | store i32 %methodIndex, ptr %methodIndex.addr, align 4 # | store i32 %paramCount, ptr %paramCount.addr, align 4 # | store ptr %params, ptr %params.addr, align 4 # | call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2 # | ret void # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" } # | attributes #1 = { nounwind } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"NumRegisterParameters", i32 0} # | !1 = !{!"clang version 24.0.0"} # | !2 = !{i64 1623} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # | #0 0x000055afb30b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afb30b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afb30b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffad2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffad2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffad2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffad2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afb304cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afb304ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afb30318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afb2ce0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afb2ce0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffad2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffad2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffad2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afb2ce0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (922 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d53500eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d53500be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d53500f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe888a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe888aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe888a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe888a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d534fa4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d534fa4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d534f898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d534c38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d534c38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe888a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe888a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe888a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d534c38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (923 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, # | ... # `---data was truncated (10240/28354) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c6f687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c6f684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c6f68862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71a9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71a9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71a9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71a9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c6f61dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c6f61da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c6f6028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c6f2b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c6f2b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71a9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71a9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71a9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c6f2b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614c6c27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614c6c24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614c6c2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b4da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b4daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b4da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b4da31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614c6bbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614c6bbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614c6ba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614c6851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614c6851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b4da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b4da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b4da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614c6851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055784ce17eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055784ce14e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055784ce1862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a69849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a69849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a69831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055784cdadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055784cdada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055784cd928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055784ca41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055784ca41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a69832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a698330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055784ca41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (927 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/28559) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621271b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621271b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621271b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ccad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ccad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ccad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ccad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562127149bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562127149a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056212712e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562126ddde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562126dddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ccad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ccad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ccad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562126ddda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055810527eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055810527be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055810527f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7014705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f701475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7014705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70146ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558105214bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558105214a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581051f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558104ea8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558104ea8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70146eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70146ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70146ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558104ea8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (929 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | # | ... # `---data was truncated (10240/11488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560482e6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560482e67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560482e6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8fd505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8fd55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8fd505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8fd4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560482e00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560482e00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560482de58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560482a94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560482a94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8fd4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8fd4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8fd4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560482a94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (930 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d31142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d3113fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d3114362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42c1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42c1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42c1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42c1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d310d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d310d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d310bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d30d6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d30d6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42c1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42c1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42c1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d30d6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (931 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # | #0 0x0000555605e8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555605e8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555605e8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f410f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f410f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f410f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f410f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555605e23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555605e23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555605e088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555605ab7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555605ab7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f410f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f410f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f410f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555605ab7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (933 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, # | ... # `---data was truncated (10240/159327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f17bbd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f17bbcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f17bbd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b3301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b330725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b3301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b33003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f17bb68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f17bb68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f17bb4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f17b7fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f17b7fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b33004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b330050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b330050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f17b7fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a434a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a434a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a434a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff052b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff052b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff052b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff052b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a4343ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a4343ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a434238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a430d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a430d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff052b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff052b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff052b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a430d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector. # | ... # `---data was truncated (10240/78690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fb0272eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fb026fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fb027362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc0a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc0a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc0a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc0a631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fb0208bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fb0208a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fb01ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fafe9ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fafe9cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc0a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc0a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc0a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fafe9ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056152d77aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056152d777e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056152d77b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f3db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f3db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f3db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f3db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056152d710bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056152d710a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056152d6f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056152d3a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056152d3a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f3db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f3db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f3db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056152d3a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (937 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue # | ... # `---data was truncated (10240/21007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561753058eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561753055e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056175305962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08d731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561752feebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561752feea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561752fd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561752c82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561752c82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08d731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561752c82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (938 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd5b81deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd5b81ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd5b81e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7d1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7d155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7d1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7d14ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd5b7b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd5b7b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd5b7988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd5b447e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd5b447b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7d14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7d14ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7d14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd5b447a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (939 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | # | ... # `---data was truncated (10240/211223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a30e08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a30e05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a30e0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c6af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c6af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c6af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c6af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a30d9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a30d9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a30d838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a30a32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a30a32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c6af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c6af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c6af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a30a32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (940 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %add.i = fadd <4 x float> %2, %3 # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %sub.i = fsub <2 x float> %2, %3 # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <4 x float> %2, %3 # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <2 x double> %2, %3 # | store <2 x double> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <4 x float> %2, %3 # | store <4 x float> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <2 x double> %2, %3 # | store <2 x double> %mul.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | %v3.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | store <2 x float> %v3, ptr %v3.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | %2 = load <2 x float>, ptr %v3.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x float>, ptr %__p2.addr.i, align 8 # | %mul.i = fmul <2 x float> %4, %5 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %6 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | %v3.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | store <4 x float> %v3, ptr %v3.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | %2 = load <4 x float>, ptr %v3.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load <4 x float>, ptr %__p2.addr.i, align 16 # | %mul.i = fmul <4 x float> %4, %5 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; F # | ... # `---data was truncated (10240/91378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055a352c65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a352c62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a352c6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff74c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff74c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff74c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff74c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a352bfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a352bfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a352be08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a35288fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a35288fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff74c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff74c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff74c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a35288fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (941 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056033a7efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056033a7ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056033a7f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe125b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe125b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe125b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe125b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056033a785bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056033a785a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056033a76a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056033a419e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056033a419b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe125b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe125b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe125b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056033a419a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (942 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8f16.nxv4f16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16f16.nxv4f16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16f16.nxv4f16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16f16.nxv4f16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32f16.nxv4f16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32f16.nxv4f16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32f16.nxv4f16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32f16.nxv4f16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32f16.nxv4f16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32f16.nxv4f16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32f16.nxv4f16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16f16.nxv8f16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32f16.nxv8f16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32f16.nxv8f16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32f16.nxv8f16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m4_f16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32f16.nxv16f16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f32m1_f32m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 4 # | %v1.addr = alloca , align 4 # | store %v0, ptr %v0.addr, align 4 # | store %v1, ptr %v1.addr, align 4 # | %0 = load , ptr %v0.addr, align 4 # | %1 = load , ptr %v1.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( poison, %0, i64 0) # | %3 = call @llvm. # | ... # `---data was truncated (10240/593252) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056295591feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056295591ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056295592062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f00d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f00d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f00d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f00d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629558b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629558b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056295589a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562955549e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562955549b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f00d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f00d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f00d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562955549a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcabc0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bcabc08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bcabc0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81af049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81af0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81af049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81af031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcabba1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bcabba1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bcabb868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bcab835e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bcab835b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81af032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81af0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81af0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcab835a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (944 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555811deaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555811de7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555811deb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9ef849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9ef8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9ef849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9ef831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555811d80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555811d80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555811d658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555811a14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555811a14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9ef832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9ef8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9ef8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555811a14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603816f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603816f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603816fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d63849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d638a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d63849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d63831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056038168fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056038168fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603816748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560381323e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560381323b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d63832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d638330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d638330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560381323a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (949 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055989f9a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055989f9a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055989f9aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2d7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2d718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2d7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2d711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055989f93fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055989f93fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055989f9248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055989f5d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055989f5d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2d711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2d711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2d711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055989f5d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (950 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwi # | ... # `---data was truncated (10240/235604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558842791eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055884278ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055884279262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4761b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4761b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4761b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4761b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558842727bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558842727a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055884270c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588423bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588423bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4761b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4761b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4761b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588423bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (951 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d431e60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d431e5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d431e6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6cda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6cdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6cda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6cda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d431df6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d431df6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d431ddb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d431a8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d431a8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6cda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6cda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6cda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d431a8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (952 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b7583feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b7583ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b7584062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa534b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa534b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa534b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa534aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b757d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b757d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b757ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b75469e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b75469b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa534aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa534aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa534aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b75469a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c14392eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c1438fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c1439362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f132681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13268725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f132681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1326803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c14328bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c14328a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c1430d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c13fbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c13fbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1326804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13268050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13268050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c13fbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f05af6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f05af67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f05af6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5179649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51796a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5179649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5179631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f05af00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f05af00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f05aee58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f05ab94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f05ab94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5179632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51796330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51796330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f05ab94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (955 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <2 x float>, align 8 # | store <2 x float> %x, ptr %x.addr, align 8 # | %0 = load <2 x float>, ptr %x.addr, align 8 # | %1 = bitcast <2 x float> %0 to <8 x i8> # | ret <8 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <8 x i8> %0 to <2 x float> # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <4 x float>, align 16 # | store <4 x float> %x, ptr %x.addr, align 16 # | %0 = load <4 x float>, ptr %x.addr, align 16 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 { # | entry: # | %x.addr = alloca i128, align 16 # | store i128 %x, ptr %x.addr, align 16 # | %0 = load i128, ptr %x.addr, align 16 # | %1 = bitcast i128 %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to i128 # | ret i128 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x000055828740beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558287408e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055828740c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7131b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7131b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7131b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7131b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582873a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582873a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582873868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558287035e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558287035b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7131b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7131b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7131b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558287035a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (956 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/63169) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a107345eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a107342e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a10734662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff14449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff144a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff14449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff14431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1072dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1072dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1072c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a106f6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a106f6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff14432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff144330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff144330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a106f6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (957 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load # | ... # `---data was truncated (10240/31171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005644608deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644608dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644608df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aa3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aa398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aa3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aa391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564460874bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564460874a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644608598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564460508e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564460508b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6aa391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aa391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aa391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564460508a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (958 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (959 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr % # | ... # `---data was truncated (10240/67150) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b539fc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b539fc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b539fca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b27933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b2798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b27933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b2791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b539f5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b539f5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b539f448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b539bf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b539bf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b2791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b2791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b2791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b539bf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be3078ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be30789e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be3078d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3187733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f318778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3187733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f318771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be30722bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be30722a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be307078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be303b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be303b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f318771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f318771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f318771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be303b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (963 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_0( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_1( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c8fd10beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8fd108e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8fd10c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb18fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb18fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb18fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb18fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8fd0a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8fd0a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8fd0868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8fcd35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8fcd35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb18fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb18fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb18fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8fcd35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/112825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccfd69eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ccfd69be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ccfd69f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb155249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1552a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb155249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb155231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccfd634bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ccfd634a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ccfd6198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ccfd2c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ccfd2c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb155232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1552330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1552330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccfd2c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (965 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055956b4b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055956b4b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055956b4ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f438f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f438f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f438f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f438f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055956b44fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055956b44fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055956b4348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055956b0e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055956b0e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f438f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f438f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f438f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055956b0e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dcd15feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564dcd15ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564dcd16062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d41449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d414a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d41449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d41431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dcd0f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dcd0f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dcd0da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564dccd89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564dccd89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d41432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d414330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d414330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dccd89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d236b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d236b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d236b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f639141bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63914725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f639141ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6391403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d2364bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d2364ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d236308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d232dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d232dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6391404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63914050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63914050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d232dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset # | ... # `---data was truncated (10240/287213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ab2c4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ab2c4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ab2c4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff86c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff86c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff86c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff86c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ab2be3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ab2be3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ab2bc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ab2877e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ab2877b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff86c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff86c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff86c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ab2877a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/70971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561959114eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561959111e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056195911562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e7a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e7a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e7a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e7a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619590aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619590aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056195908f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561958d3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561958d3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e7a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e7a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e7a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561958d3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (971 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558e947e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e947e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e947e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1865049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18650a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1865049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1865031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e9477ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e9477ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e947638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e94412e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e94412b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1865032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18650330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18650330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e94412a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (972 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563de787eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563de784e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563de78862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff941e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff941ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff941e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff941e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563de71dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563de71da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563de7028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563de3b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563de3b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff941e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff941e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff941e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563de3b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b23378eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b23375e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b2337962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5051533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f505158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5051533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f505151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b2330ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b2330ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b232f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b22fa2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b22fa2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f505151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f505151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f505151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b22fa2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (974 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005563e7f44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563e7f41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563e7f4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9ecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9ecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9ecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9ecc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563e7edabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563e7edaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563e7ebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563e7b6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563e7b6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9ecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9ecc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9ecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563e7b6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560867522eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056086751fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056086752362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6561905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f656195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6561905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65618ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608674b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608674b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056086749d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056086714ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056086714cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65618eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65618ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65618ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056086714ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (976 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b2c56feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b2c56ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b2c57062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba6d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba6d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba6d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba6d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b2c505bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b2c505a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b2c4ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b2c199e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b2c199b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba6d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba6d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba6d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b2c199a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (977 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560847716eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560847713e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056084771762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d8a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d8a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d8a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d8a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608476acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608476aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608476918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560847340e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560847340b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d8a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d8a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d8a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560847340a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (979 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f4102fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4102fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4102fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b86449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b86449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b86431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f410293bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f410293a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4102788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f40ff27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f40ff27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b86432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f40ff27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056544716ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565447169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056544716d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb81b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb81b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb81b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb81aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565447102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565447102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654470e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565446d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565446d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb81aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb81aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb81aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565446d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee1e084eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee1e081e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee1e08562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0784933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f078498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0784933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f078491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee1e01abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee1e01aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee1dfff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee1dcaee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee1dcaeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f078491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f078491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f078491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee1dcaea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557073543eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557073540e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055707354462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbaed533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbaed58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbaed533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbaed51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570734d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570734d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570734be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055707316de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055707316db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbaed51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbaed51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbaed51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055707316da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (985 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acac2aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055acac2a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055acac2ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3448333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f344838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3448333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f344831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acac242bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055acac242a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055acac2278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055acabed6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055acabed6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f344831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f344831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f344831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acabed6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (986 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/68065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559197236eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559197233e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055919723762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53aba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53abaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53aba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53aba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591971ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591971cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591971b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559196e60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559196e60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f53aba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53aba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53aba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559196e60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (987 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569b672aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569b6727e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569b672b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f985d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f985d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f985d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f985d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569b66c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569b66c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569b66a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569b6354e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569b6354b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f985d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f985d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f985d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569b6354a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (988 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c04f0a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c04f09fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c04f0a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa721533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa72158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa721533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa72151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c04f038bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c04f038a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c04f01d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c04eccce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c04ecccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa72151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa72151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa72151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c04eccca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (989 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056333a8f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056333a8f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056333a8f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c3001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c300725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c3001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c30003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056333a88abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056333a88aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056333a86f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056333a51ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056333a51eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c30004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c300050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c300050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056333a51ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654b3dc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654b3dc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654b3dc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e43733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e4378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e43733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e4371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654b3d5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654b3d5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654b3d3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654b39eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654b39eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e4371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e4371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e4371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654b39eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (991 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (992 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (993 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a0e325eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a0e322e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a0e32662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac1ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac1ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac1ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac1eced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a0e2bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a0e2bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a0e2a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a0df4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a0df4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac1eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac1ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac1ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a0df4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree n # | ... # `---data was truncated (10240/15237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e9da66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e9da63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e9da6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2842933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f284298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2842933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f284291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e9d9fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e9d9fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e9d9e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e9d690e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e9d690b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f284291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f284291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f284291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e9d690a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055861a071eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055861a06ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055861a07262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4478733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f447878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4478733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f447871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055861a007bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055861a007a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558619fec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558619c9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558619c9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f447871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f447871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f447871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558619c9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (997 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556963034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556963031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055696303562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b8af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b8af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b8af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b8af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556962fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556962fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556962faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556962c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556962c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b8af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b8af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b8af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556962c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e06b1d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e06b1d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e06b1d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea16333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea1638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea16333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea1631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e06b16dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e06b16da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e06b1528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e06ae01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e06ae01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea1631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea1631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea1631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e06ae01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (1000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/136489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a046cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a046ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a046cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc66da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc66daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc66da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc66da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a046c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a046c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a046c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0468fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0468fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc66da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc66da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc66da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0468faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (1001 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (1002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562eedba7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562eedba4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562eedba862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fdc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fdc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fdc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fdc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562eedb3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562eedb3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562eedb228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562eed7d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562eed7d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fdc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fdc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fdc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562eed7d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (1003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_and_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32( %0) # | ret i32 %rdx.and # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.and.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_or_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32( %0) # | ret i32 %rdx.or # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.or.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_xor_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32( %0) # | ret i32 %rdx.xor # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.xor.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smax_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smin_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umax_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umin_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmax_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmax.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmin_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmin.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmaximum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32( %0) # | ret float %rdx.maximum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmaximum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fminimum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32( %0) # | ret float %rdx.minimum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fminimum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32_m8( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv16i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @reduce_add_i64( %a) #0 { # | entry: # | %a.addr = alloca , align 8 # | store %a, ptr %a.addr, align 8 # | %0 = load , ptr %a.addr, align 8 # | %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64( %0) # | ret i64 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vector.reduce.add.nxv1i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_mul_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32( %0) # | ret i32 %rdx.mul # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.mul.nxv2i32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000557287095eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557287092e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055728709662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52d7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52d7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52d7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52d7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055728702bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055728702ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572870108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557286cbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557286cbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52d7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52d7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52d7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557286cbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align # | ... # `---data was truncated (10240/22890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2c950ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2c9509e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2c950d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a72933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a7298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a72933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a7291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2c94a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2c94a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2c94878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2c9136e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2c9136b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a7291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a7291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a7291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2c9136a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (1005 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i) # | store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i) # | store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i) # | store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i) # | store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i) # | store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i) # | store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/162735) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fbe5682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbe567fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbe568362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81e0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81e018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81e0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81e011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbe5618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbe5618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbe55fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbe52ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbe52acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81e011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81e011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81e011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbe52aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (1006 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056372197beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563721978e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056372197c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd25049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd250a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd25049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd25031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563721911bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563721911a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637218f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637215a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637215a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd25032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd250330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd250330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637215a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (1007 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv4f32( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv2f64( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv2f64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamin_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famin.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famin.x2.nxv8f16(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (1008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (1009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv # | ... # `---data was truncated (10240/165238) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2148e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2148e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2148e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f870a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f870a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f870a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f870a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a21487abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a21487aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a21485f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a21450ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a21450eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f870a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f870a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f870a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a21450ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (1010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610114d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610114d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610114d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff73a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff73a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff73a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff73a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561011469bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561011469a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056101144e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610110fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610110fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff73a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff73a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff73a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610110fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (1011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2776d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2776d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2776d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f105e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f105e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f105e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f105e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f27766ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f27766ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2776538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f277302e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f277302b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f105e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f105e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f105e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f277302a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (1012 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562f6a6efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f6a6ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f6a6f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fc7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fc7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fc7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fc7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f6a685bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f6a685a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f6a66a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f6a319e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f6a319b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fc7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fc7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fc7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f6a319a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (1013 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cca54edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cca54eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cca54ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f319c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f319c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f319c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f319c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cca5483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cca5483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cca54688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cca5117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cca5117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f319c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f319c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f319c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cca5117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (1014 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (1015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv # | ... # `---data was truncated (10240/255166) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618f7949eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618f7946e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618f794a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cffb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cffb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cffb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cffb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618f78dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618f78dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618f78c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618f7573e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618f7573b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9cffb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cffb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cffb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618f7573a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (1016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | # | ... # `---data was truncated (10240/11938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdc8f0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bdc8f07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bdc8f0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc1a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc1a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc1a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc1a003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdc8ea0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bdc8ea0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bdc8e858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bdc8b34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bdc8b34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc1a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc1a0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc1a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdc8b34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (1017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dc0740eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dc073de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dc074162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b45449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b45449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b45431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dc06d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dc06d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dc06bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dc036ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dc036ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b45432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b454330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dc036aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (1018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/18353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056020f2f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056020f2eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056020f2f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dad733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dad78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dad733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dad71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056020f287bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056020f287a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056020f26c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056020ef1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056020ef1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dad71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dad71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dad71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056020ef1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (1019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fe5df0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fe5dede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fe5df162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1868133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f186818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1868133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f186811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fe5d86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fe5d86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fe5d6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558fe5a1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558fe5a1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f186811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f186811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f186811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fe5a1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (1020 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3b25edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a3b25eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a3b25ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1289b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1289b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1289b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1289b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3b2583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3b2583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3b25688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3b2217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3b2217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1289b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1289b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1289b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3b2217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (1021 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm. # | ... # `---data was truncated (10240/14102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b405117eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b405114e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b40511862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa098049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa098049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa098031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4050adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4050ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4050928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b404d41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b404d41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa098032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0980330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b404d41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bcafebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bcafe8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bcafec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5efb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5efb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5efb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5efb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bcaf81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bcaf81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bcaf668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bcac15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bcac15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5efb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5efb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5efb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bcac15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (1023 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.1a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %c.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | %2 = load <8 x i16>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | store <8 x i16> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %6, ptr %__ret.i, align 16 # | %7 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %c.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | %2 = load <4 x i32>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | store <4 x i32> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32> # | %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32> # | %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32> # | %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i) # | %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | %__ret_140 = alloca <4 x i16>, align 8 # | %__s0_140 = alloca <4 x i16>, align 8 # | %__s1_140 = alloca <4 x i16>, align 8 # | %__s2_140 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_140, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_140, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %2, ptr %__s2_140, align 8 # | %3 = load <4 x i16>, ptr %__s0_140, align 8 # | %4 = load <4 x i16>, ptr %__s1_140, align 8 # | %5 = load <4 x i16>, ptr %__s2_140, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_140, align 8 # | %16 = load <4 x i16>, ptr %__ret_140, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr # | ... # `---data was truncated (10240/38786) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x0000557aa6a90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557aa6a8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557aa6a9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45bf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45bf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45bf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45bf231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aa6a26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557aa6a26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557aa6a0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557aa66bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557aa66bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f45bf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45bf2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45bf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aa66baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (1024 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581d42beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581d42bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581d42bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa376933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa37698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa376933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa37691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581d4254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581d4254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581d42398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581d3ee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581d3ee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa37691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa37691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa37691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581d3ee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-misc.c (1025 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = icmp sge <8 x i8> %1, zeroinitializer # | %vcgez.i = sext <8 x i1> %2 to <8 x i8> # | store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8 # | %3 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %3, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %3 = icmp sge <4 x i16> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %3 = icmp sge <2 x i32> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x i64> # | %3 = icmp sge <1 x i64> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = icmp sge <16 x i8> %1, zeroinitializer # | %vcgez.i = sext <16 x i1> %2 to <16 x i8> # | store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16 # | %3 = load <16 x i8>, ptr %ref.tmp.i, align 16 # | store <16 x i8> %3, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x i16> # | %3 = icmp sge <8 x i16> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x i32> # | %3 = icmp sge <4 x i32> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x i64> # | %3 = icmp sge <2 x i64> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x float> # | %3 = fcmp oge <2 x float> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x double> # | %3 = fcmp oge <1 x double> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fcmp oge <4 x float> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %3 = fcmp oge <2 x double> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, ali # | ... # `---data was truncated (10240/217310) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000560973bb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560973bb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560973bb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4e1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4e1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4e1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4e1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560973b4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560973b4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560973b328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609737e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609737e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4e1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4e1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4e1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609737e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (1026 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005593ad82eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593ad82be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593ad82f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86a2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86a278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86a2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86a271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593ad7c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593ad7c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593ad7a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593ad458e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593ad458b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86a271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86a271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86a271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593ad458a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (1027 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614447d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614447cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614447d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6beac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6beac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6beac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6beac03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561444768bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561444768a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056144474d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614443fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614443fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6beac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6beac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6beac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614443fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (1028 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba6f83ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba6f839e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba6f83d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b8cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b8cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b8cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b8cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba6f7d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba6f7d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba6f7b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba6f466e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba6f466b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b8cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b8cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b8cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba6f466a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (1029 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, pt # | ... # `---data was truncated (10240/73955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ee1761eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ee175ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ee176262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6a4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6a4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6a4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6a4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ee16f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ee16f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ee16dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ee138be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ee138bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe6a4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6a4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6a4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ee138ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (1031 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llv # | ... # `---data was truncated (10240/20513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e30abbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e30ab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e30abc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f124ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f124ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124ae03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e30a51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e30a51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e30a368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e306e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e306e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f124ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124ae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e306e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (1032 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf09256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf09253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf0925762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5ee01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5ee0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5ee01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5ee003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf091ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf091eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf091d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf08e80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf08e80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5ee004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5ee0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5ee0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf08e80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (1033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (1034 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555942c3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555942c39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555942c3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ca2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ca20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ca2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ca2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555942bd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555942bd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555942bb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555942866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555942866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ca2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ca20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ca20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555942866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (1035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) # | ... # `---data was truncated (10240/68437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056347e29deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056347e29ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056347e29e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f1501bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f150725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f1501ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f15003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056347e233bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056347e233a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056347e2188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056347dec7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056347dec7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f15004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f150050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f150050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056347dec7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (1036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562776f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562776f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562776f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb435733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb43578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb435733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb43571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562776f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562776f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562776f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562776bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562776bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb43571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb43571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb43571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562776bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (1037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fac9d42eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fac9d3fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fac9d4362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23f0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23f058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23f0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23f051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fac9cd8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fac9cd8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fac9cbd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fac996ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fac996cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23f051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23f051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23f051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fac996ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (1038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op # | ... # `---data was truncated (10240/154517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b738536eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b738533e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b73853762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7d7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7d7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7d7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7d7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7384ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7384cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7384b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b738160e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b738160b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7d7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7d7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7d7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b738160a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (1039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603f6353eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603f6350e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603f635462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f2c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f2c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f2c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f2c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603f62e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603f62e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603f62ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005603f5f7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005603f5f7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f2c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f2c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f2c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603f5f7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (1040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/95445) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056033f19ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056033f199e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056033f19d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f90f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f90f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f90f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f90eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056033f132bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056033f132a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056033f1178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056033edc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056033edc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f90eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f90eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f90eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056033edc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (1041 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b0c6581eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0c657ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0c658262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd38b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd38b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd38b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd38b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0c6517bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0c6517a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0c64fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0c61abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0c61abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd38b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd38b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd38b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0c61aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (1042 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056262f646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056262f643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056262f64762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d1b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d1b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d1b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d1b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056262f5dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056262f5dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056262f5c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056262f270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056262f270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d1b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d1b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d1b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056262f270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (1043 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bd84723eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd84720e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd8472462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52f7c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52f7c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52f7c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52f7c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd846b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd846b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd8469e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd8434de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd8434db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52f7c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52f7c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52f7c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd8434da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (1044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055debb646eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055debb643e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055debb64762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f0af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f0af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f0af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f0aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055debb5dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055debb5dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055debb5c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055debb270e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055debb270b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f0aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f0aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f0aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055debb270a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (1045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608375e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608375e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608375e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bd5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bd5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bd5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bd5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056083757ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056083757ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608375638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560837212e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560837212b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0bd5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bd5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bd5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560837212a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (1046 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = ashr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = lshr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = ashr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = lshr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %shl = shl <16 x i32> %0, %1 # | store <16 x i32> %shl, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 imma # | ... # `---data was truncated (10240/51475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000559304f0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559304f0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559304f1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c3d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c3d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c3d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c3d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559304ea5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559304ea5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559304e8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559304b39e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559304b39b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c3d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c3d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c3d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559304b39a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (1047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3db2f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b3db2efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3db2f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1201933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f120198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1201933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f120191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3db288bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b3db288a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3db26d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3daf1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3daf1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f120191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f120191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f120191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3daf1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (1048 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (1049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561722501eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617224fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056172250262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e3fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e3fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e3fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e3fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561722497bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561722497a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056172247c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056172212be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056172212bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e3fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e3fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e3fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056172212ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (1050 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, , # | ... # `---data was truncated (10240/16521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd0b64feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd0b64ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd0b65062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17d121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17d12725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17d121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17d1203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd0b5e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd0b5e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd0b5ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd0b279e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd0b279b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17d1204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17d12050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17d12050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd0b279a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc95485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc95482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc9548662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42e7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42e718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42e7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42e711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc9541bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc9541ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc954008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc950afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc950afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42e711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42e711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42e711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc950afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (1052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d32846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d32843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d3284762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01c8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d327dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d327dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d327c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d32470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d32470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01c8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d32470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (1053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055befbc40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055befbc3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055befbc4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd72f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd72f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd72f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055befbbd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055befbbd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055befbbbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055befb86ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055befb86ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd72f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd72f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd72f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055befb86aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (1054 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b70ff1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b70ff17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b70ff1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92a7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92a76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92a7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92a7631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b70feb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b70feb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b70fe958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b70fb44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b70fb44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f92a7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92a76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92a76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b70fb44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (1055 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccb54b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ccb54b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ccb54b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4804d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4804d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4804d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4804d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccb544dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ccb544da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ccb54328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ccb50e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ccb50e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4804d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4804d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4804d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccb50e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (1056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i8 @subscript_int8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i8 @subscript_uint8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64( %a.coerce, i64 0) # | store <4 x double> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x double>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b273c59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b273c56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b273c5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a68733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a6878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a68733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a6871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b273befbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b273befa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b273bd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b273883e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b273883b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a6871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a6871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a6871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b273883a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (1057 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (1058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562569cabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562569ca8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562569cac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8c7d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8c7d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8c7d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8c7ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562569c41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562569c41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562569c268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625698d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625698d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8c7ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8c7cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8c7cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625698d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (1059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (1060 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (1061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f09cb11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f09cb0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f09cb1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f604e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f604e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f604e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f604e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f09caa7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f09caa7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f09ca8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f09c73be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f09c73bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f604e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f604e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f604e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f09c73ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (1062 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b1d405eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b1d402e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b1d40662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41e671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b1d39bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b1d39ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b1d3808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b1d02fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b1d02fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41e671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b1d02fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f7c297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f7c294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f7c29862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc40449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc404a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc40449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc40431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f7c22dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f7c22da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f7c2128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f7bec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f7bec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc40432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc404330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc404330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f7bec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (1064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8c6425eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d8c6422e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8c642662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f606db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f606db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f606db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f606db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8c63bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8c63bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8c63a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8c604fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8c604fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f606db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f606db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f606db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8c604fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (1065 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (1066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9be80feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9be80ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9be81062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae1e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae1e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae1e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae1e0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9be7a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9be7a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9be78a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9be439e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9be439b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae1e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae1e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae1e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9be439a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (1067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/34581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3d54fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3d54f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3d54fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe743049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7430a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe743049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe743031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d5491bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3d5491a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3d54768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3d5125e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3d5125b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe743032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7430330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7430330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d5125a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (1068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563308013eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563308010e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056330801462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8613d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8613d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8613d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8613d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563307fa9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563307fa9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563307f8e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563307c3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563307c3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8613d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8613d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8613d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563307c3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (1069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d2d188eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d2d185e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d2d18962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe799049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7990a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe799049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe799031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d2d11ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d2d11ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d2d1038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d2cdb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d2cdb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe799032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7990330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7990330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d2cdb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (1070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b78933eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b78930e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b7893462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1218849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1218849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1218831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b788c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b788c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b788ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b7855de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b7855db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1218832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12188330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b7855da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (1071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (1072 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,102 # | ... # `---data was truncated (10240/10769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4f9c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4f9c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4f9c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e35a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e35a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e35a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e35a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4f9c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4f9c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4f9bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4f98a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4f98a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e35a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e35a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e35a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4f98a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (1073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (1074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055677abd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055677abd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055677abd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80f2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80f2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80f2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80f2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055677ab6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055677ab6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055677ab538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055677a802e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055677a802b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f80f2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80f2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80f2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055677a802a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (1075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc62ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc62ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc62ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f094ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f094ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f094ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f094ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc62e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc62e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc62e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc62aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc62aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f094ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f094ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f094ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc62aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (1076 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (1077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 im # | ... # `---data was truncated (10240/78242) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583e2663eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583e2660e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583e266462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4103449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41034a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4103449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4103431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583e25f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583e25f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583e25de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583e228de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583e228db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4103432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41034330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41034330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583e228da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (1078 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | ... # `---data was truncated (10240/66298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b98880eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b9887de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b9888162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0694e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0694ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0694e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0694e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b98816bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b98816a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b987fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b984aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b984aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0694e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0694e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0694e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b984aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (1079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed0a753eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed0a750e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed0a75462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb648333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb64838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb648333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb64831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed0a6e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed0a6e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed0a6ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed0a37de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed0a37db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb64831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb64831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb64831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed0a37da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (1080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563aecf55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563aecf52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563aecf5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5e6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5e68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5e6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5e6831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563aeceebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563aeceeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563aeced08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563aecb7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563aecb7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5e6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5e68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5e68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563aecb7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm_acle.c (1081 of 27910) ******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dmb() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dsb() #0 { # | entry: # | call void @llvm.arm.dsb(i32 2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_isb() #0 { # | entry: # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pld() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pldx() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pli() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_plix() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 32 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i32, ptr %__x.addr.i, align 4 # | store i32 %4, ptr %retval.i, align 4 # | br label %__ror.exit # | # | if.end.i: ; preds = %entry # | %5 = load i32, ptr %__x.addr.i, align 4 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %shr.i = lshr i32 %5, %6 # | %7 = load i32, ptr %__x.addr.i, align 4 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 32, %8 # | %shl.i = shl i32 %7, %sub.i # | %or.i = or i32 %shr.i, %shl.i # | store i32 %or.i, ptr %retval.i, align 4 # | br label %__ror.exit # | # | __ror.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i32, ptr %retval.i, align 4 # | ret i32 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i.i = alloca i32, align 4 # | %__x.addr.i.i = alloca i32, align 4 # | %__y.addr.i.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | store i32 %2, ptr %__x.addr.i.i, align 4 # | store i32 %3, ptr %__y.addr.i.i, align 4 # | %4 = load i32, ptr %__y.addr.i.i, align 4 # | %rem.i.i = urem i32 %4, 32 # | store i32 %rem.i.i, ptr %__y.addr.i.i, align 4 # | %5 = load i32, ptr %__y.addr.i.i, align 4 # | %cmp.i.i = icmp eq i32 %5, 0 # | br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i # | # | if.then.i.i: ; preds = %entry # | %6 = load i32, ptr %__x.addr.i.i, align 4 # | store i32 %6, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | if.end.i.i: ; preds = %entry # | %7 = load i32, ptr %__x.addr.i.i, align 4 # | %8 = load i32, ptr %__y.addr.i.i, align 4 # | %shr.i.i = lshr i32 %7, %8 # | %9 = load i32, ptr %__x.addr.i.i, align 4 # | %10 = load i32, ptr %__y.addr.i.i, align 4 # | %sub.i.i = sub i32 32, %10 # | %shl.i.i = shl i32 %9, %sub.i.i # | %or.i.i = or i32 %shr.i.i, %shl.i.i # | store i32 %or.i.i, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | __rorl.exit: ; preds = %if.then.i.i, %if.end.i.i # | %11 = load i32, ptr %retval.i.i, align 4 # | ret i32 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i64, align 8 # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i64, align 8 # | %y.addr = alloca i32, align 4 # | store i64 %x, ptr %x.addr, align 8 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i64, ptr %x.addr, align 8 # | %1 = load i32, ptr %y.addr, align 4 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 64 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i64, ptr %__x.addr.i, align 8 # | store i64 %4, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | if.end.i: ; preds = %entry # | %5 = load i64, ptr %__x.addr.i, align 8 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %sh_prom.i = zext i32 %6 to i64 # | %shr.i = lshr i64 %5, %sh_prom.i # | %7 = load i64, ptr %__x.addr.i, align 8 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 64, %8 # | %sh_prom1.i = zext i32 %sub.i to i64 # | %shl.i = shl i64 %7, %sh_prom1.i # | %or.i = or i64 %shr.i, %shl.i # | store i64 %or.i, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | __rorll.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i64, ptr %retval.i, align 8 # | ret i64 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clz(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzl(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzll(i64 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i64, align 8 # | %t.addr = alloca i64, align 8 # | store i64 %t, ptr %t.addr, align 8 # | %0 = load i64, ptr %t.addr, align 8 # | store i64 %0, ptr %__t.addr.i, align 8 # | %1 = load i64, ptr %__t.addr.i, align 8 # | %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false) # | %3 = trunc i64 %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %cls.i = call i32 @llvm.arm.cls(i32 %1) # | ret i32 %cls.i # | } # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/86891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560108808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560108805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056010880962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f8c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f8c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f8c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f8c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056010879ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056010879ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601087838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560108432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560108432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f8c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f8c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f8c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560108432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (1082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (1083 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 2, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 3, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bbeef29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbeef26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbeef2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23b0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23b00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23b0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23b0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbeeebfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbeeebfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbeeea48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbeeb53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbeeb53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23b0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23b00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23b00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbeeb53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (1084 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, % # | ... # `---data was truncated (10240/291999) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563df2476eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563df2473e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563df247762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06a1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06a118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06a1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06a111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563df240cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563df240ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563df23f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563df20a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563df20a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06a111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06a111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06a111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563df20a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (1085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd09450eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd0944de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd0945162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa231d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa231d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa231d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa231d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd093e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd093e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd093cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd0907ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd0907ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa231d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa231d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa231d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd0907aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (1086 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e74eb5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e74eb2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e74eb662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d31d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d31d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d31d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d31d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e74e4bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e74e4ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e74e308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e74adfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e74adfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d31d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d31d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d31d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e74adfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (1087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (1088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/81507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b0ca5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b0ca5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b0ca5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3075933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f307598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3075933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f307591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b0c9f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b0c9f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b0c9d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b0c688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b0c688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f307591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f307591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f307591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b0c688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (1089 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc8247beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc82478e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc8247c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaf6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaf64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaf6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaf6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc82411bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc82411a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc823f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc820a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc820a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaf6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaf64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaf64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc820a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (1090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (1091 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b0e2f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b0e2f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b0e2f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8946649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8946649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8946631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b0e28cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b0e28ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b0e2718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b0df20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b0df20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8946632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89466330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b0df20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (1092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (1093 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd7d955eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd7d952e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd7d95662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47dfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47dfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47dfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47dfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd7d8ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd7d8eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd7d8d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd7d57fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd7d57fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47dfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47dfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47dfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd7d57fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (1094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560032d0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560032d0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560032d1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a5d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a5d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a5d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a5d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560032ca5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560032ca5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560032c8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560032939e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560032939b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a5d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a5d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a5d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560032939a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (1095 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f022ca1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f022c9ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f022ca262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ca5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ca5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ca5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ca5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f022c37bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f022c37a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f022c1c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0228cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0228cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ca5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ca5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ca5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0228cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (1096 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cac44beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cac448e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cac44c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f308d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f308d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f308d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f308d403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cac3e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cac3e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cac3c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cac075e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cac075b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f308d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f308d4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f308d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cac075a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (1097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f174559eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f174556e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f17455a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1acbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1acbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1acbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1acbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1744efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1744efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1744d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f174183e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f174183b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1acbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1acbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1acbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f174183a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1098 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %p0.addr = alloca <4 x float>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <4 x float> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <4 x float>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bf9f96eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf9f96be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf9f96f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b65333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b6538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b65333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b6531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf9f904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf9f904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf9f8e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf9f598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf9f598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b6531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b6531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b6531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf9f598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (1099 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (1100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target # | ... # `---data was truncated (10240/23439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b1cd45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b1cd42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b1cd4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78d1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78d1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78d1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78d1c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b1ccdbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b1ccdba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b1ccc08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b1c96fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b1c96fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78d1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78d1c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78d1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b1c96fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (1101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d20a05deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d20a05ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d20a05e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60ef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60ef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60ef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60ef231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d209ff3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d209ff3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d209fd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d209c87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d209c87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60ef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60ef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60ef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d209c87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (1102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (1103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af223feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055af223fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055af223ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa8d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa8d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa8d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa8d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af22394bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055af22394a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055af223798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055af22028e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055af22028b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa8d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa8d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa8d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af22028a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (1104 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0) # | r # | ... # `---data was truncated (10240/43005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595ab4e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595ab4e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595ab4ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe35b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe35b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe35b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe35b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595ab47fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595ab47fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595ab4648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595ab113e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595ab113b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe35b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe35b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe35b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595ab113a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (1105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056243020deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056243020ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056243020e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f346fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f346fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f346fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f346fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624301a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624301a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624301888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056242fe37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056242fe37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f346fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f346fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f346fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056242fe37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (1107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a891731eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a89172ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a89173262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f093a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f093a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f093a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f093a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8916c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8916c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8916ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a89135be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a89135bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f093a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f093a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f093a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a89135ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (1108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/20082) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594adaeeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594adaebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594adaef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dbf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dbf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dbf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dbf71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594ada84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594ada84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594ada698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594ad718e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594ad718b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5dbf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dbf71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dbf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594ad718a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (1109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eac9840eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eac983de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eac984162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1351e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1351e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1351e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1351e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eac97d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eac97d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eac97bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eac946ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eac946ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1351e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1351e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1351e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eac946aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (1110 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056333fc71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056333fc6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056333fc7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7733133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f773318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7733133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f773311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056333fc07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056333fc07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056333fbec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056333f89be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056333f89bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f773311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f773311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f773311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056333f89ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (1111 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_b() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_b() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005558e7c2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558e7c2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558e7c2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e93b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e93b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e93b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e93b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558e7bc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558e7bc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558e7ba88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558e7857e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558e7857b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e93b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e93b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e93b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558e7857a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (1112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (1113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0fd2d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0fd2d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0fd2d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa587849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5878a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa587849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa587831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0fd26cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0fd26ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0fd2518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0fcf00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0fcf00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa587832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5878330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5878330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0fcf00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (1114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/31876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056181f7f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056181f7f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056181f7f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86f0705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86f075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86f0705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86f06ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056181f78dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056181f78da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056181f7728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056181f421e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056181f421b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86f06eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86f06ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86f06ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056181f421a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/getset.c (1115 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <1 x i8>, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <1 x i8>, align 1 # | %tmp = alloca <1 x i8>, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load <1 x i8>, ptr %ref.tmp, align 1 # | store <1 x i8> %2, ptr %__ret, align 1 # | %3 = load <1 x i8>, ptr %__ret, align 1 # | store <1 x i8> %3, ptr %tmp, align 1 # | %4 = load <1 x i8>, ptr %tmp, align 1 # | ret <1 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_847 = alloca half, align 2 # | %__s0_847 = alloca <4 x half>, align 8 # | %ref.tmp = alloca i16, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp1 = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %tmp2 = alloca half, align 2 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_847, align 8 # | %1 = load <4 x i16>, ptr %__s0_847, align 8 # | store <4 x i16> %1, ptr %__s0, align 8 # | %2 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %2, i32 1 # | store i16 %vget_lane, ptr %ref.tmp1, align 2 # | %3 = load i16, ptr %ref.tmp1, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | store i16 %5, ptr %ref.tmp, align 2 # | %6 = load half, ptr %ref.tmp, align 2 # | store half %6, ptr %__ret_847, align 2 # | %7 = load half, ptr %__ret_847, align 2 # | store half %7, ptr %tmp2, align 2 # | %8 = load half, ptr %tmp2, align 2 # | %conv = fpext half %8 to float # | ret float %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %1, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %1, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align # | ... # `---data was truncated (10240/76998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562c69210eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c6920de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c6921162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca2b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca2b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca2b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca2b803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c691a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c691a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c6918b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c68e3ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c68e3ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca2b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca2b8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca2b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c68e3aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (1116 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x # | ... # `---data was truncated (10240/18674) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad3cf33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad3cf30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad3cf3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5032249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5032249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5032231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad3cec9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad3cec9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad3ceae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad3cb5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad3cb5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5032232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50322330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad3cb5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (1117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a7a197eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a7a194e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a7a19862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27b1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27b115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27b1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27b10ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a7a12dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a7a12da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a7a1128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a79dc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a79dc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27b10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27b10ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27b10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a79dc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (1118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056277ff2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056277ff2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056277ff2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d9fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d9fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d9fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d9fc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056277fec4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056277fec4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056277fea98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056277fb58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056277fb58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d9fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d9fc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d9fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056277fb58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (1119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7aa2e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7aa2e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7aa2e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f101e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f101e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f101e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f101e0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7aa27abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7aa27aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7aa25f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7a9f0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7a9f0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f101e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f101e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f101e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7a9f0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1120 of 27910) ******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }> # | %struct.A.base = type <{ ptr, i32 }> # | # | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8 # | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000055ea6a421eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea6a41ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea6a42262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04d1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04d115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04d1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04d10ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea6a3b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea6a3b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea6a39c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea6a04be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea6a04bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04d10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04d10ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04d10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea6a04ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (1121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db2ff5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db2ff59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db2ff5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ae01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ae0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ae01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ae003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db2fef2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db2fef2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db2fed78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db2fb86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db2fb86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3ae004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ae0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ae0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db2fb86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (1122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b841233eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b841230e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b84123462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8731333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f873138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8731333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f873131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8411c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8411c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8411ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b840e5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b840e5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f873131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f873131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f873131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b840e5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (1123 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (1124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, ali # | ... # `---data was truncated (10240/280217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643b85ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643b85fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643b860062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0cac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0cac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0cac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0cac03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643b8595bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643b8595a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643b857a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643b8229e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643b8229b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0cac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0cac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0cac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643b8229a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (1125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc4ed8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc4ed88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc4ed8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ce5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ce5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ce5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ce5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc4ed21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc4ed21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc4ed068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc4e9b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc4e9b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ce5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ce5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ce5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc4e9b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (1126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574d79f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574d79eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574d79f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbfaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbfaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbfaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbfaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574d7987bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574d7987a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574d796c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574d761be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574d761bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbfaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbfaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbfaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574d761ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (1127 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou # | ... # `---data was truncated (10240/28396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x000055d08cb06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d08cb03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d08cb0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b97b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b97b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b97b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b97b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d08ca9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d08ca9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d08ca818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d08c730e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d08c730b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b97b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b97b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b97b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d08c730a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (1128 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpb_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpb.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpb.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562d8dd6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d8dd67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d8dd6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe452533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe45258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe452533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe45251b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d8dd00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d8dd00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d8dce58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d8d994e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d8d994b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe45251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe45251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe45251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d8d994a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (1129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612b2355eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612b2352e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612b235662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7337e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7337ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7337e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7337e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612b22ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612b22eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612b22d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612b1f7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612b1f7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7337e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7337e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7337e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612b1f7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (1130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b56aefaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b56aef7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b56aefb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9e5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9e5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9e5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9e5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b56ae90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b56ae90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b56ae758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b56ab24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b56ab24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9e5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9e5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9e5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b56ab24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (1131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f326927eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f326924e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f32692862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadf9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadf9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadf9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadf9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3268bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3268bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3268a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f326551e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f326551b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadf9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadf9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadf9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f326551a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (1132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c60f9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c60f99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c60f9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa37e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa37e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa37e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa37e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c60f32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c60f32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c60f178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c60bc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c60bc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa37e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa37e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa37e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c60bc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (1133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cf6841eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cf683ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cf684262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c0f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c0f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c0f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c0f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cf67d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cf67d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cf67bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cf646be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cf646bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c0f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c0f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c0f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cf646ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (1134 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560535d51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560535d4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560535d5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f78333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f7838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f78333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f7831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560535ce7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560535ce7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560535ccc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056053597be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056053597bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f7831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f7831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f7831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056053597ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (1135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (1136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/110070) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ea33f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ea33f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ea33f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7a2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7a2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7a2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7a2a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ea338dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ea338da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ea33728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ea3021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ea3021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7a2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7a2a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7a2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ea3021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (1137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df04aeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df04ae7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df04aeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5cd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5cd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5cd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5cd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df04a80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df04a80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df04a658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df04714e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df04714b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5cd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5cd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5cd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df04714a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (1138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bfd391eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bfd38ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bfd39262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff755c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff755ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff755c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff755c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bfd327bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bfd327a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bfd30c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bfcfbbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bfcfbbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff755c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff755c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff755c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bfcfbba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (1139 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559116a2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559116a2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559116a2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36ded1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591169c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591169c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591169a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559116658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559116658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f36ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559116658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (1140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be61b84eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be61b81e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be61b8562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8549f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8549f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8549f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8549eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be61b1abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be61b1aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be61aff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be617aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be617aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8549eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8549eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8549eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be617aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (1141 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563064f93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563064f90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563064f9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51e2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51e278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51e2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51e271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563064f29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563064f29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563064f0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563064bbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563064bbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51e271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51e271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51e271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563064bbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (1142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593e7f9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593e7f98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593e7f9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf9de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf9dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf9de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf9de31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593e7f31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593e7f31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593e7f168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593e7bc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593e7bc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf9de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf9de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf9de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593e7bc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (1143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, a # | ... # `---data was truncated (10240/30276) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056089e783eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056089e780e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056089e78462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f537a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f537a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f537a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f537a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056089e719bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056089e719a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056089e6fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056089e3ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056089e3adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f537a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f537a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f537a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056089e3ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (1144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae8acc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae8acc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae8acca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0c5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0c5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0c5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0c5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae8ac5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae8ac5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae8ac448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae8a8f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae8a8f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0c5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0c5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0c5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae8a8f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (1145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b60e3c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b60e3bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b60e3c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91ad249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91ad2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91ad249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91ad231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b60e356bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b60e356a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b60e33b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b60dfeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b60dfeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91ad232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91ad2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91ad2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b60dfeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (1146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd71325eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd71322e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd7132662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f01e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f01e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f01e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f01e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd712bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd712bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd712a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd70f4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd70f4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f01e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f01e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f01e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd70f4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (1147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e62daaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e62daa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e62daab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf05c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf05ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf05c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf05c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e62da40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e62da40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e62da258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e62d6d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e62d6d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf05c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf05c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf05c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62d6d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (1148 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a46f1daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a46f1d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a46f1db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff949733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff94978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff949733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff94971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a46f170bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a46f170a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a46f1558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a46ee04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a46ee04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff94971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff94971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff94971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a46ee04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (1149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563caf4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563caf4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563caf4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2a4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2a40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2a4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2a4031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563caf46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563caf46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563caf4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563caf102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563caf102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2a4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2a40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2a40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563caf102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (1150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (1151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv16i8 # | ... # `---data was truncated (10240/215036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650c21fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005650c21f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005650c21fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd686c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd686ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd686c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd686c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650c2191bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005650c2191a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650c21768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005650c1e25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005650c1e25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd686c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd686c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd686c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650c1e25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (1152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , a # | ... # `---data was truncated (10240/98437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558518832eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055851882fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055851883362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ded33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ded8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ded33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ded1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585187c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585187c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585187ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055851845ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055851845cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3ded1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ded1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ded1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055851845ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (1153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (1154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055788d1cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055788d1c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055788d1cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2ee649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2ee6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2ee649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2ee631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055788d162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055788d162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055788d1478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055788cdf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055788cdf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd2ee632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2ee6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2ee6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055788cdf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (1155 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdce242eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdce23fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdce24362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4e9831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdce1d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdce1d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdce1bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdcde6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdcde6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4e98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdcde6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (1156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc05f2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc05f2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc05f2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f254af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f254af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f254af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f254af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc05ec4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc05ec4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc05ea98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc05b58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc05b58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f254af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f254af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f254af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc05b58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (1157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkx1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055602e201eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055602e1fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055602e20262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd93cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd93cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd93cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd93cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055602e197bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055602e197a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055602e17c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055602de2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055602de2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd93cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd93cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd93cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055602de2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (1158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store # | ... # `---data was truncated (10240/79497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056381e4fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056381e4f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056381e4fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feafcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feafcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feafcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feafcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056381e492bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056381e492a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056381e4778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056381e126e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056381e126b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feafcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feafcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feafcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056381e126a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (1159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9f8ca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9f8ca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9f8ca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ca8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ca858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ca8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ca851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9f8c3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9f8c3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9f8c208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9f88cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9f88cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ca851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ca851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ca851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9f88cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (1160 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dc09c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564dc09c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564dc09c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5d801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5d80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5d801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5d8003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dc095abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dc095aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dc093f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564dc05eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564dc05eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb5d8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5d80050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5d80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dc05eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (1161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | } # | # | ; Fun # | ... # `---data was truncated (10240/34633) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572ce749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572ce746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572ce74a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff453733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff45378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff453733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff45371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572ce6dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572ce6dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572ce6c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572ce373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572ce373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff45371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff45371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff45371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572ce373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (1162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558da2daceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558da2da9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558da2dad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7ce133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7ce18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7ce133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7ce11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558da2d42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558da2d42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558da2d278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558da29d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558da29d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7ce11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7ce11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7ce11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558da29d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (1163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/100960) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056148b0b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056148b0b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056148b0ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7660105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f766015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7660105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76600ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056148b04fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056148b04fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056148b0348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056148ace3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056148ace3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76600eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76600ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76600ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056148ace3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (1164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7d6d87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7d6d84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7d6d8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd23c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd23c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd23c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd23c803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7d6d1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7d6d1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7d6d028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7d69b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7d69b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd23c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd23c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd23c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7d69b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (1165 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %b # | ... # `---data was truncated (10240/22231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fa8118beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa81188e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa8118c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1698449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16984a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1698449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1698431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa81121bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa81121a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa811068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa80db5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa80db5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1698432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16984330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16984330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa80db5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (1166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b02247eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564b02244e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564b0224862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3e8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3e84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3e8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3e8431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b021ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564b021dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564b021c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564b01e71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564b01e71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3e8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3e84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3e84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b01e71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (1167 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005607366c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607366bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607366c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0e5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0e54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0e5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0e5431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560736657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560736657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056073663c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607362ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607362ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0e5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0e54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0e54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607362eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (1168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (1169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055955f02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055955f027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055955f02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16f3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16f338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16f3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16f331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055955efc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055955efc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055955efa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055955ec54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055955ec54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16f331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16f331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16f331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055955ec54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (1170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623cf4a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623cf4a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623cf4a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55b8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55b858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55b8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55b851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623cf439bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623cf439a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623cf41e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623cf0cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623cf0cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55b851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55b851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55b851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623cf0cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (1171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561dd5ed4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561dd5ed1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561dd5ed562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0598533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f059858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0598533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f059851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dd5e6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561dd5e6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561dd5e4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561dd5afee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561dd5afeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f059851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f059851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f059851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dd5afea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (1172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564881671eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056488166ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056488167262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1c0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1c078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1c0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1c071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564881607bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564881607a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648815ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056488129be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056488129bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1c071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1c071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1c071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056488129ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (1174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (1175 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d9901dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9901dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9901e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadca649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadca6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadca649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadca631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d990175bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d990175a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d99015a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d98fe09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d98fe09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fadca632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadca6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadca6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d98fe09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (1176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d2baf6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d2baf3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d2baf762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e3de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e3dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e3de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e3de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d2ba8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d2ba8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d2ba718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d2b720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d2b720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e3de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e3de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e3de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d2b720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (1177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b90469eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b90466e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b9046a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a73e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a73ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a73e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a73e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b903ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b903ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b903e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b90093e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b90093b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a73e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a73e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a73e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b90093a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (1178 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf17c37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf17c34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf17c3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c1a81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c1a8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c1a81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c1a803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf17bcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf17bcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf17bb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf17861e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf17861b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c1a804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c1a8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c1a8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf17861a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (1179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/72143) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a40e0e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a40e0e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a40e0e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17db133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17db18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17db133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17db11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a40e07abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a40e07aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a40e05f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a40dd0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a40dd0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17db11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17db11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17db11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a40dd0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (1181 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i) # | store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i) # | store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i) # | store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i) # | store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i) # | store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i) # | store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i) # | store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i) # | store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vrndns_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vrndn.i = call float @llvm.roundeven.f32(float %1) # | store float %vrndn.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i) # | store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndm.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i) # | store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i) # | store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a # | ... # `---data was truncated (10240/29785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563d94d16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d94d13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d94d1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aae533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aae58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aae533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aae51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d94cacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d94caca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d94c918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d94940e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d94940b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0aae51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aae51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aae51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d94940a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (1182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589910adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589910aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589910ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4add249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4add2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4add249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4add231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558991043bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558991043a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589910288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558990cd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558990cd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4add232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4add2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4add2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558990cd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (1183 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %5 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %5, ptr %__ret, align 8 # | %6 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %6, ptr %tmp, align 8 # | %7 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3 # | %5 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4 # | %6 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5 # | %7 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6 # | %8 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %9 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_39 = alloca <4 x half>, align 8 # | %__s0_39 = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_39, align 8 # | %1 = load <4 x half>, ptr %__s0_39, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_39, align 8 # | %7 = load <4 x half>, ptr %__ret_39, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_20 = alloca <8 x half>, align 16 # | %__s0_20 = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_20, align 8 # | %1 = load <4 x half>, ptr %__s0_20, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_20, align 16 # | %7 = load <8 x half>, ptr %__ret_20, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_432 = alloca <4 x half>, align 8 # | %__s0_432 = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_432, align 16 # | %1 = load <8 x half>, ptr %__s0_432, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_432, align 8 # | %7 = load <4 x half>, ptr %__ret_432, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_408 = alloca <8 x half>, align 16 # | %__s0_408 = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_408, align 16 # | %1 = load <8 x half>, ptr %__s0_408, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_408, align 16 # | %7 = load <8 x half>, ptr %__ret_408, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <4 x half>, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <4 x half> %vec, ptr %vec.addr, align 8 # | %0 = load <4 x half>, ptr %vec.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x half> %1, i32 3 # | store half %vget_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <8 x half>, align 16 # | %__ret = alloca half, align 2 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <8 x half> %vec, ptr %vec.addr, align 16 # | %0 = load <8 x half>, ptr %vec.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x half> %1, i32 7 # | store half %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-s # | ... # `---data was truncated (10240/10414) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ab83b4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab83b4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab83b4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c86f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c86f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c86f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c86f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab83ae4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab83ae4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab83ac98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab83778e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab83778b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c86f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c86f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c86f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab83778a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (1184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560495808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560495805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056049580962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27f7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27f7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27f7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27f7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056049579ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056049579ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604957838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560495432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560495432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27f7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27f7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27f7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560495432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (1185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/69542) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee746faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee746f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee746fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c7281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c728725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c7281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c72803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee74690bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee74690a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee746758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee74324e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee74324b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c72804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c728050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c728050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee74324a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (1187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/12431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606aff80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005606aff7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005606aff8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0966533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f096658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0966533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f096651b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606aff16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005606aff16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606afefb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606afbaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606afbaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f096651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f096651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f096651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606afbaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649eb6eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649eb6ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649eb6ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e94b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e94b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e94b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e94b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649eb684bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649eb684a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649eb6698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649eb318e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649eb318b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e94b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e94b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e94b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649eb318a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (1189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.addr = al # | ... # `---data was truncated (10240/41670) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562af5fe7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562af5fe4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562af5fe862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3167933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f316798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3167933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f316791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562af5f7dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562af5f7da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562af5f628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562af5c11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562af5c11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f316791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f316791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f316791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562af5c11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (1190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1ac29ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1ac299e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1ac29d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febbe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febbe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febbe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febbe431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1ac232bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1ac232a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1ac2178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1abec6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1abec6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febbe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febbe4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febbe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1abec6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1191 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (1192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562495ac0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562495abde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562495ac162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb16a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb16a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb16a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb16a831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562495a56bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562495a56a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562495a3b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624956eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624956eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb16a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb16a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb16a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624956eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (1193 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %v, ptr %v.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | declare void @g(<1 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_cst(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %vecext = extractelement <16 x i8> %0, i32 3 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # | #0 0x0000556730810eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055673080de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055673081162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4985533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f498558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4985533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f498551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567307a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567307a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055673078b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055673043ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055673043ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f498551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f498551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f498551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055673043aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (1194 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055723f5ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055723f5fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055723f60062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06bef05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06bef5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06bef05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06beeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055723f595bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055723f595a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055723f57a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055723f229e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055723f229b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06beeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06beeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06beeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055723f229a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (1195 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622cd8deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622cd8dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622cd8df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd377333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd37738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd377333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd37731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622cd874bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622cd874a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622cd8598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622cd508e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622cd508b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd37731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd37731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd37731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622cd508a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (1196 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv16i8(, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8i16(, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4i32(, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f16( %op1, half noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8f16( %0, half %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8f16(, half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f32( %op1, float noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4f32( %0, float %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4f32(, float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f64( %op1, double noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load double, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2f64( %0, double %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2f64(, double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_bf16( %op1, bfloat noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8bf16( %0, bfloat %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8bf16(, bfloat) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055729ba32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055729ba2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055729ba3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d31333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d3138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d31333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d3131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055729b9c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055729b9c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055729b9ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055729b65ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055729b65cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d3131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d3131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d3131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055729b65ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (1197 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <4 x half>, align 8 # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <8 x i8> %4 to <4 x half> # | %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6) # | store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <16 x i8> %4 to <8 x half> # | %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %9 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %9, ptr %__ret, align 8 # | %10 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %10, ptr %tmp, align 8 # | %11 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <16 x i8>, align 16 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | store <16 x i8> %2, ptr %__s2, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <16 x i8>, ptr %__s2, align 16 # | %7 = load i64, ptr %__s4, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %8 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %8, ptr %__ret, align 8 # | %9 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %9, ptr %tmp, align 8 # | %10 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <16 x i8>, ptr %__s0, align 16 # | %5 = load <16 x i8>, ptr %__s1, align 16 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <16 x i8> %4 to <8 x half> # | %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3) # | store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16 # | %9 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, < # | ... # `---data was truncated (10240/24508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000055619bbfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055619bbfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055619bbfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc79c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc79ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc79c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc79c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055619bb93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055619bb93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055619bb788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055619b827e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055619b827b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc79c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc79c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc79c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055619b827a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (1198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | s # | ... # `---data was truncated (10240/280209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604d0e76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005604d0e73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005604d0e7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dae333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dae38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dae333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dae31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604d0e0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604d0e0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604d0df18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604d0aa0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604d0aa0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dae31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dae31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dae31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604d0aa0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (1199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d63895ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d638959e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d63895d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa40ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa40eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa40ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa40ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6388f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6388f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6388d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d638586e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d638586b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa40ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa40ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa40ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d638586a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (1200 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (1201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ac78edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ac78eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ac78ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb05b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb05b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb05b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb05b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ac7883bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ac7883a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ac78688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ac7517e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ac7517b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb05b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb05b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb05b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ac7517a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (1202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613bd95deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613bd95ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613bd95e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb3f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb3f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb3f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb3f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613bd8f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613bd8f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613bd8d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613bd587e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613bd587b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb3f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb3f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb3f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613bd587a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (1203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7778b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7778ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7778b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf8d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf8d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf8d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf8d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c777846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c777846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c77782b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7774dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7774dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf8d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf8d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf8d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7774daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (1204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649d0917eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649d0914e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649d091862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a64905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a6495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a64905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a648ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649d08adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649d08ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649d08928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649d0541e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649d0541b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a648eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a648ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a648ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649d0541a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1205 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (1206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, # | ... # `---data was truncated (10240/26468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631c2e30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631c2e2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631c2e3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1aa0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1aa0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1aa0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1aa0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631c2dc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631c2dc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631c2dab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631c2a5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631c2a5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1aa0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1aa0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1aa0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631c2a5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (1207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = loa # | ... # `---data was truncated (10240/33443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c25c364eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c25c361e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c25c36562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3508849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3508849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3508831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c25c2fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c25c2faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c25c2df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c25bf8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c25bf8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3508832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35088330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c25bf8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (1208 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b3a214eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b3a211e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b3a21562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc599e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc599ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc599e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc599e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b3a1aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b3a1aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b3a18f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b39e3ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b39e3eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc599e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc599e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc599e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b39e3ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (1209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b2a0e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b2a0dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b2a0e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa729933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa72998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa729933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa72991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b2a077bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b2a077a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b2a05c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b29d0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b29d0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa72991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa72991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa72991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b29d0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (1210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577cb64ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577cb649e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577cb64d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc75b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc75b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc75b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc75b231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577cb5e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577cb5e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577cb5c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577cb276e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577cb276b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc75b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc75b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc75b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577cb276a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560465d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560465d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560465d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc08c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc08c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc08c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc08c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560465cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560465cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560465cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560465969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560465969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc08c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc08c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc08c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560465969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (1212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (1213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056397f912eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056397f90fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056397f91362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc062c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc062ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc062c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc062c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056397f8a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056397f8a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056397f88d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056397f53ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056397f53cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc062c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc062c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc062c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056397f53ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (1214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d2f4d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d2f4d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d2f4d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fd0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fd08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fd0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fd0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d2f46ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d2f46ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d2f4538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d2f102e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d2f102b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1fd0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fd08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fd08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d2f102a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (1215 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632e693feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632e693ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632e694062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f04f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f04f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f04f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f04f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632e68d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632e68d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632e68ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632e6569e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632e6569b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f04f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f04f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f04f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632e6569a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (1216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b3dd4beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b3dd48e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b3dd4c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0789733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f078978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0789733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f078971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b3dce1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b3dce1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b3dcc68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b3d975e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b3d975b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f078971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f078971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f078971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b3d975a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (1217 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (1218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ec93bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ec93b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ec93bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a34d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a34d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a34d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a34d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ec9352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ec9352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ec93378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ec8fe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ec8fe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a34d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a34d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a34d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ec8fe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (1219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562784d5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562784d59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562784d5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59dff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59dff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59dff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59dff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562784cf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562784cf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562784cd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562784986e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562784986b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59dff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59dff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59dff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562784986a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (1220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056080c982eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056080c97fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056080c98362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b5421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b542725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b5421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b54203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056080c918bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056080c918a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056080c8fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056080c5ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056080c5acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b54204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b542050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b542050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056080c5aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (1221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614ca25feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614ca25ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614ca26062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bbb21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bbb2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bbb21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bbb203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614ca1f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614ca1f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614ca1da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614c9e89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614c9e89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bbb204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bbb2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bbb2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614c9e89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (1222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/31868) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648a1a7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648a1a7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648a1a7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0e9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0e918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0e9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0e911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648a1a13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648a1a13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648a19f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648a16a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648a16a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0e911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0e911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0e911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648a16a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (1224 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560aa1e7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560aa1e79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560aa1e7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab02f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab02f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab02f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab02eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560aa1e12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560aa1e12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560aa1df78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560aa1aa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560aa1aa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab02eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab02eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab02eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560aa1aa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (1225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (1227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2dd622eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2dd61fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2dd62362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1179a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1179a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1179a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1179a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2dd5b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2dd5b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2dd59d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2dd24ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2dd24cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1179a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1179a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1179a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2dd24ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (1228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a58367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a58364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a5836862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f79133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f7918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f79133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f7911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a582fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a582fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a582e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a57f91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a57f91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f7911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f7911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f7911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a57f91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (1229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d17ec0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d17ec0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d17ec0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd39681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3968725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd39681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd396803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d17eba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d17eba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d17eb888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d17e837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d17e837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd396804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3968050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3968050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d17e837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (1230 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe67efeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe67efbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe67eff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe67e94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe67e94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe67e798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe67b28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe67b28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9b7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe67b28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1231 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (1232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (1233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/235596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1db0caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1db0c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1db0cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84bae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84baea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84bae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84bae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1db060bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1db060a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1db0458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1dacf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1dacf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84bae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84bae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84bae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1dacf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (1234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f90c8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f90c8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f90c9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef6281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef628725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef6281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef62803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f90c25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f90c25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f90c0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f908b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f908b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef62804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef628050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef628050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f908b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ebcdd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ebcdd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ebcdda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6332b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6332b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6332b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6332aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ebcd6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ebcd6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ebcd548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ebca03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ebca03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6332aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6332aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6332aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ebca03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d46efdaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d46efd7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d46efdb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3786b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3786b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3786b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3786b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d46ef70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d46ef70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d46ef558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d46ec04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d46ec04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3786b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3786b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3786b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d46ec04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (1237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed3f886eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed3f883e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed3f88762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bd8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bd8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bd8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bd8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed3f81cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed3f81ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed3f8018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed3f4b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed3f4b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bd8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bd8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bd8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed3f4b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (1238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055952d018eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055952d015e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055952d01962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef4ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef4ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef4ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef4ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055952cfaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055952cfaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055952cf938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055952cc42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055952cc42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef4ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef4ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef4ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055952cc42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (1239 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb6dc76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb6dc73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb6dc7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbffff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbffff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbffff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbffff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb6dc0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb6dc0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb6dbf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb6d8a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb6d8a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbffff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbffff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbffff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb6d8a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (1240 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cnot.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cnot.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (1241 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3f990ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3f9909e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3f990d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57c9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57c978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57c9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57c971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3f98a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3f98a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3f98878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3f9536e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3f9536b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f57c971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57c971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57c971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3f9536a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (1242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8f5aafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d8f5aace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8f5ab062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9637533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f963758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9637533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f963751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8f5a45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8f5a45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8f5a2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8f56d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8f56d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f963751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f963751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f963751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8f56d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (1243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/76627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf13e4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf13e4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf13e5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c82249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c822a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c82249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c82231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf13de5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf13de5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf13dca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf13a79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf13a79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c82232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c822330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c822330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf13a79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (1244 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc67335eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc67332e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc6733662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa766049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa766049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa766031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc672cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc672cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc672b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc66f5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc66f5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa766032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7660330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc66f5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (1245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/10610) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055642c12ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055642c129e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055642c12d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f574fe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f574fe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f574fe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f574fe03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055642c0c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055642c0c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055642c0a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055642bd56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055642bd56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f574fe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f574fe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f574fe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055642bd56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (1246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (1247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf89e9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf89e99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf89e9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b86049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b86049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b86031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf89e32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf89e32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf89e178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf89ac6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf89ac6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b86032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b860330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf89ac6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (1248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a30a00ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a30a009e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a30a00d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7004333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f700438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7004333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f700431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a309fa2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a309fa2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a309f878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a309c36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a309c36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f700431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f700431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f700431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a309c36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (1249 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b6a1aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b6a1abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b6a1af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7c0c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7c0c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7c0c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7c0c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b6a144bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b6a144a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b6a1298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b69dd8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b69dd8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7c0c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7c0c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7c0c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b69dd8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0791b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0791b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0791b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff70f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff70f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff70f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff70f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b079149bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b079149a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b07912e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b078ddde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b078dddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff70f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff70f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff70f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b078ddda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (1251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b22acdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b22acae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b22ace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e2cd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e2cd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e2cd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e2cced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b22a63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b22a63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b22a488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b226f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b226f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e2cceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e2ccef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e2ccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b226f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (1252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (1253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/63140) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f7a11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f7a119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f7a11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b64c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b64ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b64c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b64c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f7a0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f7a0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f7a0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f79d46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f79d46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b64c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b64c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b64c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f79d46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (1254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055626897deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055626897ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055626897e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6a1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6a18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6a1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6a1831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556268913bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556268913a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562688f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562685a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562685a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6a1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6a18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6a18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562685a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (1255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/11969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd50c03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd50c00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd50c0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f309dd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f309dd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f309dd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f309dced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd50b99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd50b99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd50b7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd5082de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd5082db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f309dceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f309dcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f309dcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd5082da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (1256 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558847b05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558847b02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558847b0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89cf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89cf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89cf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89cf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558847a9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558847a9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558847a808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055884772fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055884772fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f89cf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89cf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89cf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055884772fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (1257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e93dcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e93dcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e93dce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbb3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbb338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbb3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbb331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e93d63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e93d63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e93d488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e939f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e939f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbb331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbb331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbb331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e939f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (1258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567c51cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005567c51cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005567c51ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38ff849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38ff8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38ff849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38ff831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567c5163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005567c5163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567c51488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567c4df7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567c4df7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38ff832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38ff8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38ff8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567c4df7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620e6829eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620e6826e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620e682a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5bff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5bff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5bff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5bff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620e67bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620e67bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620e67a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620e6453e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620e6453b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5bff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5bff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5bff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620e6453a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (1260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (1261 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (1262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, # | ... # `---data was truncated (10240/223801) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be5b359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be5b356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be5b35a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78a6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78a62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78a6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78a6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be5b2efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be5b2efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be5b2d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be5af83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be5af83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78a6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78a62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78a62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be5af83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (1263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = ashr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = lshr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = ashr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = lshr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %shl = shl <8 x i32> %0, %1 # | store <8 x i32> %shl, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %r # | ... # `---data was truncated (10240/50943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055f600649eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f600646e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f60064a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6c6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6c6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6c6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6c6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6005dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6005dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6005c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f600273e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f600273b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6c6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6c6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6c6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f600273a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (1264 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561372b8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561372b8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561372b8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1acd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1acd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1acd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1acd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561372b24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561372b24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561372b098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613727b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613727b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1acd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1acd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1acd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613727b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/205805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a02d7eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a02d7ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a02d7ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9691133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f969118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9691133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f969111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a02d784bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a02d784a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a02d7698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a02d418e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a02d418b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f969111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f969111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f969111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a02d418a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (1266 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f7af9aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7af9a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7af9ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f275da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f275daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f275da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f275da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7af942bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7af942a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7af9278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7af5d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7af5d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f275da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f275da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f275da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7af5d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1f3270eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1f326de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1f327162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4632133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4632133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f463211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1f3206bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1f3206a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1f31eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1f2e9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1f2e9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f463211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f463211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f463211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1f2e9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (1268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (1269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055601cebdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055601cebae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055601cebe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde2f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde2f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde2f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde2f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055601ce53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055601ce53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055601ce388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055601cae7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055601cae7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde2f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde2f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde2f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055601cae7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (1270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056373c648eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056373c645e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056373c64962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36b4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056373c5debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056373c5dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056373c5c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056373c272e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056373c272b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f36b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056373c272a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (1271 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592d7122eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005592d711fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005592d712362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa2ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa2ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa2ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa2ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592d70b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005592d70b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005592d709d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005592d6d4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005592d6d4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa2ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa2ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa2ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592d6d4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (1272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561137749eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561137746e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056113774a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82ba01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82ba0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82ba01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82ba003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611376dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611376dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611376c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561137373e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561137373b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82ba004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82ba0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82ba0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561137373a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (1273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d49889ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d498899e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d49889d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64bc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64bc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64bc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64bc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d498832bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d498832a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4988178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4984c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4984c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f64bc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64bc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64bc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4984c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (1274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | # | ... # `---data was truncated (10240/23255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056498d8ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056498d8fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056498d90062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3225333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f322538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3225333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f322531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056498d895bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056498d895a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056498d87a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056498d529e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056498d529b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f322531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f322531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f322531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056498d529a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (1275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, al # | ... # `---data was truncated (10240/12389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee95c32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee95c2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee95c3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ec2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ec24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ec2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ec2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee95bc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee95bc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee95bad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee9585ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee9585cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ec2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ec24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ec24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee9585ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (1276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c52f92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c52f8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c52f9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbca4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbca44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbca4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbca4431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c52f28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c52f28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c52f0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c52bbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c52bbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbca4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbca44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbca44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c52bbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (1277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e697f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e697f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e697f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f440d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f440d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f440d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f440d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e6978bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e6978ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e697708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e6941fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e6941fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f440d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f440d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f440d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e6941fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (1278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f053017eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f053014e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f05301862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc337105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc33715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc337105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3370ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f052fadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f052fada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f052f928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f052c41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f052c41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3370eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3370ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3370ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f052c41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (1279 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loca # | ... # `---data was truncated (10240/18587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558afa581eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558afa57ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558afa58262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca88849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca888a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca88849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca88831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558afa517bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558afa517a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558afa4fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558afa1abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558afa1abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca88832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca888330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca888330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558afa1aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (1280 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_571 = alloca float, align 4 # | %__s0_571 = alloca float, align 4 # | %__s1_571 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_571, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_571, align 8 # | %2 = load float, ptr %__s0_571, align 4 # | %3 = load <2 x float>, ptr %__s1_571, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_571, align 4 # | %8 = load float, ptr %__ret_571, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret_570 = alloca double, align 8 # | %__s0_570 = alloca double, align 8 # | %__s1_570 = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_570, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_570, align 8 # | %2 = load double, ptr %__s0_570, align 8 # | %3 = load <1 x double>, ptr %__s1_570, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %4, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_570, align 8 # | %8 = load double, ptr %__ret_570, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_577 = alloca float, align 4 # | %__s0_577 = alloca float, align 4 # | %__s1_577 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_577, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_577, align 16 # | %2 = load float, ptr %__s0_577, align 4 # | %3 = load <4 x float>, ptr %__s1_577, align 16 # | store <4 x float> %3, ptr %__s0, align 16 # | %4 = load <4 x float>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <4 x float> %4, i32 3 # | store float %vgetq_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_577, align 4 # | %8 = load float, ptr %__ret_577, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret_575 = alloca double, align 8 # | %__s0_575 = alloca double, align 8 # | %__s1_575 = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_575, align 8 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1_575, align 16 # | %2 = load double, ptr %__s0_575, align 8 # | %3 = load <2 x double>, ptr %__s1_575, align 16 # | store <2 x double> %3, ptr %__s0, align 16 # | %4 = load <2 x double>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <2 x double> %4, i32 1 # | store double %vgetq_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_575, align 8 # | %8 = load double, ptr %__ret_575, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca double, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <1 x double>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store double %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x double>, ptr %__p0.addr.i, align 8 # | %3 = load double, ptr %__p1.addr.i, align 8 # | %4 = bitcast <1 x double> %2 to double # | %5 = fmul double %4, %3 # | store double %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %6, ptr %__ret.i, align 8 # | %7 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_626 = alloca float, align 4 # | %__s0_626 = alloca float, align 4 # | %__s1_626 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_626, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_626, align 8 # | %2 = load float, ptr %__s0_626, align 4 # | %3 = load <2 x float>, ptr %__s1_626, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | store float %2, ptr %__p0.addr.i, align 4 # | store float %7, ptr %__p1.addr.i, align 4 # | %8 = load float, ptr %__p0.addr.i, align 4 # | %9 = load float, ptr %__p1.addr.i, align 4 # | %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9) # | store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4 # | %10 = load float, ptr %ref.tmp.i, align 4 # | store float %10, ptr %__ret.i, align 4 # | %11 = load float, ptr %__ret.i, align 4 # | store float %11, ptr %__ret_626, align 4 # | %12 = load float, ptr %__ret_626, align 4 # | store float %12, ptr %tmp1, align 4 # | %13 = load float, ptr %tmp1, align 4 # | ret float %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_636 = alloca float, align 4 # | %__s0_636 = alloca float, align 4 # | %__s1_636 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_636, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_636, align 16 # | %2 = load float, ptr %__s0_636, align 4 # | %3 = load <4 x float>, ptr %__s1_636, align 16 # | store <4 x float> %3, ptr % # | ... # `---data was truncated (10240/74804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000555fd3a77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fd3a74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fd3a7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f559e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f559e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f559e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f559e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fd3a0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fd3a0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fd39f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fd36a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fd36a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f559e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f559e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f559e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fd36a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (1281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636cfdc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636cfdc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636cfdc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a1101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a110725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a1101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a11003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636cfd5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636cfd5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636cfd428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636cf9f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636cf9f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a11004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a110050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a110050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636cf9f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (1282 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6d5719eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6d5716e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6d571a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2e4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2e4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2e4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2e4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6d56afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6d56afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6d56948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6d5343e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6d5343b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2e4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2e4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2e4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6d5343a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (1283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (1284 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556d526fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d526fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d526fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd565449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5654a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd565449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd565431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d52693bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d52693a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d526788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d52327e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d52327b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd565432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5654330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5654330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d52327a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (1285 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055fb9cb46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb9cb43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb9cb4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2f8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2f80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2f8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2f8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb9cadcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb9cadca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb9cac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb9c770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb9c770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2f8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2f80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2f80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb9c770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (1286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8c5b66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8c5b63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8c5b6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd15ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd15ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd15ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd15ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8c5afcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c8c5afca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c8c5ae18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8c5790e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8c5790b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd15ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd15ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd15ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8c5790a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (1287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e30888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e30885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e3088962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6f1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6f198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6f1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6f191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e3081ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e3081ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e308038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e304b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e304b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6f191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6f191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6f191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e304b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (1288 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640dfebdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640dfebae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640dfebe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d3d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d3d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d3d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d3d403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640dfe53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640dfe53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640dfe388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640dfae7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640dfae7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d3d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d3d4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d3d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640dfae7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (1289 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = sitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = uitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = sitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = uitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptosi <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptosi <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptoui <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptoui <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm # | ... # `---data was truncated (10240/37578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccde8ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ccde8dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ccde8de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f670a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f670a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f670a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f670a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccde873bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ccde873a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ccde8588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ccde507e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ccde507b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f670a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f670a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f670a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccde507a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (1290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565554dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565554dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565554dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef7321bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef732725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef7321ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef73203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565554d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565554d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565554d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005655549fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005655549fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef73204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef732050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef732050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655549fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (1291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a40786eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a40783e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a4078762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bf0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bf018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bf0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bf011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a4071cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a4071ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a407018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a403b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a403b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bf011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bf011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bf011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a403b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (1292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bi # | ... # `---data was truncated (10240/136481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f66795eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f66795be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f66795f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d95733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d9578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d95733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d9571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6678f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6678f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6678d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f667588e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f667588b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d9571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d9571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d9571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f667588a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (1293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621749c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621749bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621749c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7166333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f716638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7166333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f716631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562174958bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562174958a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056217493d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621745ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621745ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f716631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f716631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f716631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621745eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (1294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056375fadceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056375fad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056375fadd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc384733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc38478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc384733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc38471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056375fa72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056375fa72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056375fa578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056375f706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056375f706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc38471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc38471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc38471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056375f706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (1295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600257eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600257e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600257ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4188f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4188f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4188f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4188eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560025782bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560025782a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600257678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560025416e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560025416b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4188eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4188eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4188eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560025416a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (1296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5d555beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5d5558e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5d555c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7040d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7040d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7040d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7040d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5d54f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5d54f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5d54d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5d5185e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5d5185b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7040d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7040d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7040d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5d5185a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (1297 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ae27deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ae27dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ae27df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdadd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdadd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdadd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdadd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ae2774bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ae2774a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ae27598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ae2408e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ae2408b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbdadd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdadd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdadd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ae2408a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (1298 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (1299 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5dac1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5dac17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5dac1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3937649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3937649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3937631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5dabb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5dabb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5dab958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5da844e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5da844b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3937632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39376330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5da844a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (1300 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055756e42deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055756e42ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055756e42e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cefe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cefea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cefe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cefe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055756e3c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055756e3c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055756e3a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055756e057e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055756e057b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cefe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cefe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cefe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055756e057a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (1301 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ea7404eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ea7401e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ea740562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ca7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ca7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ca7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ca7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ea739abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ea739aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ea737f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ea702ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ea702eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ca7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ca7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ca7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ea702ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (1302 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.ad # | ... # `---data was truncated (10240/26762) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df44280eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df4427de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df4428162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fade1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fade1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fade1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fade1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df44216bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df44216a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df441fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df43eaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df43eaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fade1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fade1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fade1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df43eaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (1303 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d99544aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d995447e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d99544b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f249c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f249c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f249c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f249c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9953e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9953e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9953c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d995074e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d995074b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f249c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f249c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f249c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d995074a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1304 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555912328eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555912325e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055591232962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4693f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4693f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4693f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4693f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559122bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559122bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559122a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555911f52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555911f52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4693f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4693f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4693f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555911f52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (1305 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578923f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578923f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578923f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba4cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba4cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba4cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba4cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055789238dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055789238da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578923728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557892021e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557892021b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba4cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba4cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba4cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557892021a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (1306 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %v # | ... # `---data was truncated (10240/43948) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560df1e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560df1e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560df1e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f4df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f4df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f4df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f4df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560df1dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560df1deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560df1dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560df1a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560df1a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f4df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f4df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f4df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560df1a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (1307 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056488f3cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056488f3c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056488f3cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0fd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0fd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0fd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0fd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056488f362bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056488f362a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056488f3478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056488eff6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056488eff6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0fd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0fd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0fd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056488eff6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (1308 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639c618eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639c618be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639c618f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fc4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fc42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fc4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fc4231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639c6124bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639c6124a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639c61098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639c5db8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639c5db8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fc4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fc42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fc42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639c5db8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (1309 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a147e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a147e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a147ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e02f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e02f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e02f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e02f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a1477fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a1477fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a147648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a14413e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a14413b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e02f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e02f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e02f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a14413a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (1310 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5ba57aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5ba577e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5ba57b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d73249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d73249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d73231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5ba510bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5ba510a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5ba4f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5ba1a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5ba1a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d73232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d732330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5ba1a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (1311 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaa # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e91654eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e91651e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e9165562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa635849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6358a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa635849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa635831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e915eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e915eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e915cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e9127ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e9127eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa635832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6358330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6358330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e9127ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/poly64.c (1312 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %cmp.i = icmp eq <1 x i64> %2, %3 # | %sext.i = sext <1 x i1> %cmp.i to <1 x i64> # | store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %cmp.i = icmp eq <2 x i64> %2, %3 # | %sext.i = sext <2 x i1> %cmp.i to <2 x i64> # | store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %6 = and <1 x i64> %4, %5 # | %7 = icmp ne <1 x i64> %6, zeroinitializer # | %vtst.i = sext <1 x i1> %7 to <1 x i64> # | store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8 # | %8 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %8, ptr %__ret.i, align 8 # | %9 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %6 = and <2 x i64> %4, %5 # | %7 = icmp ne <2 x i64> %6, zeroinitializer # | %vtst.i = sext <2 x i1> %7 to <2 x i64> # | store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16 # | %8 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %8, ptr %__ret.i, align 16 # | %9 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_913 = alloca <1 x i64>, align 8 # | %__s0_913 = alloca <1 x i64>, align 8 # | %__s2_913 = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp3 = alloca <1 x i64>, align 8 # | %tmp4 = alloca <1 x i64>, align 8 # | %tmp5 = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0_913, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_913, align 8 # | %2 = load <1 x i64>, ptr %__s2_913, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <1 x i64>, ptr %__s0_913, align 8 # | store <1 x i64> %7, ptr %__s1, align 8 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <1 x i64>, ptr %__s1, align 8 # | %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0 # | store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <1 x i64>, ptr %ref.tmp3, align 8 # | store <1 x i64> %10, ptr %__ret, align 8 # | %11 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %11, ptr %tmp4, align 8 # | %12 = load <1 x i64>, ptr %tmp4, align 8 # | store <1 x i64> %12, ptr %__ret_913, align 8 # | %13 = load <1 x i64>, ptr %__ret_913, align 8 # | store <1 x i64> %13, ptr %tmp5, align 8 # | %14 = load <1 x i64>, ptr %tmp5, align 8 # | ret <1 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_909 = alloca <2 x i64>, align 16 # | %__s0_909 = alloca <2 x i64>, align 16 # | %__s2_909 = alloca <1 x i64>, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_909, align 16 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_909, align 8 # | %2 = load <1 x i64>, ptr %__s2_909, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <2 x i64>, ptr %__s0_909, align 16 # | store <2 x i64> %7, ptr %__s1, align 16 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <2 x i64>, ptr %__s1, align 16 # | %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1 # | store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <2 x i64>, ptr %ref.tmp3, align 16 # | store <2 x i64> %10, ptr %__ret, align 16 # | %11 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %11, ptr %tmp4, align 16 # | %12 = load <2 x i64>, ptr %tmp4, align 16 # | store <2 x i64> %12, ptr %__ret_909, align 16 # | %13 = load <2 x i64>, ptr %__ret_909, align 16 # | store <2 x i64> %13, ptr %tmp5, align 16 # | %14 = load <2 x i64>, ptr %tmp5, align 16 # | ret <2 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret_915 = alloca <2 x i64>, align 16 # | %__s0_915 = alloca <2 x i64>, align 16 # | %__s2_915 = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_915, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s2_915, align 16 # | %2 = load <2 x i64>, ptr %__s2_915, align 16 # | store <2 x i64> %2, ptr %__s02, align 16 # | %3 = load <2 x i64>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <2 x i64> %3, i32 1 # | store i64 %vgetq_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = # | ... # `---data was truncated (10240/22456) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056108cc3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056108cc3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056108cc3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c8051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056108cbd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056108cbd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056108cbb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056108c868e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056108c868b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c8051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056108c868a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (1313 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (1314 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/79671) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d72364eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d72361e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d7236562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f21933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f2198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f21933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f2191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d722fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d722faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d722df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d71f8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d71f8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f2191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f2191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f2191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d71f8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (1315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (1316 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | st # | ... # `---data was truncated (10240/110292) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055671f8eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055671f8ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055671f8ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc712933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc71298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc712933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc71291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055671f884bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055671f884a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055671f8698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055671f518e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055671f518b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc71291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc71291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc71291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055671f518a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (1317 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5f9c4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5f9c49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5f9c4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5f9be2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5f9be2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5f9bc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5f9876e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5f9876b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ff711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5f9876a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (1318 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i1 # | ... # `---data was truncated (10240/182173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556136c34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556136c31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556136c3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40e1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40e16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40e1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40e1631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556136bcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556136bcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556136baf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055613685ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055613685eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40e1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40e16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40e16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055613685ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (1319 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (1320 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561e19e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561e19dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561e19e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62c0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62c0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62c0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62c0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561e1976bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005561e1976a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561e195b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561e160ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561e160ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62c0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62c0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62c0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561e160aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1321 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (1322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @l # | ... # `---data was truncated (10240/62760) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649f2fc6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649f2fc3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649f2fc762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa603a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa603aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa603a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa603a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649f2f5cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649f2f5ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649f2f418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649f2bf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649f2bf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa603a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa603a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa603a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649f2bf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (1323 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d16ff5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d16ff5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d16ff5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00b0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00b015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00b0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00b00ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d16fef3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d16fef3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d16fed88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d16fb87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d16fb87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f00b00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00b00ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00b00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d16fb87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (1324 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = mul <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = mul <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = mul <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fmul <4 x float> %0, %1 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.m # | ... # `---data was truncated (10240/21288) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005612548c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612548c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612548ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98ee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98ee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98ee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98ee031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056125485fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056125485fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612548448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612544f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612544f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98ee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98ee0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98ee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612544f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (1325 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (1326 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565154aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565154aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565154af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c06c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c06ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c06c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c06c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565154a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565154a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565154a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565154719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565154719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c06c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c06c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c06c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565154719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (1327 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | # | ... # `---data was truncated (10240/25279) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5be311eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5be30ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5be31262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f632ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f632baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f632ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f632ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5be2a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a5be2a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5be28c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5bdf3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5bdf3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f632ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f632ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f632ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5bdf3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (1328 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1329 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e26e5bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e26e5bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e26e5c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8aed049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8aed0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8aed049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8aed031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e26e555bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e26e555a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e26e53a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e26e1e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e26e1e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8aed032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8aed0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8aed0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e26e1e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (1330 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/80648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab2b2f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab2b2f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab2b2f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f392ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f392ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f392ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f392ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab2b289bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab2b289a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab2b26e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab2af1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab2af1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f392ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f392ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f392ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab2af1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (1331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c39a5d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c39a5d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c39a5d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f408e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f408e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f408e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f408e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c39a56abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c39a56aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c39a54f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c39a1fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c39a1feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f408e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f408e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f408e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c39a1fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (1332 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055890ed0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055890ed07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055890ed0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb134849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1348a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb134849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb134831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055890eca0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055890eca0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055890ec858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055890e934e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055890e934b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb134832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1348330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1348330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055890e934a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (1333 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfc1b74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfc1b71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfc1b7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7921e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7921e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7921e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7921e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfc1b0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfc1b0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfc1aef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfc179ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfc179eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7921e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7921e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7921e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfc179ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (1334 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (1335 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558eff05feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558eff05ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558eff06062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41e7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41e778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41e7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41e771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558efeff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558efeff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558efefda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558efec89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558efec89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41e771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41e771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41e771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558efec89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (1336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632ccbe9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632ccbe6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632ccbea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe26f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe26f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe26f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe26f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632ccb7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632ccb7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632ccb648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632cc813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632cc813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe26f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe26f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe26f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632cc813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (1337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (1338 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb757bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb757bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb757c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f6a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f6a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f6a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f6a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb75755bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb75755a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb7573a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb753e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb753e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f6a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f6a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f6a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb753e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (1339 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed2e7eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed2e7e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed2e7eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3fd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3fd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3fd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3fd8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed2e780bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed2e780a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed2e7658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed2e414e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed2e414b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3fd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3fd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3fd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed2e414a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (1340 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (1341 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/94157) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3b6cb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3b6cb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3b6cb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbecfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbecfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbecfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbecfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3b6c4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3b6c4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3b6c338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3b68e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3b68e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbecfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbecfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbecfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3b68e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (1342 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vs # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a004345eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a004342e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a00434662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a42f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a42f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a42f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a42f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0042dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0042dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0042c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a003f6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a003f6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a42f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a42f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a42f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a003f6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (1343 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5cffcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5cffc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5cffcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f854f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f854f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f854f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f854f031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5cff60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a5cff60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5cff458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5cfbf4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5cfbf4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f854f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f854f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f854f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5cfbf4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (1344 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558408b23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558408b20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558408b2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4908b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4908b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4908b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4908b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558408ab9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558408ab9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558408a9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055840874de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055840874db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4908b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4908b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4908b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055840874da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (1345 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (1346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e413649eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e413646e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e41364a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d26431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4135dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4135dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4135c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e413273e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e413273b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e413273a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (1347 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f884c62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f884c5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f884c6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa48e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa48e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa48e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa48e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f884bf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f884bf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f884bdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f88488ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f88488cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa48e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa48e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa48e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f88488ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (1348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b86f2d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b86f2d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b86f2da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba17f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba17f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba17f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba17f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b86f26fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b86f26fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b86f2548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b86ef03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b86ef03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba17f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba17f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba17f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b86ef03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (1349 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636fd50ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005636fd509e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005636fd50d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f575e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f575e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f575e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f575e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636fd4a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636fd4a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636fd4878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005636fd136e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005636fd136b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f575e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f575e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f575e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636fd136a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (1350 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca58f37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca58f34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca58f3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb0d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb0d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb0d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb0d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca58ecdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca58ecda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca58eb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca58b61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca58b61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb0d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb0d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb0d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca58b61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (1351 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561508ae8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561508ae5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561508ae962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa32ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa32ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa32ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa32ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561508a7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561508a7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561508a638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561508712e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561508712b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa32ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa32ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa32ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561508712a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (1352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (1353 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559587732eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055958772fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055958773362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d2cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d2cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d2cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d2cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595876c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595876c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595876ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055958735ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055958735cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d2cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d2cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d2cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055958735ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (1354 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b31ecc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b31ecc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b31ecc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b10449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b104a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b10449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b10431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b31ec5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b31ec5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b31ec3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b31e8eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b31e8eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b10432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b104330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b104330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b31e8eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1355 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (1356 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 # | ... # `---data was truncated (10240/18303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632b8351eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632b834ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632b835262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40e8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632b82e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632b82e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632b82cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632b7f7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632b7f7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40e8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632b7f7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (1357 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqr # | ... # `---data was truncated (10240/28170) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566c6a62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566c6a5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566c6a6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3206705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f320675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3206705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32066ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566c69f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566c69f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566c69dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566c668ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566c668cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f32066eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32066ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32066ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566c668ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (1358 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b14fd51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b14fd4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b14fd5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ac5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ac54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ac5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ac5431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b14fce7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b14fce7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b14fccc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b14f97be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b14f97bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ac5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ac54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ac54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b14f97ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (1359 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f93c55deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f93c55ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f93c55e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa64ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa64ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa64ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa64ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f93c4f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f93c4f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f93c4d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f93c187e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f93c187b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa64ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa64ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa64ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f93c187a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (1360 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (1361 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f64.i64( poison, double %0, i64 %1) # | # | ... # `---data was truncated (10240/30849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cd71cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561cd71cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561cd71ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fdbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fdbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fdbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fdbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cd7163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561cd7163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561cd71488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561cd6df7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561cd6df7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5fdbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fdbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fdbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cd6df7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (1362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (1363 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 # | ... # `---data was truncated (10240/28361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055baad70ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055baad709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055baad70d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9cee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9ceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9cee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9cee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055baad6a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055baad6a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055baad6878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055baad336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055baad336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9cee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9cee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9cee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055baad336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (1364 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b0872beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b08728e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b0872c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f039fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f039fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f039fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f039fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b086c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b086c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b086a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b08355e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b08355b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f039fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f039fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f039fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b08355a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (1365 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca # | ... # `---data was truncated (10240/153805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4fd47eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4fd47be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4fd47f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f616c61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f616c6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f616c61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f616c603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4fd414bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4fd414a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4fd3f98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4fd0a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4fd0a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f616c604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f616c6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f616c6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4fd0a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (1366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, alig # | ... # `---data was truncated (10240/150641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055921a14eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055921a14be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055921a14f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe669449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6694a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe669449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe669431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055921a0e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055921a0e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055921a0c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559219d78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559219d78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe669432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6694330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6694330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559219d78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (1367 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b86da5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b86da5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b86da5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f501f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f501f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f501f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f501f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b86d9f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b86d9f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b86d9d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b86d688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b86d688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f501f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f501f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f501f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b86d688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (1368 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/26764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2970bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2970bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2970be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa192733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa19278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa192733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa19271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e297053bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e297053a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2970388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e296ce7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e296ce7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa19271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa19271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa19271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e296ce7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (1369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d6856feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d6856ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d6857062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb96133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb9618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb96133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb9611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d68505bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d68505a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d684ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d68199e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d68199b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb9611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb9611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb9611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d68199a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (1370 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560569848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560569845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056056984962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75a2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75a2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75a2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75a2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605697debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605697dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605697c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560569472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560569472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75a2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75a2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75a2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560569472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (1371 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556385684eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556385681e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055638568562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055638561abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055638561aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563855ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563852aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563852aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563852aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (1372 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6e5863eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6e5860e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6e586462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d8c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d8c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d8c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d8c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6e57f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6e57f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6e57de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e6e548de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e6e548db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d8c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d8c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d8c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6e548da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (1373 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f89537eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f89534e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f8953862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3847d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3847d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3847d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3847d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f894cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f894cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f894b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f89161e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f89161b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3847d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3847d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3847d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f89161a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (1374 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (1375 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/79861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c5900beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c59008e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c5900c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ba3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ba3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ba3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ba3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c58fa1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c58fa1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c58f868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c58c35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c58c35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ba3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ba3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ba3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c58c35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (1376 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 noundef # | ... # `---data was truncated (10240/29167) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5c9288eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5c9285e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5c928962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3252d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3252d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3252d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3252d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5c921ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5c921ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5c92038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5c8eb2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5c8eb2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3252d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3252d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3252d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5c8eb2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (1377 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/17403) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560da92f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560da92f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560da92f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ee2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ee2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ee2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ee2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560da9289bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560da9289a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560da926e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560da8f1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560da8f1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ee2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ee2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ee2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560da8f1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (1378 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d24dd58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d24dd55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d24dd5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9038733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f903878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9038733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f903871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d24dceebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d24dceea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d24dcd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d24d982e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d24d982b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f903871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f903871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f903871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d24d982a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (1379 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i64, i64, # | ... # `---data was truncated (10240/120460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f266f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f266f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f266f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedebb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f2668cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f2668ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f266718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f26320e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f26320b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fedebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f26320a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (1380 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1381 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl # | ... # `---data was truncated (10240/78896) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558004d5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558004d57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558004d5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7437f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7437f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7437f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7437eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558004cf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558004cf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558004cd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558004984e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558004984b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7437eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7437eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7437eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558004984a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (1382 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (1383 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b407827eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b407824e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b40782862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26e8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4077bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4077bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4077a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b407451e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b407451b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f26e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26e8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b407451a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (1384 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b88a4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b88a4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b88a5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d6ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d6ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d6ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d6ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b889e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b889e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b889ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b88679e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b88679b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d6ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d6ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d6ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b88679a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (1385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8665b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c8665aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c8665b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cb9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cb9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cb9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cb9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c866547bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c866547a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c86652c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c8661dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c8661dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cb9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cb9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cb9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8661dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/store.c (1386 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | store <4 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <2 x float> # | store <2 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | store <1 x double> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %val.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %val, ptr %val.addr, align 8 # | %0 = load <8 x i8>, ptr %val.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | store <4 x i16> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store <1 x i64> %val, ptr %val.addr, align 8 # | %0 = load <1 x i64>, ptr %val.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %ptr.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | store <1 x i64> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | store <8 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x float>, align 16 # | %__s1 = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <4 x float> # | store <4 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr # | ... # `---data was truncated (10240/446007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000558cec2aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cec2a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cec2ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16ecb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16ecb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16ecb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16ecb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cec240bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cec240a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cec2258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cebed4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cebed4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16ecb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16ecb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16ecb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cebed4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (1387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (1388 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/210435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee1f2beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ee1f2bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ee1f2bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8119049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81190a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8119049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8119031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee1f254bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ee1f254a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ee1f2398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ee1eee8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ee1eee8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8119032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81190330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81190330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee1eee8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (1389 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e3cf67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e3cf64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e3cf6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efeacf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efeacf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efeacf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efeacf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e3cefdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e3cefda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e3cee28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e3cb91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e3cb91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efeacf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efeacf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efeacf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e3cb91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (1390 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/68255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f15ac11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f15ac0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f15ac1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff07d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff07d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff07d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff07d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f15aba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f15aba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f15ab8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f15a83be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f15a83bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff07d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff07d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff07d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f15a83ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (1391 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca # | ... # `---data was truncated (10240/22898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563821267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563821264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056382126862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8b1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8b1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8b1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8b1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638211fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638211fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638211e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563820e91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563820e91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8b1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8b1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8b1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563820e91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (1392 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632a1adceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632a1ad9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632a1add62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfc8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfc878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfc8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfc871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632a1a72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632a1a72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632a1a578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632a1706e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632a1706b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfc871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfc871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfc871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632a1706a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (1393 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559537b66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559537b63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559537b6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fb6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fb64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fb6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fb6431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559537afcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559537afca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559537ae18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559537790e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559537790b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3fb6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fb64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fb64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559537790a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (1394 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.i6 # | ... # `---data was truncated (10240/18619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d746875eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d746872e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d74687662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b46b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b46b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b46b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b46b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d74680bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d74680ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7467f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d74649fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d74649fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b46b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b46b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b46b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d74649fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (1395 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4518e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4518e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4518e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3510849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35108a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3510849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3510831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c45187bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c45187ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4518608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c45150fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c45150fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3510832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35108330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35108330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c45150fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (1396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f62fe3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f62fe0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f62fe462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2443505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f244355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2443505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24434ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f62f79bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f62f79a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f62f5e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f62c0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f62c0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f24434eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24434ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24434ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f62c0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (1397 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe67f26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe67f23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe67f2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc917133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc91718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc917133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc91711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe67ebcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe67ebca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe67ea18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe67b50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe67b50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc91711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc91711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc91711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe67b50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (1398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fed7fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fed7f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fed7fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3901133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f390118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3901133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f390111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fed791bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fed791a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fed7768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fed425e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fed425b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f390111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f390111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f390111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fed425a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1399 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d37ff32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d37ff2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d37ff3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2716333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f271638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2716333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f271631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d37fec8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d37fec8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d37fead8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d37fb5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d37fb5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f271631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f271631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f271631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d37fb5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1400 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056506ed16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056506ed13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056506ed1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19f2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19f258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19f2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19f251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056506ecacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056506ecaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056506ec918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056506e940e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056506e940b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19f251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19f251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19f251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056506e940a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (1401 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = # | ... # `---data was truncated (10240/124514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565039aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565039abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565039af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cbc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cbc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cbc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cbc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556503944bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556503944a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565039298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565035d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565035d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cbc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cbc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cbc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565035d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (1402 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586944c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586944bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586944c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3832333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f383238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3832333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f383231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558694457bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558694457a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055869443c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586940ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586940ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f383231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f383231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f383231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586940eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1403 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056518313beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565183138e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056518313c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a95933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a9598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a95933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a9591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651830d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651830d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651830b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565182d65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565182d65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a9591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a9591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a9591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565182d65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (1404 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/410391) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609e75daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609e75d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609e75db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd573b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd573b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd573b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd573b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609e7570bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609e7570a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609e75558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609e7204e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609e7204b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd573b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd573b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd573b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609e7204a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (1405 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3f7e80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3f7e7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3f7e8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4963b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4963b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4963b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4963b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3f7e16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d3f7e16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d3f7dfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d3f7aaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d3f7aaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4963b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4963b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4963b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3f7aaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (1406 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555fe963eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555fe960e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555fe96462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f872fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f872fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f872fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f872fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555fe8f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555fe8f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555fe8de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555fe58de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555fe58db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f872fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f872fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f872fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555fe58da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (1407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ef5c14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ef5c11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ef5c1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f360fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f360fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f360fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f360fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef5baabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ef5baaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ef5b8f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ef583ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ef583eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f360fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f360fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f360fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef583ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (1408 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cd9936eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cd9933e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cd993762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5223849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5223849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5223831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cd98ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cd98cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cd98b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cd9560e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cd9560b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5223832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52238330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cd9560a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (1409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i16 # | ... # `---data was truncated (10240/84971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b98e40eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b98e40be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b98e40f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb9f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb9f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb9f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb9f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b98e3a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b98e3a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b98e3898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b98e038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b98e038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb9f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb9f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb9f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b98e038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1410 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a75d07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a75d04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a75d0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ffbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ffbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ffbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ffbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a75c9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a75c9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a75c828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a75931e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a75931b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ffbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ffbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ffbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a75931a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (1411 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @foo() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @bar() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @baz(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @quux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %call = call target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %0) # | ret target("riscv.vector.tuple", , 2) %call # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b97ba2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b97b9fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b97ba362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe10733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe1078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe10733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe1071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b97b38bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b97b38a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b97b1d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b977cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b977ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe1071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe1071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe1071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b977cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (1412 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c89c77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c89c74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c89c7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde4a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde4a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde4a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde4a431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c89c0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c89c0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c89bf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c898a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c898a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde4a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde4a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde4a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c898a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (1413 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e386ca6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e386ca3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e386ca762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c19449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c19449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c19431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e386c3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e386c3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e386c218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3868d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3868d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c19432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c194330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3868d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (1414 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cb3e58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cb3e55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cb3e5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ca1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ca1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ca1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ca1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cb3deebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cb3deea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cb3dd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cb3a82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cb3a82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ca1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ca1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ca1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cb3a82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (1415 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c66c8aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c66c8a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c66c8ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56b8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56b838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56b8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56b831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c66c842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c66c842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c66c8278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c66c4d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c66c4d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f56b831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56b831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56b831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c66c4d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (1416 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e9a2d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e9a2d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e9a2da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d06d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d06d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d06d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d06d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e9a26fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e9a26fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e9a2548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e99f03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e99f03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d06d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d06d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d06d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e99f03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (1417 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d93d1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d93d17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d93d1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f733ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f733aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f733ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f733ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d93cb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d93cb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d93c958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d93944e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d93944b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f733ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f733ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f733ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d93944a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (1418 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bc1548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bc1545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bc154962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf28a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf28aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf28a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf28a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bc14debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bc14dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bc14c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bc1172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bc1172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf28a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf28a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf28a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bc1172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (1419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db40668eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db40665e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db4066962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f520cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f520cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f520cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f520cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db405febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db405fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db405e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db40292e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db40292b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f520cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f520cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f520cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db40292a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (1420 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b521d18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b521d15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b521d1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34d2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34d28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34d2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34d2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b521caebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b521caea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b521c938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b521942e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b521942b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34d2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34d28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34d28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b521942a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-dot-product.c (1421 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 8 # | %__s0_827 = alloca <4 x i32>, align 8 # | %__s1_827 = alloca <16 x i8>, align 8 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x i32>, align 8 # | %tmp2 = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0_827, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %1, ptr %__s1_827, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 8 # | %4 = load <16 x i8>, ptr %__s1_827, align 8 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (1422 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> # | ... # `---data was truncated (10240/63117) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005612fbd9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612fbd9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612fbd9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6deed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6deed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6deed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6deed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612fbd33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612fbd33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612fbd188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612fb9c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612fb9c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6deed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6deed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6deed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612fb9c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (1423 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66314) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056413c0bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056413c0bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056413c0be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f794a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f794a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f794a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f794a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056413c053bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056413c053a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056413c0388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056413bce7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056413bce7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f794a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f794a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f794a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056413bce7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (1425 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e904503eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e904500e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e90450462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94c5305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94c535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94c5305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94c52ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e904499bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e904499a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e90447e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e90412de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e90412db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94c52eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94c52ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94c52ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e90412da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (1426 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (1427 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a6fbf32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6fbf2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6fbf3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3df4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3df478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3df4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3df471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6fbec8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6fbec8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6fbead8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6fbb5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6fbb5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3df471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3df471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3df471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6fbb5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (1428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e504c85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e504c82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e504c8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3c5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3c5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3c5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3c5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e504c1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e504c1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e504c008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5048afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5048afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3c5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3c5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3c5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5048afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (1429 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056306f98feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056306f98ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056306f99062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa213649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2136a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa213649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa213631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056306f925bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056306f925a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056306f90a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056306f5b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056306f5b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa213632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2136330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2136330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056306f5b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (1430 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/26976) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7e1d1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7e1d18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7e1d1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd83849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd838a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd83849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd83831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7e1cb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7e1cb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7e1c968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7e1945e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7e1945b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd83832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd838330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd838330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7e1945a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (1431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-crc32.c (1432 of 27910) ******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055876533aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558765337e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055876533b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5ab849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5ab8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5ab849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5ab831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587652d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587652d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587652b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558764f64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558764f64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5ab832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5ab8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5ab8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558764f64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1433 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8be4a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8be49fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8be4a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f515b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f515b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f515b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f515b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8be438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8be438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8be41d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8be0cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8be0ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f515b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f515b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f515b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8be0cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (1434 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056483f94deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056483f94ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056483f94e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01d5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01d538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01d5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01d531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056483f8e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056483f8e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056483f8c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056483f577e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056483f577b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01d531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01d531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01d531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056483f577a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (1435 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/58460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055775c1cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055775c1cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055775c1ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f353b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f353b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f353b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f353b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055775c163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055775c163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055775c1488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055775bdf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055775bdf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f353b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f353b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f353b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055775bdf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1436 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = e # | ... # `---data was truncated (10240/100513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c767d0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c767d09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c767d0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb99649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb996a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb99649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb99631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c767ca2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c767ca2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c767c878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c767936e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c767936b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb99632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb996330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb996330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c767936a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (1437 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (1438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564afd327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564afd324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564afd32862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8d1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8d1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8d1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8d1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564afd2bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564afd2bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564afd2a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564afcf51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564afcf51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8d1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8d1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8d1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564afcf51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (1439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056151d757eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056151d754e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056151d75862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23a6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23a658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23a6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23a651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056151d6edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056151d6eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056151d6d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056151d381e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056151d381b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23a651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23a651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23a651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056151d381a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (1440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (1441 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # | #0 0x0000561bd5d43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561bd5d40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561bd5d4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5bc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5bc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5bc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5bc831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bd5cd9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561bd5cd9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561bd5cbe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561bd596de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561bd596db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5bc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5bc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5bc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bd596da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (1442 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559da754feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559da754ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559da755062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e59333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e5938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e59333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e5931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559da74e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559da74e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559da74ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559da7179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559da7179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e5931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e5931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e5931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559da7179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (1443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620c139aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620c1397e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620c139b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe27f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe27f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe27f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe27f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620c1330bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620c1330a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620c13158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620c0fc4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620c0fc4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe27f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe27f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe27f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620c0fc4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (1444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a21c167eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a21c164e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a21c16862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10a6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10a638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10a6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10a631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a21c0fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a21c0fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a21c0e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a21bd91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a21bd91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10a631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10a631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10a631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a21bd91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (1445 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 5) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 5) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 18) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 3) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 11) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 7) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 4) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 19) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 7) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 15) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 31) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = lshr <16 x i8> %0, splat (i8 1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = lshr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = lshr <4 x i32> %0, splat (i32 10) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | ret <16 x i8> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | ret <4 x i32> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinlin # | ... # `---data was truncated (10240/66359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563195ea4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563195ea1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563195ea562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a92b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563195e3abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563195e3aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563195e1f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563195acee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563195aceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563195acea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (1446 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b53d9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b53d99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b53d9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7cca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7cca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7cca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7cca03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b53d32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b53d32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b53d178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b539c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b539c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7cca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7cca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7cca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b539c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (1447 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055860de12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055860de0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055860de1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb09e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb09e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb09e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb09e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055860dda8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055860dda8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055860dd8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055860da3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055860da3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb09e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb09e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb09e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055860da3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (1448 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630fb8c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630fb8bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630fb8c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb43ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb43eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb43ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb43ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630fb857bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630fb857a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630fb83c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630fb4ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630fb4ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb43ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb43ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb43ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630fb4eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (1449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c51f80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c51f7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c51f8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3887133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f388718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3887133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f388711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c51f16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c51f16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c51efb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c51baae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c51baab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f388711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f388711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f388711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c51baaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-endianness.c (1450 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-arm-none-eabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 2 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 3 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 1 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # | #0 0x000055e031703eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e031700e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e03170462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51aa21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51aa2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51aa21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51aa203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e031699bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e031699a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e03167e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e03132de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e03132db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f51aa204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51aa2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51aa2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e03132da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (1451 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfs # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e399034eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e399031e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e39903562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff748249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff748249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff748231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e398fcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e398fcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e398faf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e398c5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e398c5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff748232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7482330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e398c5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (1452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608a0367eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608a0364e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608a036862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b0aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b0aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b0aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b0aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608a02fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608a02fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608a02e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056089ff91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056089ff91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b0aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b0aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b0aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056089ff91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (1453 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556750583eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556750580e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055675058462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff332333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff33238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff332333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff33231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556750519bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556750519a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567504fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005567501ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005567501adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff33231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff33231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff33231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567501ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (1454 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> # | %fmla = bitcast <16 x i8> %4 to <8 x half> # | %fmla1 = bitcast <16 x i8> %3 to <8 x half> # | %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %fmla2, ptr %ref.tmp, align 16 # | %7 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %7, ptr %__ret, align 16 # | %8 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %8, ptr %tmp, align 16 # | %9 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp, align 8 # | %10 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %10, ptr %__ret, align 8 # | %11 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %11, ptr %tmp, align 8 # | %12 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 # | ... # `---data was truncated (10240/13273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056463afa6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056463afa3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056463afa762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa542533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa54258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa542533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa54251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056463af3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056463af3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056463af218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056463abd0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056463abd0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa54251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa54251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa54251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056463abd0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (1455 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558752051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055875204ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055875205262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f997e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f997e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f997e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f997e231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558751fe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558751fe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558751fcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558751c7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558751c7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f997e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f997e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f997e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558751c7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (1456 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f74f2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f74f29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f74f2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3f6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3f6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3f6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3f6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f74ec2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f74ec2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f74ea78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f74b56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f74b56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3f6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3f6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3f6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f74b56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (1457 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1c68f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1c68efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1c68f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1aa6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1aa638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1aa6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1aa631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1c6888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1c6888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1c686d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1c651ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1c651cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1aa631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1aa631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1aa631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1c651ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1458 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (1459 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (1460 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f70b04aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f70b047e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f70b04b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f914bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f914bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f914bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f914bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f70afe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f70afe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f70afc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f70ac74e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f70ac74b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f914bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f914bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f914bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f70ac74a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (1461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (1462 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf9d31ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf9d319e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf9d31d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97bf105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97bf15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97bf105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97bf0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf9d2b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf9d2b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf9d2978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf9cf46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf9cf46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97bf0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97bf0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97bf0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf9cf46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (1463 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557737b01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557737afee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557737b0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbeec733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbeec78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbeec733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbeec71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557737a97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557737a97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557737a7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055773772be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055773772bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbeec71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbeec71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbeec71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055773772ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1464 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %vext, ptr %ref.tmp, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %4, ptr %__ret, align 8 # | %5 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %5, ptr %tmp, align 8 # | %6 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | %5 = bitcast <8 x i8> %3 to <4 x i16> # | %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> # | store <4 x i16> %vext, ptr %ref.tmp, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %6, ptr %__ret, align 8 # | %7 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %7, ptr %tmp, align 8 # | %8 = load <4 x i16>, ptr %tmp, align 8 # | ret <4 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %__s1 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <2 x i32> # | %5 = bitcast <8 x i8> %3 to <2 x i32> # | %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> # | store <2 x i32> %vext, ptr %ref.tmp, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %6, ptr %__ret, align 8 # | %7 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %7, ptr %tmp, align 8 # | %8 = load <2 x i32>, ptr %tmp, align 8 # | ret <2 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer # | store <1 x i64> %vext, ptr %ref.tmp, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %6, ptr %__ret, align 8 # | %7 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %7, ptr %tmp, align 8 # | %8 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca <16 x i8>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %vext, ptr %ref.tmp, align 16 # | %4 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %4, ptr %__ret, align 16 # | %5 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %5, ptr %tmp, align 16 # | %6 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x i16> # | %5 = bitcast <16 x i8> %3 to <8 x i16> # | %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> # | store <8 x i16> %vext, ptr %ref.tmp, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %6, ptr %__ret, align 16 # | %7 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %7, ptr %tmp, align 16 # | %8 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <4 x i32> # | %5 = bitcast <16 x i8> %3 to <4 x i32> # | %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> # | store <4 x i32> %vext, ptr %ref.tmp, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %6, ptr %__ret, align 16 # | %7 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %7, ptr %tmp, align 16 # | %8 = load <4 x i32>, ptr %tmp, align 16 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> # | store <2 x i64> %vext, ptr %ref.tmp, align 16 # | %6 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %6, ptr %__ret, align 16 # | %7 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %7, ptr %tmp, align 16 # | %8 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> # | ... # `---data was truncated (10240/29598) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055cc3aa50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc3aa4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc3aa5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe806849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8068a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe806849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe806831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc3a9e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc3a9e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc3a9cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc3a67ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc3a67ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe806832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8068330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8068330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc3a67aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (1465 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (1466 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b78c457eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b78c454e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b78c45862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa58649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa58649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa58631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b78c3edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b78c3eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b78c3d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b78c081e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b78c081b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa58632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa586330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b78c081a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (1467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556682e2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556682e27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556682e2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e9db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e9db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e9db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e9db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556682dc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556682dc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556682da58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556682a54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556682a54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e9db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e9db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e9db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556682a54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (1468 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/126436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055afef33deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afef33ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afef33e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2cab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2cab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2cab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2caaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afef2d3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afef2d3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afef2b88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afeef67e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afeef67b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe2caaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2caaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2caaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afeef67a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (1469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561fcf3d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561fcf3cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561fcf3d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b42933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b4298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b42933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b4291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561fcf366bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561fcf366a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561fcf34b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561fceffae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561fceffab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b4291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b4291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b4291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fceffaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (1470 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (1471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/68133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce48c16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce48c13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce48c1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9995649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99956a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9995649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9995631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce48bacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce48baca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce48b918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce48840e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce48840b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9995632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99956330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99956330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce48840a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (1472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e57951ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e579519e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e57951d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c2b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c2b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c2b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c2b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5794b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5794b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5794978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e579146e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e579146b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c2b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c2b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c2b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e579146a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (1473 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a05002eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a04fffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a0500362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65bb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65bb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65bb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65bb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a04f98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a04f98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a04f7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a04c2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a04c2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65bb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65bb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65bb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a04c2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1474 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (1475 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f1e2a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f1e2a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f1e2a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f850cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f850cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f850cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f850cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f1e23ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f1e23ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f1e2238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f1ded2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f1ded2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f850cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f850cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f850cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f1ded2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (1476 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebf67ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebf67fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebf680062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa6d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa6d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa6d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa6d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebf6795bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebf6795a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebf677a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebf6429e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebf6429b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa6d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa6d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa6d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebf6429a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1477 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056386e5afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056386e5ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056386e5b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecea705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecea75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecea705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecea6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056386e545bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056386e545a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056386e52a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056386e1d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056386e1d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecea6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecea6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecea6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056386e1d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (1478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | # | ... # `---data was truncated (10240/169917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598b4b15eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598b4b12e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598b4b1662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8baa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598b4aabbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598b4aaba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598b4a908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598b473fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598b473fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8baa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598b473fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (1479 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056014df9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056014df9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056014dfa062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc3ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc3ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc3ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc3ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056014df35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056014df35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056014df1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056014dbc9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056014dbc9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc3ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc3ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc3ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056014dbc9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (1480 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c99a4edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c99a4eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c99a4ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa341049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3410a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa341049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa341031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c99a483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c99a483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c99a4688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c99a117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c99a117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa341032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3410330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3410330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c99a117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (1481 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560967d22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560967d1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560967d2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e6a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e6a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e6a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e6a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560967cb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560967cb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560967c9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056096794ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056096794cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e6a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e6a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e6a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056096794ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (1482 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a51e70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a51e6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a51e7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5adfc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5adfc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5adfc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5adfc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a51e06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a51e06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a51deb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a51a9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a51a9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5adfc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5adfc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5adfc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a51a9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (1483 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c47181eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c4717ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c4718262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb625849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6258a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb625849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb625831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c47117bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c47117a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c470fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c46dabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c46dabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb625832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6258330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6258330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c46daba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (1484 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594a8460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594a845de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594a846162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71b8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71b895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71b8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71b88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594a83f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594a83f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594a83db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594a808ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594a808ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71b88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71b88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71b88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594a808aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (1485 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563526898eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563526895e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056352689962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1986449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1986449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1986431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056352682ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056352682ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635268138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635264c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635264c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1986432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635264c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (1486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (1487 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563669263eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563669260e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056366926462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e15333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e1538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e15333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e1531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636691f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005636691f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005636691de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563668e8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563668e8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e1531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e1531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e1531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563668e8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (1488 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccdae6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ccdae6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ccdae6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9654049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96540a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9654049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9654031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccdae03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ccdae03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ccdade88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ccdaa97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ccdaa97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9654032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96540330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96540330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccdaa97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (1489 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, # | ... # `---data was truncated (10240/23056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3f55fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b3f55f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b3f55fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec48049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec480a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec48049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec48031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3f5592bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b3f5592a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3f55778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b3f5226e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b3f5226b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec48032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec480330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec480330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3f5226a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (1490 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b3f859eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556b3f856e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556b3f85a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6996d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6996d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6996d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6996ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b3f7efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556b3f7efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556b3f7d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556b3f483e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556b3f483b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6996ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6996cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6996cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b3f483a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (1491 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr.i = alloca bfloat, align 2 # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | store bfloat %0, ptr %bf.addr.i, align 2 # | %1 = load bfloat, ptr %bf.addr.i, align 2 # | %2 = fpext bfloat %1 to float # | ret float %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr.i = alloca float, align 4 # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | store float %0, ptr %sf.addr.i, align 4 # | %1 = load float, ptr %sf.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | ret bfloat %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cd7f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cd7f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cd7f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0109733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f010978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0109733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f010971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cd7ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cd7ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cd7eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cd7b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cd7b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f010971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f010971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f010971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cd7b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (1492 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056161cefceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056161cef9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056161cefd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaf5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaf518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaf5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaf511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056161ce92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056161ce92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056161ce778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056161cb26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056161cb26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaf511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaf511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaf511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056161cb26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (1493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055812c9cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055812c9cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055812c9ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc165f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc165f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc165f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc165f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055812c963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055812c963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055812c9488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055812c5f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055812c5f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc165f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc165f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc165f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055812c5f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (1494 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e55f466eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e55f463e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e55f46762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9489b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9489b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9489b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9489b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e55f3fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e55f3fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e55f3e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e55f090e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e55f090b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9489b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9489b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9489b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e55f090a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (1495 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = extractelement <8 x half> %0, i32 2 # | ret half %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = extractelement <4 x float> %0, i32 3 # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 4 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 0 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 10 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 3 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 3 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 1 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 1 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca <8 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load half, ptr %a.addr, align 2 # | %2 = insertelement <8 x half> %0, half %1, i32 4 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 8 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load float, ptr %a.addr, align 4 # | %2 = insertelement <4 x float> %0, float %1, i32 2 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 12 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 6 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 2 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 0 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 2 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 7 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 1 # | ret <2 x i64> %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055587a0fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055587a0f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055587a0fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbded249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbded2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbded249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbded231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055587a092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055587a092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055587a0778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555879d26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555879d26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbded232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbded2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbded2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555879d26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (1496 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005640e99d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640e99d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640e99d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b8c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b8c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b8c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b8c631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640e9969bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640e9969a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640e994e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640e95fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640e95fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b8c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b8c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b8c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640e95fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (1497 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c99228eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c99225e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c9922962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa35649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa35649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa35631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c991bebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c991bea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c991a38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c98e52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c98e52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa35632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa356330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c98e52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (1498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8528e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8528dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8528e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b62649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b626a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b62649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b62631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a852878bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a852878a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a85285d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a85250ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a85250cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b62632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b626330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b626330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a85250ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (1499 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f59c3e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f59c3dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f59c3e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1809b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1809b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1809b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1809b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f59c376bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f59c376a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f59c35b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f59c00ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f59c00ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1809b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1809b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1809b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f59c00aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (1500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f # | ... # `---data was truncated (10240/165246) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9c62d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9c62d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9c62d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b93905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b9395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b93905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b938ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9c626ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9c626ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9c62538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9c5f02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9c5f02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b938eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b938ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b938ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9c5f02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1501 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581c97e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581c97e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581c97e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb12fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb12fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb12fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb12fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581c9779bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581c9779a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581c975e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581c940de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581c940db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb12fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb12fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb12fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581c940da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (1502 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555582469eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555582466e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055558246a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4d331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555823ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555823ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555823e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555582093e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555582093b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4d331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555582093a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (1503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576096adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576096aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576096ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa918c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa918ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa918c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa918c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557609643bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557609643a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576096288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576092d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576092d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa918c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa918c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa918c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576092d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (1504 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e0b102eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e0b0ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e0b10362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff25ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff25ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff25ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff25eced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e0b098bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e0b098a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e0b07d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e0ad2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e0ad2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff25eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff25ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff25ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e0ad2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (1505 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c490cf1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c490ceee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c490cf262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff114305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff11435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff114305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1142ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c490c87bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c490c87a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c490c6c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c49091be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c49091bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1142eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1142ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1142ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c49091ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1506 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/95437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630c8a38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630c8a35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630c8a3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f729cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f729cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f729cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f729cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630c89cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630c89cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630c89b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630c8662e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630c8662b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f729cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f729cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f729cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630c8662a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (1507 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (1508 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv16i8(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8i16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4i32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8f16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8f16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4f32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4f32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2f64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2f64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 { # | entry: # | %x0.addr = alloca i8, align 1 # | %x1.addr = alloca i8, align 1 # | %x2.addr = alloca i8, align 1 # | %x3.addr = alloca i8, align 1 # | %x4.addr = alloca i8, align 1 # | %x5.addr = alloca i8, align 1 # | %x6.addr = alloca i8, align 1 # | %x7.addr = alloca i8, align 1 # | %x8.addr = alloca i8, align 1 # | %x9.addr = alloca i8, align 1 # | %x10.addr = alloca i8, align 1 # | %x11.addr = alloca i8, align 1 # | %x12.addr = alloca i8, align 1 # | %x13.addr = alloca i8, align 1 # | %x14.addr = alloca i8, align 1 # | %x15.addr = alloca i8, align 1 # | store i8 %x0, ptr %x0.addr, align 1 # | store i8 %x1, ptr %x1.addr, align 1 # | store i8 %x2, ptr %x2.addr, align 1 # | store i8 %x3, ptr %x3.addr, align 1 # | store i8 %x4, ptr %x4.addr, align 1 # | store i8 %x5, ptr %x5.addr, align 1 # | store i8 %x6, ptr %x6.addr, align 1 # | store i8 %x7, ptr %x7.addr, align 1 # | store i8 %x8, ptr %x8.addr, align 1 # | store i8 %x9, ptr %x9.addr, align 1 # | store i8 %x10, ptr %x10.addr, align 1 # | store i8 %x11, ptr %x11.addr, align 1 # | store i8 %x12, ptr %x12.addr, align 1 # | store i8 %x13, ptr %x13.addr, align 1 # | store i8 %x14, ptr %x14.addr, align 1 # | store i8 %x15, ptr %x15.addr, align 1 # | %0 = load i8, ptr %x0.addr, align 1 # | %1 = load i8, ptr %x1.addr, align 1 # | %2 = load i8, ptr %x2.addr, align 1 # | %3 = load i8, ptr %x3.addr, align 1 # | %4 = load i8, ptr %x4.addr, align 1 # | %5 = load i8, ptr %x5.addr, align 1 # | %6 = load i8, ptr %x6.addr, align 1 # | %7 = load i8, ptr %x7.addr, align 1 # | %8 = load i8, ptr %x8.addr, align 1 # | %9 = load i8, ptr %x9.addr, align 1 # | %10 = load i8, ptr %x10.addr, align 1 # | %11 = load i8, ptr %x11.addr, align 1 # | %12 = load i8, ptr %x12.addr, align 1 # | %13 = load i8, ptr # | ... # `---data was truncated (10240/42600) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563d8febaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d8feb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d8febb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb842133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb84218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb842133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb84211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d8fe50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d8fe50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d8fe358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d8fae4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d8fae4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb84211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb84211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb84211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d8fae4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (1509 of 27910) ******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %6, ptr %__ret.i, align 8 # | %7 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_812 = alloca <4 x float>, align 8 # | %__s0_812 = alloca <4 x float>, align 8 # | %__s1_812 = alloca <8 x bfloat>, align 8 # | %__s2_812 = alloca <8 x bfloat>, align 8 # | %ref.tmp = alloca <4 x float>, align 8 # | %__ret = alloca <4 x float>, align 8 # | %__s0 = alloca <4 x float>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x float>, align 8 # | %tmp2 = alloca <4 x float>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | store <4 x float> %0, ptr %__s0_812, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | store <8 x bfloat> %1, ptr %__s1_812, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <8 x bfloat> %2, ptr %__s2_812, align 8 # | %3 = load <4 x float>, ptr %__s0_812, align 8 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 8 # | %5 = load <4 x float>, ptr %__s2_812, align 8 # | store <4 x float> %5, ptr %__s0, align 8 # | %6 = load <16 x i8>, ptr %__s0, align 8 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <4 x float>, ptr %ref.tmp1, align 8 # | store <4 x float> %8, ptr %__ret, align 8 # | %9 = load <4 x float>, ptr %__ret, align 8 # | store <4 x float> %9, ptr %tmp, align 8 # | %10 = load <4 x float>, ptr %tmp, align 8 # | store <4 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x float> %3, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %15, ptr %__ret.i, align 8 # | %16 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %16, ptr %__ret_812, align 8 # | %17 = load <4 x float>, ptr %__ret_812, align 8 # | store <4 x float> %17, ptr %tmp2, align 8 # | %18 = load <4 x float>, ptr %tmp2, align 8 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_814 = alloca <2 x float>, al # | ... # `---data was truncated (10240/54174) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005607ffdd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607ffdd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607ffdda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f8c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f8c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f8c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f8c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607ffd6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607ffd6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607ffd548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607ffa03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607ffa03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f8c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f8c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f8c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607ffa03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (1510 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f60b67aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f60b677e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f60b67b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd36649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd36649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd36631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f60b610bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f60b610a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f60b5f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f60b2a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f60b2a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd36632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd366330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f60b2a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (1511 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f47dca3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f47dca0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f47dca462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9ee849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9ee8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9ee849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9ee831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f47dc39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f47dc39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f47dc1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f47d8cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f47d8cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9ee832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9ee8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9ee8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f47d8cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1512 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv1f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv2f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m1_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv4f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv16f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m8_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv32f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32mf2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv1f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m1_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m4_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv8f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m8_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv16f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m1_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv1f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m2_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m4_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv4f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m8_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv8f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fc7368eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fc7365e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fc736962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae8f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae8f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae8f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae8f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fc72febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fc72fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fc72e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fc6f92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fc6f92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae8f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae8f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae8f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fc6f92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (1513 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632d26c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632d26bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632d26c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f330ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f330eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f330ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f330ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632d2657bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632d2657a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632d263c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632d22ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632d22ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f330ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f330ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f330ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632d22eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (1514 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | # | ... # `---data was truncated (10240/40891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e65b42beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e65b428e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e65b42c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36e5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e65b3c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e65b3c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e65b3a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e65b055e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e65b055b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f36e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36e52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e65b055a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (1515 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562840ebeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562840ebbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562840ebf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe593249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5932a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe593249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe593231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562840e54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562840e54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562840e398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562840ae8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562840ae8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe593232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5932330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5932330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562840ae8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (1516 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (1517 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/67482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63cfd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c63cfd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c63cfd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ab6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ab6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ab6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ab6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63cf69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c63cf69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c63cf4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c63cbfde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c63cbfdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ab6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ab6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ab6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63cbfda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (1518 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | % # | ... # `---data was truncated (10240/33764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1d5e37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1d5e34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1d5e3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58b5905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58b595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58b5905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58b58ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1d5dcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1d5dcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1d5db28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1d5a61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1d5a61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58b58eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58b58ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58b58ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1d5a61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (1519 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056257f63eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056257f63be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056257f63f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00acb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00acb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00acb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00acb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056257f5d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056257f5d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056257f5b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056257f268e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056257f268b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f00acb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00acb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00acb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056257f268a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (1520 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587bb548eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587bb545e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587bb54962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf36649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf366a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf36649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf36631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587bb4debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587bb4dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587bb4c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587bb172e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587bb172b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf36632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf366330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf366330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587bb172a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (1521 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = and <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = and <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = and <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = and <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055694516ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556945169e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055694516d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f057d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f057d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f057d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f057d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556945102bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556945102a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569450e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556944d96e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556944d96b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f057d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f057d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f057d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556944d96a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1522 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563423983eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563423980e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056342398462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe670a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe670aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe670a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe670a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563423919bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563423919a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634238fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634235ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634235adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe670a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe670a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe670a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634235ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (1523 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"SmallDataLi # | ... # `---data was truncated (10240/10285) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cb8221eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cb821ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cb822262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5ed81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5ed8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5ed81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5ed803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cb81b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cb81b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cb819c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cb7e4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cb7e4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5ed804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5ed8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5ed8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cb7e4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (1524 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556374d0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556374d0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556374d0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe184705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe18475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe184705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1846ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556374ca3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556374ca3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556374c888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556374937e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556374937b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1846eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1846ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1846ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556374937a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (1525 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d890a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d890a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d890aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfec733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfec78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfec733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfec71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d8903fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d8903fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d890248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d88cd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d88cd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfec71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfec71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfec71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d88cd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (1526 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | # | ... # `---data was truncated (10240/135119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562d27bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562d27b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562d27bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94c1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94c138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94c1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94c131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562d2751bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562d2751a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562d27368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562d23e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562d23e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94c131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94c131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94c131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562d23e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (1527 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056340e7dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056340e7d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056340e7dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08eb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056340e772bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056340e772a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056340e7578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056340e406e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056340e406b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056340e406a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (1528 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8e7e34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8e7e31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8e7e3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e0f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e0f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e0f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e0f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8e7dcabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8e7dcaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8e7daf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8e7a5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8e7a5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e0f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e0f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e0f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8e7a5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (1529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf7d674eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf7d671e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf7d67562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe872933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe87298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe872933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe87291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf7d60abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf7d60aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf7d5ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf7d29ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf7d29eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe87291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe87291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe87291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf7d29ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (1530 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <8 x i8>, al # | ... # `---data was truncated (10240/26059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005572246a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055722469ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572246a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4b2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557224637bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557224637a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055722461c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572242cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572242cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4b2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572242cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (1531 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5055eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5055ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5055ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc18b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc18b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc18b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc18b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a505584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a505584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5055698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a505218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a505218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc18b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc18b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc18b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a505218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (1532 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd574f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cd574f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cd574f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe31a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe31a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe31a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe31a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd5748bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cd5748ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cd574708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cd5711fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cd5711fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe31a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe31a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe31a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd5711fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (1533 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f3866aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f38667e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f3866b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7630733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f763078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7630733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f763071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f38600bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f38600a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f385e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f38294e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f38294b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f763071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f763071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f763071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f38294a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1534 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ef49e2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ef49dfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ef49e362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9dbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9dbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9dbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9dbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ef4978bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ef4978a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ef495d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ef460ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ef460cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9dbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9dbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9dbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ef460ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (1535 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | # | ... # `---data was truncated (10240/100521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589a6230eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589a622de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589a623162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff801505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff80155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff801505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8014ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589a61c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005589a61c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589a61ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589a5e5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589a5e5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8014eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8014ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8014ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589a5e5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (1536 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , # | ... # `---data was truncated (10240/170497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d63a39deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d63a39ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d63a39e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6456c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6456ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6456c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6456c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d63a333bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d63a333a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d63a3188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d639fc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d639fc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6456c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6456c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6456c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d639fc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/builtins-arm.c (1537 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-unknown-unknown-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @f0() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | %b.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load ptr, ptr %b.addr, align 4 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf0(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtr.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf1(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtru.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd0(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtr.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd1(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtru.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 0, ptr %res, align 4 # | store volatile i32 1, ptr %res, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_barrier() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | call void @llvm.arm.dsb(i32 2) # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch(i32 noundef %i) #0 { # | entry: # | %i.addr = alloca i32, align 4 # | store i32 %i, ptr %i.addr, align 4 # | call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp() #0 { # | entry: # | call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp2() #0 { # | entry: # | call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc2() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr2(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_lo # | ... # `---data was truncated (10240/15632) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4e571eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4e571be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4e571f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d1df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d1df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d1df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d1df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4e56b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4e56b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4e56998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4e5348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4e5348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d1df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d1df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d1df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4e5348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (1538 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a56699eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a56696e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a5669a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67d7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67d7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67d7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67d7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a5662fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a5662fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a566148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a562c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a562c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67d7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67d7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67d7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a562c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (1539 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de1e308eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de1e305e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de1e30962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4caf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4caf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4caf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4caf11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de1e29ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de1e29ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de1e2838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de1df32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de1df32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4caf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4caf11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4caf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de1df32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (1540 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (1541 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.ris # | ... # `---data was truncated (10240/12914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a4716feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a4716ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a4717062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d4fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d4fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d4fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d4fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a47105bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a47105a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a470ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a46d99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a46d99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d4fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d4fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d4fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a46d99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (1542 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056307e0f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056307e0f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056307e0f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde56e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde56ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde56e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde56e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056307e08dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056307e08da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056307e0728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056307dd21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056307dd21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde56e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde56e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde56e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056307dd21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (1543 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (1544 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed68067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed68064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed6806862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4c6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4c658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4c6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4c651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed67ffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed67ffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed67fe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed67c91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed67c91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4c651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4c651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4c651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed67c91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (1545 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055faa48b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faa48b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faa48ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73d0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73d018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73d0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73d011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faa484fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faa484fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faa48348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055faa44e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055faa44e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73d011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73d011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73d011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faa44e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (1546 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a0e0f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a0e0f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a0e0f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc59449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc59449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc59431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a0e089bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a0e089a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a0e06e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a0dd1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a0dd1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc59432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc594330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a0dd1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (1547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1ac131eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1ac12ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1ac13262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f473cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f473cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f473cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f473cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1ac0c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1ac0c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1ac0ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1abd5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1abd5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f473cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f473cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f473cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1abd5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (1548 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e79c424eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e79c421e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e79c42562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6afbf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6afbf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6afbf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6afbeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e79c3babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e79c3baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e79c39f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e79c04ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e79c04eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6afbeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6afbeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6afbeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e79c04ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (1549 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fa247beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fa2478e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fa247c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbd9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbd9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbd9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbd9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fa2411bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fa2411a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fa23f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fa20a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fa20a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbd9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbd9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbd9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fa20a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/aapcs-bitfield.c (1550 of 27910) ******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-eabi" # | # | %struct.st6 = type { i16, i8, i8 } # | %struct.st7b = type { i8, [3 x i8], %struct.st7a } # | %struct.st7a = type { i8, i8, [2 x i8] } # | %struct.st11 = type <{ i8, i16, i8 }> # | %struct.st13 = type <{ i8, i32 }> # | %struct.st16 = type { i32, i16, i32, i16 } # | %struct.st17 = type <{ i32, i8 }> # | %struct.zero_bitfield = type { i8, i8, [2 x i8] } # | %struct.zero_bitfield_ok = type { i16, i32 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st0_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st0_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st1_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.ashr = ashr i16 %bf.load, 10 # | %conv = sext i16 %bf.ashr to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st1_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, 1023 # | %bf.set = or i16 %bf.clear, 1024 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st2_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 9 # | %bf.ashr = ashr i32 %bf.shl, 25 # | %bf.cast = trunc i32 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st2_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -8323073 # | %bf.set = or i32 %bf.clear, 65536 # | store i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st3_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st3_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store volatile i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st4_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 2 # | %bf.ashr = ashr i16 %bf.shl, 11 # | %bf.cast = trunc i16 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -15873 # | %bf.set = or i16 %bf.clear, 512 # | store volatile i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -512 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st5_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 11 # | %bf.ashr = ashr i32 %bf.shl, 27 # | %bf.cast = trunc i32 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st5_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -2031617 # | %bf.set = or i32 %bf.clear, 65536 # | store volatile i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st6_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %x = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 4 # | %bf.ashr = ashr i16 %bf.shl, 4 # | %bf.cast = sext i16 %bf.ashr to i32 # | store i32 %bf.cast, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | %2 = load volatile i8, ptr %b, align 2 # | %conv = sext i8 %2 to i32 # | %3 = load i32, ptr %x, align 4 # | %add = add nsw i32 %3, %conv # | store i32 %add, ptr %x, align 4 # | %4 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2 # | %bf.load1 = load volatile i8, ptr %c, align 1 # | %bf.shl2 = shl i8 %bf.load1, 3 # | %bf.ashr3 = ashr i8 %bf.shl2, 3 # | %bf.cast4 = sext i8 %bf.ashr3 to i32 # | %5 = load i32, ptr %x, align 4 # | %add5 = add nsw i32 %5, %bf.cast4 # | store i32 %add5, ptr %x, align 4 # | %6 = load i32, ptr %x, align 4 # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st6_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -4096 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | store i8 2, ptr %b, align 2 # | %2 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2 # | %bf.load1 = load i8, ptr %c, align 1 # | %bf.clear2 = and i8 %bf.load1, -32 # | %bf.set3 = or i8 %bf.clear2, 3 # | store i8 %bf.set3, ptr %c, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st7_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %r = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | %1 = load i8, ptr %x, align 4 # | %conv = sext i8 %1 to i32 # | store i32 %conv, ptr %r, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | %3 = load volatile i8, ptr %a, align 4 # | %conv1 = sext i8 %3 to i32 # | %4 = load i32, ptr %r, align 4 # | %add = add nsw i32 %4, %conv1 # | store i32 %add, ptr %r, align 4 # | %5 = load ptr, ptr %m.addr, align 4 # | %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.shl = shl i8 %bf.load, 3 # | %bf.ashr = ashr i8 %bf.shl, 3 # | %bf.cast = sext i8 %bf.ashr to i32 # | %6 = load i32, ptr %r, align 4 # | %add3 = add nsw i32 %6, %bf.cast # | store i32 %add3, ptr %r, align 4 # | %7 = load i32, ptr %r, align 4 # | ret i32 %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st7_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | store i8 1, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | store volatile i8 2, ptr %a, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.clear = and i8 %bf.load, -32 # | %bf.set = or i8 %bf.clear, 3 # | store volatile i8 %bf.set, ptr %b, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | store i16 -1, ptr %0, align 4 # | ret i32 65535 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @read_st9(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 4 # | %bf.cast = sext i8 %bf.load to i32 # | r # | ... # `---data was truncated (10240/24998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f25cbcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f25cbc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f25cbcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4ba705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4ba75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4ba705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4ba6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f25cb60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f25cb60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f25cb458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f25c7f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f25c7f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4ba6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4ba6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4ba6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f25c7f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (1551 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c0a24deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c0a24ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c0a24e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f498a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f498a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f498a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f498a231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c0a1e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c0a1e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c0a1c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c09e77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c09e77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f498a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f498a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f498a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c09e77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (1552 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocall # | ... # `---data was truncated (10240/12425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f38414eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f38411e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f3841562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76a6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76a6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76a6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76a6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f383aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f383aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f3838f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f3803ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f3803eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76a6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76a6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76a6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f3803ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (1553 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1554 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561371ddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561371dd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561371ddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe129649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1296a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe129649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe129631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561371d72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561371d72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561371d578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561371a06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561371a06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe129632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1296330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1296330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561371a06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (1555 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad191f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad191eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad191f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1136905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f113695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1136905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11368ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad19187bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad19187a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad1916c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad18e1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad18e1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f11368eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11368ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11368ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad18e1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (1556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f02385eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f02382e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f0238662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca90d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca90d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca90d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca90d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f0231bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f0231ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f023008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f01fafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f01fafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca90d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca90d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca90d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f01fafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (1557 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, ali # | ... # `---data was truncated (10240/201234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571bc2e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571bc2e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571bc2e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3093533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f309358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3093533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f309351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571bc27bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571bc27ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571bc2608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571bbf0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571bbf0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f309351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f309351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f309351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571bbf0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (1558 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.add # | ... # `---data was truncated (10240/14453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594db670eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594db66de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594db67162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91ac333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91ac38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91ac333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91ac31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594db606bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594db606a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594db5eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594db29ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594db29ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91ac31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91ac31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91ac31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594db29aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (1559 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (1560 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (1561 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1 # | ... # `---data was truncated (10240/26476) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fda04ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fda04fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fda050062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6a9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6a998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6a9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6a991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fda0495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fda0495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fda047a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fda0129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fda0129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6a991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6a991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6a991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fda0129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (1562 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055828df31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055828df2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055828df3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0215c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0215ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0215c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0215c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055828dec7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055828dec7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055828deac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055828db5be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055828db5bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0215c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0215c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0215c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055828db5ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (1563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/176535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ceeb9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ceeb98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ceeb9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f791b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f791b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f791b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f791b831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ceeb31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ceeb31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ceeb168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559cee7c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559cee7c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f791b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f791b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f791b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cee7c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1564 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569ba42beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569ba428e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569ba42c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0041333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f004138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0041333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f004131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569ba3c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569ba3c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569ba3a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569ba055e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569ba055b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f004131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f004131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f004131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569ba055a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (1565 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = or <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = or <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = or <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = or <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, al # | ... # `---data was truncated (10240/11056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9c3cb9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9c3cb6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9c3cba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb48b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb48b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb48b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb48b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9c3c4fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9c3c4fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9c3c348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9c38e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9c38e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb48b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb48b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb48b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9c38e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (1566 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055660dc83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055660dc80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055660dc8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65a8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65a835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65a8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65a82ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055660dc19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055660dc19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055660dbfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055660d8ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055660d8adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65a82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65a82ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65a82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055660d8ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (1567 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c18e3afeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c18e3ace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c18e3b062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe92905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe9295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe92905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe928ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c18e345bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c18e345a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c18e32a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c18dfd9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c18dfd9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe928eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe928ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe928ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c18dfd9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (1568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (1569 of 27910) ******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | declare noundef zeroext i1 @_Z1av() #1 # | # | declare noundef zeroext i1 @_Z1bv() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.expect.i64(i64, i64) #2 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true) # | br i1 %call.expval, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true) # | br i1 %call1.expval, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i1 @llvm.expect.i1(i1, i1) #2 # | # | declare noundef zeroext i1 @_Z1cv() #1 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1cv() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: ; preds = %lor.lhs.false # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %lor.end # | # | lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry # | %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %lor.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.end # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %if.then, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %if.then, label %lor.lhs.false2 # | # | lor.lhs.false2: ; preds = %lor.lhs.false # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.lhs.false2 # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %dec = add nsw i32 %2, -1 # | store i32 %dec, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: # | ... # `---data was truncated (10240/28468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # | #0 0x0000559bc4dc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bc4dc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bc4dc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9bfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9bfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9bfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9bfc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bc4d59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bc4d59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bc4d3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bc49ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bc49edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9bfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9bfc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9bfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bc49eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (1570 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c081c47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c081c44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c081c4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3283449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32834a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3283449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3283431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c081bddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c081bdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c081bc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c081871e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c081871b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3283432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32834330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32834330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c081871a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (1571 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe7970ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe79709e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe7970d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4729733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f472978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4729733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f472971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe796a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe796a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe796878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe79336e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe79336b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f472971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f472971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f472971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe79336a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (1572 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea2a26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dea2a23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dea2a2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feba261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feba26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feba261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feba2603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea29bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dea29bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dea29a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dea2650e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dea2650b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feba2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feba26050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feba26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea2650a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1573 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | # | ... # `---data was truncated (10240/223129) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c845d73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c845d70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c845d7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b9df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b9df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b9df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b9df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c845d09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c845d09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c845cee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c84599de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c84599db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b9df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b9df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b9df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c84599da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (1574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9a9a10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9a9a0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9a9a1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38b5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38b52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38b5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38b5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9a99a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9a99a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9a998b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9a963ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9a963ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38b5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38b52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38b52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9a963aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (1575 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056084940ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560849409e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056084940d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1f6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1f64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1f6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1f6431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608493a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608493a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608493878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560849036e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560849036b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1f6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1f64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1f64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560849036a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (1576 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd6d54eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd6d54be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd6d54f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0271533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f027158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0271533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f027151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd6d4e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd6d4e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd6d4c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd6d178e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd6d178b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f027151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f027151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f027151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd6d178a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1577 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ab6758eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ab6755e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ab675962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa950449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa950449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa950431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ab66eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ab66eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ab66d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ab6382e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ab6382b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa950432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9504330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ab6382a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (1578 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t. # | ... # `---data was truncated (10240/15486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631eb95beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631eb958e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631eb95c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5813249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58132a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5813249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5813231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631eb8f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631eb8f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631eb8d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631eb585e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631eb585b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5813232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58132330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58132330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631eb585a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (1579 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562709668eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562709665e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056270966962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feab5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feab5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feab5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feab5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627095febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627095fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627095e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562709292e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562709292b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feab5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feab5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feab5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562709292a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1580 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, pt # | ... # `---data was truncated (10240/71947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572f3750eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572f374de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572f375162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2a1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2a1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2a1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2a1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572f36e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572f36e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572f36cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572f337ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572f337ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe2a1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2a1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2a1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572f337aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (1581 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr # | ... # `---data was truncated (10240/44315) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558ff7f9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ff7f9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ff7f9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77b551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ff7f33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ff7f33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ff7f188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ff7bc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ff7bc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77b551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ff7bc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (1582 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbc3cbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbc3cbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbc3cbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6e2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6e20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6e2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6e2031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbc3c53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbc3c53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbc3c388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbc38e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbc38e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6e2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6e20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6e20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbc38e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (1583 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (1584 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed516a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed516a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed516a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cf701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cf70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cf701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cf7003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed51639bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed51639a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed5161e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed512cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed512cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7cf7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cf70050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cf70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed512cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (1585 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c64b334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c64b331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c64b33562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4af4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4af4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4af4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4af4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c64b2cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c64b2caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c64b2af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c64af5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c64af5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4af4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4af4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4af4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c64af5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (1586 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fafc741eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fafc73ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fafc74262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1568933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f156898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1568933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f156891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fafc6d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fafc6d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fafc6bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fafc36be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fafc36bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f156891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f156891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f156891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fafc36ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (1587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a1bc1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a1bc19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a1bc1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1937133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f193718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1937133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f193711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a1bbb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a1bbb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a1bb978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a1b846e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a1b846b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f193711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f193711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f193711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a1b846a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (1588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602fc8efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602fc8ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602fc8f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a18333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a1838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a18333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a1831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602fc885bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602fc885a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602fc86a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602fc519e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602fc519b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a1831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a1831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a1831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602fc519a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (1589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/12652) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595bca86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595bca83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595bca8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4cc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4cc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4cc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4cc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595bca1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595bca1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595bca018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595bc6b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595bc6b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4cc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4cc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4cc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595bc6b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1590 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfm # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fbf9adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fbf9aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fbf9ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1212b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1212b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1212b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1212b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fbf943bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fbf943a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fbf9288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fbf5d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fbf5d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1212b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1212b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1212b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fbf5d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (1591 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c3c1d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c3c1d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c3c1d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0319933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f031998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0319933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f031991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c3c16ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c3c16ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c3c1538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c3be02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c3be02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f031991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f031991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f031991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c3be02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (1592 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600a3dd2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600a3dcfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600a3dd362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa73d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa73d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa73d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa73d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600a3d68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600a3d68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600a3d4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600a39fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600a39fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa73d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa73d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa73d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600a39fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (1593 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562031a6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562031a6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562031a7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dae71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562031a05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562031a05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620319ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562031699e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562031699b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0dae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dae71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562031699a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (1594 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558199cfdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558199cfae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558199cfe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd185649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd185649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd185631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558199c93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558199c93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558199c788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558199927e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558199927b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd185632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1856330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558199927a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (1595 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (1596 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (1597 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562643ab0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562643aade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562643ab162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3df733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3df78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3df733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3df71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562643a46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562643a46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562643a2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626436dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626436dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3df71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3df71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3df71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626436daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (1598 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055846c336eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055846c333e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055846c33762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f013f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f013f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f013f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f013f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055846c2ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055846c2cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055846c2b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055846bf60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055846bf60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f013f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f013f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f013f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055846bf60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (1599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ae435aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ae4357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ae435b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd011133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd01118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd011133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd01111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ae42f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ae42f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ae42d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ae3f84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ae3f84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd01111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd01111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd01111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ae3f84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (1600 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d5c4ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d5c4fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d5c50062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb041733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb04178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb041733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb04171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d5c495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d5c495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d5c47a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d5c129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d5c129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb04171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb04171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb04171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d5c129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (1601 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558135278eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558135275e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055813527962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd88a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd88a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd88a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd88a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055813520ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055813520ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581351f38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558134ea2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558134ea2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd88a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd88a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd88a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558134ea2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (1602 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be4eb1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be4eb1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be4eb1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13aa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13aa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13aa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13aa431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be4eab3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be4eab3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be4ea988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be4e747e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be4e747b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13aa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13aa4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13aa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be4e747a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (1603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsli # | ... # `---data was truncated (10240/14908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d82c1b3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d82c1b0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d82c1b462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43fbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d82c149bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d82c149a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d82c12e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d82bddde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d82bdddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43fbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d82bddda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (1604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/246606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a6d9cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a6d9cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a6d9ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab15049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab150a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab15049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab15031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a6d963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a6d963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a6d9488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a6d5f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a6d5f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab15032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab150330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab150330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a6d5f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (1605 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (1606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) % # | ... # `---data was truncated (10240/27994) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e39f4d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e39f4d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e39f4da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f850d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f850d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f850d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f850d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e39f46fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e39f46fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e39f4548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e39f103e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e39f103b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f850d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f850d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f850d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e39f103a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (1607 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a50a73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a50a70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a50a7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bb0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bb08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bb0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bb0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a50a09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a50a09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a509ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a5069de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a5069db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bb0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bb08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bb08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a5069da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (1608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (1609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (1610 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055759f6baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055759f6b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055759f6bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcd7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcd738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcd7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcd731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055759f650bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055759f650a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055759f6358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055759f2e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055759f2e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efcd731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcd731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcd731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055759f2e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (1611 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056106fdf4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056106fdf1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056106fdf562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b54d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b54d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b54d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b54d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056106fd8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056106fd8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056106fd6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056106fa1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056106fa1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b54d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b54d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b54d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056106fa1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (1612 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (1613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align # | ... # `---data was truncated (10240/14145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596734dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596734d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596734dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea76f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea76f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea76f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea76f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559673472bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559673472a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596734578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559673106e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559673106b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea76f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea76f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea76f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559673106a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (1614 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fe80c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fe80bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fe80c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feed6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feed66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feed6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feed6631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fe8057bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fe8057a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fe803c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fe7cebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fe7cebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feed6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feed66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feed66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fe7ceba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (1615 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (1616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056027fbcaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056027fbc7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056027fbcb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c0e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c0e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c0e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c0e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056027fb60bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056027fb60a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056027fb458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056027f7f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056027f7f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4c0e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c0e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c0e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056027f7f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (1617 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %3, ptr %__ret.i, align 8 # | %4 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %3, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055cf5e9daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf5e9d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf5e9db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0138f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0138f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0138f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0138f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf5e970bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf5e970a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf5e9558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf5e604e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf5e604b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0138f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0138f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0138f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf5e604a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (1618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d6bd0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d6bd08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d6bd0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde99449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde994a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde99449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde99431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d6bca1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d6bca1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d6bc868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d6b935e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d6b935b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde99432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde994330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde994330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d6b935a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (1619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (1620 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055997a7cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055997a7c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055997a7cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0508f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0508f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0508f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0508eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055997a761bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055997a761a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055997a7468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055997a3f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055997a3f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0508eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0508eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0508eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055997a3f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (1621 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3c6e28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3c6e25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3c6e2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a68c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a68ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a68c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a68c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3c6dbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3c6dbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3c6da38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3c6a52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3c6a52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a68c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a68c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a68c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3c6a52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (1622 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (1623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565414e47eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565414e44e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565414e4862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f740bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f740bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f740bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f740bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565414dddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565414ddda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565414dc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565414a71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565414a71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f740bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f740bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f740bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565414a71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (1624 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055758f2b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055758f2b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055758f2b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd8a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd8a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd8a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd8a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055758f24dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055758f24da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055758f2328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055758eee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055758eee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd8a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd8a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd8a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055758eee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (1625 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a65df6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a65df3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a65df762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1cfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1cfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1cfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1cfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a65d8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a65d8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a65d718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a65a20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a65a20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb1cfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1cfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1cfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a65a20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (1626 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm # | ... # `---data was truncated (10240/53200) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b4d32beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b4d328e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b4d32c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4f1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4f1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4f1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4f1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b4d2c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b4d2c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b4d2a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b4cf55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b4cf55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff4f1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4f1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4f1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b4cf55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (1627 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f6773ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f67739e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f6773d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f112121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11212725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f112121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1121203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f676d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f676d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f676b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f67366e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f67366b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1121204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11212050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11212050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f67366a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (1628 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556353864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556353861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055635386562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b1c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b1c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b1c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b1c203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563537fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563537faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563537df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055635348ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055635348eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b1c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b1c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b1c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055635348ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (1629 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e755f05eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e755f02e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e755f0662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa14249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa142a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa14249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa14231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e755e9bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e755e9ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e755e808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e755b2fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e755b2fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa14232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa142330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa142330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e755b2fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (1630 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b86672feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b86672ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b86673062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bbed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bbed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bbed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bbeced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8666c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8666c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8666aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b866359e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b866359b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8bbeceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bbecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bbecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b866359a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (1631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565127ad7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565127ad4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565127ad862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0227a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0227aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0227a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0227a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565127a6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565127a6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565127a528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565127701e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565127701b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0227a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0227a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0227a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565127701a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (1632 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056180cb70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056180cb6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056180cb7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad44f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad44f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad44f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad44f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056180cb06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056180cb06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056180caeb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056180c79ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056180c79ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad44f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad44f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad44f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056180c79aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (1633 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9f4794eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9f4791e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9f479562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09f9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09f958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09f9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09f951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9f472abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9f472aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9f470f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9f43bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9f43beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09f951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09f951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09f951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9f43bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (1634 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf4x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf4x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf4x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf4x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf4x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf4x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf2x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf2x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf2x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf2x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m1x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m1x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m1x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16m1x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16m1x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16m1x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16m1x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ec76a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ec76a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ec76a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aebd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ec763cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ec763ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ec76218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ec72d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ec72d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9aebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ec72d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (1635 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1d3b52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1d3b4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1d3b5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ee8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ee8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ee8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ee8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1d3ae8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1d3ae8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1d3acd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1d377ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1d377cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ee8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ee8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ee8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1d377ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (1636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, # | ... # `---data was truncated (10240/28346) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056474c030eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056474c02de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056474c03162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3e221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3e22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3e221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3e2203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056474bfc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056474bfc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056474bfab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056474bc5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056474bc5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3e2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3e22050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3e22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056474bc5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (1637 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/77054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bc317deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557bc317ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557bc317e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f066bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f066bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f066bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f066bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bc3113bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557bc3113a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557bc30f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557bc2da7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557bc2da7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f066bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f066bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f066bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bc2da7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1638 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tupl # | ... # `---data was truncated (10240/88444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ea5744eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ea5741e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ea574562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1038449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1038449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1038431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ea56dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ea56daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ea56bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ea536ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ea536eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1038432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10384330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ea536ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (1639 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d81885feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d81885ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d81886062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1f9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8187f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8187f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8187da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d818489e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d818489b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d818489a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (1640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2482d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2482d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2482d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67c7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67c7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67c7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67c7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d24826cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d24826ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2482518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d247f00e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d247f00b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67c7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67c7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67c7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d247f00a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (1641 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (1642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (1643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @orc_b_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @ctz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cpop_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctpop.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.orc.b.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctpop.i32(i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556996f36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556996f33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556996f3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556996eccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556996ecca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556996eb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556996b60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556996b60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556996b60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (1644 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619c04adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619c04aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619c04ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcc3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcc395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcc3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcc38ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619c0443bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619c0443a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619c04288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619c00d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619c00d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcc38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcc38ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcc38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619c00d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (1645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, a # | ... # `---data was truncated (10240/28358) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a8d8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555a8d8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555a8d8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ec2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ec298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ec2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ec291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a8d86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555a8d86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555a8d8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555a8d500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555a8d500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ec291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ec291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ec291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a8d500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (1646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64 # | ... # `---data was truncated (10240/97248) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d7cb0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d7cb0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d7cb1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fd4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fd4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fd4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fd4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d7caa5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d7caa5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d7ca8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d7c739e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d7c739b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fd4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fd4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fd4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d7c739a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (1647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eaa4d0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eaa4d0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eaa4d0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f959121bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95912725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f959121ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9591203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaa4ca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eaa4ca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eaa4c898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eaa4938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eaa4938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9591204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95912050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95912050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaa4938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (1648 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | # | ... # `---data was truncated (10240/17236) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556822ed0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556822ecde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556822ed162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff48d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff48d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff48d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff48d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556822e66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556822e66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556822e4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556822afae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556822afab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff48d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff48d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff48d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556822afaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (1649 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %v # | ... # `---data was truncated (10240/142327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f444c0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f444c0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f444c0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f417f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f417f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f417f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f417f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f444ba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f444ba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f444b888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f444837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f444837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f417f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f417f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f417f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f444837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (1650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (1651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055747961beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557479618e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055747961c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0d1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0d198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0d1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0d191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574795b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574795b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574795968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557479245e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557479245b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0d191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0d191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0d191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557479245a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (1652 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Fu # | ... # `---data was truncated (10240/68429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559814b46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559814b43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559814b4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f306481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30648725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f306481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3064803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559814adcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559814adca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559814ac18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559814770e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559814770b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3064804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30648050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30648050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559814770a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (1653 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c82be3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c82be39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c82be3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc76f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc76f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc76f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc76eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c82bdd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c82bdd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c82bdb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c82ba66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c82ba66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc76eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc76eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc76eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c82ba66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (1654 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc3dfbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc3dfb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc3dfbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b02449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b02449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b02431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc3df50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc3df50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc3df358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc3dbe4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc3dbe4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b02432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b024330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc3dbe4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (1655 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056447ee41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056447ee3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056447ee4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d21449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d214a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d21449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d21431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056447edd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056447edd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056447edbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056447ea6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056447ea6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d21432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d214330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d214330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056447ea6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (1656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055983bbc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055983bbc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055983bbc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc6ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc6ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc6ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc6aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055983bb5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055983bb5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055983bb438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055983b7f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055983b7f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc6aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc6aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc6aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055983b7f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (1657 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2586edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2586eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2586ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e4c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e4c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e4c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e4c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a258683bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a258683a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2586688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a258317e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a258317b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e4c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e4c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e4c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a258317a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (1658 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605e7a93eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605e7a90e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605e7a9462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f769bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f769bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f769bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f769baed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605e7a29bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605e7a29a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605e7a0e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605e76bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605e76bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f769baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f769baef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f769baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605e76bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (1659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (1660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (1661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (1662 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c71b849eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c71b846e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c71b84a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa033c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa033ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa033c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa033c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c71b7dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c71b7dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c71b7c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c71b473e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c71b473b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa033c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa033c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa033c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c71b473a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (1663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb5afc3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb5afc0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb5afc462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe869933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe86998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe869933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe86991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb5af59bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb5af59a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb5af3e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb5abede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb5abedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe86991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe86991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe86991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb5abeda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (1664 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9d6ad5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d9d6ad2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d9d6ad662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19b8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19b86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19b8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19b8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9d6a6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9d6a6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9d6a508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d9d66ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d9d66ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19b8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19b86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19b86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9d66ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (1665 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc21921eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc2191ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc2192262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf5e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf5e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf5e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf5e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc218b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc218b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc2189c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc2154be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc2154bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf5e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf5e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf5e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc2154ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (1666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffabe9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ffabe9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ffabe9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba89d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba89d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba89d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba89d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffabe33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ffabe33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ffabe188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ffabac7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ffabac7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba89d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba89d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba89d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffabac7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (1667 of 27910) ******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %w.addr = alloca float, align 4 # | store float %w, ptr %w.addr, align 4 # | %0 = load float, ptr %w.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %1, i32 0 # | %2 = load float, ptr %__p0.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1 # | %3 = load float, ptr %__p0.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2 # | %4 = load float, ptr %__p0.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %5 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | store <4 x float> %5, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 { # | entry: # | %V.addr = alloca <1 x double>, align 8 # | %__ret_379 = alloca <2 x double>, align 16 # | %__s0_379 = alloca <1 x double>, align 8 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | %tmp1 = alloca <2 x double>, align 16 # | store <1 x double> %V, ptr %V.addr, align 8 # | %0 = load <1 x double>, ptr %V.addr, align 8 # | store <1 x double> %0, ptr %__s0_379, align 8 # | %1 = load <1 x double>, ptr %__s0_379, align 8 # | store <1 x double> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer # | store <2 x double> %lane, ptr %ref.tmp, align 16 # | %4 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %4, ptr %__ret, align 16 # | %5 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %5, ptr %tmp, align 16 # | %6 = load <2 x double>, ptr %tmp, align 16 # | store <2 x double> %6, ptr %__ret_379, align 16 # | %7 = load <2 x double>, ptr %__ret_379, align 16 # | store <2 x double> %7, ptr %tmp1, align 16 # | %8 = load <2 x double>, ptr %tmp1, align 16 # | ret <2 x double> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %6 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %6, ptr %__ret, align 8 # | %7 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %7, ptr %tmp, align 8 # | %8 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3 # | %6 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4 # | %7 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5 # | %8 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6 # | %9 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %10 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %10, ptr %__ret, align 16 # | %11 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %11, ptr %tmp, align 16 # | %12 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %12 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005597bc40eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597bc40be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597bc40f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc77b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc77b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc77b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc77b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597bc3a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597bc3a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597bc3898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597bc038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597bc038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc77b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc77b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc77b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597bc038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (1668 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx # | ... # `---data was truncated (10240/75125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebcba81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebcba7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebcba8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd29b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd29b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd29b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd29b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebcba17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebcba17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebcb9fc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebcb6abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebcb6abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd29b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd29b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd29b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebcb6aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (1669 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/29319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fefd21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555fefd1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555fefd2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcae421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcae42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcae421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcae4203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fefcb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555fefcb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555fefc9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555fef94be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555fef94bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcae4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcae42050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcae42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fef94ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (1670 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056056cce4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056056cce1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056056cce562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6312049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63120a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6312049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6312031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056056cc7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056056cc7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056056cc5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056056c90ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056056c90eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6312032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63120330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63120330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056056c90ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (1671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f159038eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f159035e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f15903962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f991361bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99136725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f991361ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9913603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f158fcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f158fcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f158fb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f158c62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f158c62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9913604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99136050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99136050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f158c62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (1672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (1673 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608cd31deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608cd31ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608cd31e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc44d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc44d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc44d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc44d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608cd2b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005608cd2b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608cd2988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608ccf47e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608ccf47b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc44d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc44d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc44d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608ccf47a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (1674 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e48752eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e4874fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e4875362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0be7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0be718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0be7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0be711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e486e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e486e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e486cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e4837ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e4837cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0be711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0be711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0be711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e4837ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (1675 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync # | ... # `---data was truncated (10240/10618) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595fbf54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595fbf51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595fbf5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30a1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30a10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30a1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30a1031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595fbeeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595fbeeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595fbecf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595fbb7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595fbb7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f30a1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30a10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30a10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595fbb7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (1676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aa2cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558aa2cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558aa2cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aa2c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558aa2c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558aa2c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558aa2906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558aa2906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aa2906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (1677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e110715eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e110712e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e11071662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd771649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7716a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd771649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd771631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1106abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1106aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1106908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e11033fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e11033fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd771632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7716330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7716330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e11033fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-cde-vfp.c (1678 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 { # | entry: # | %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11) # | %1 = bitcast float %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %m.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = load i32, ptr %m.addr, align 4 # | %5 = bitcast i32 %4 to float # | %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5) # | %7 = bitcast float %6 to i32 # | ret i32 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 { # | entry: # | %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11) # | %1 = bitcast double %0 to i64 # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %m.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = load i64, ptr %m.addr, align 8 # | %5 = bitcast i64 %4 to double # | %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5) # | %7 = bitcast double %6 to i64 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5e7492eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5e748fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5e749362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44a0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44a0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44a0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44a0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5e7428bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5e7428a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5e740d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5e70bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5e70bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44a0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44a0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44a0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5e70bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (1679 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, # | ... # `---data was truncated (10240/211231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577c76e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577c76dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577c76e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f124ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f124ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124feed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577c7677bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577c7677a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577c765c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577c730be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577c730bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f124feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577c730ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (1680 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b395be5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b395be2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b395be662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2530b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2530b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2530b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2530b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b395b7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b395b7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b395b608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b39580fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b39580fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2530b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2530b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2530b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b39580fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (1681 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (1682 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605b7395eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605b7392e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605b739662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effd8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effd8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effd8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effd8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605b732bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605b732ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605b73108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605b6fbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605b6fbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effd8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effd8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effd8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605b6fbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (1683 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, al # | ... # `---data was truncated (10240/169925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2c9efeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2c9efbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2c9eff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9c0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9c0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9c0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9c0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2c9e94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2c9e94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2c9e798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2c9b28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2c9b28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9c0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9c0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9c0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2c9b28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (1684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055906bd56eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055906bd53e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055906bd5762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f212561bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21256725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f212561ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2125603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055906bcecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055906bceca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055906bcd18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055906b980e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055906b980b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2125604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21256050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21256050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055906b980a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1685 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ebd118eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ebd115e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ebd11962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bf4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bf4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bf4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bf4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ebd0aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ebd0aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ebd0938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ebcd42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ebcd42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bf4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bf4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bf4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ebcd42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (1686 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9ba032eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9ba02fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9ba03362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0b1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0b178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0b1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0b171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9b9fc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9b9fc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9b9fad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9b9c5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9b9c5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0b171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0b171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0b171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9b9c5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (1687 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056249170deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056249170ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056249170e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65e1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65e16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65e1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65e1631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624916a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624916a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624916888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562491337e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562491337b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65e1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65e16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65e16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562491337a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (1688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/12644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623b27c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623b27c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623b27c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cda133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cda18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cda133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cda11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623b275abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623b275aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623b273f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623b23eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623b23eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cda11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cda11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cda11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623b23eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (1689 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a386952eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a38694fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a38695362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05fd505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05fd55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05fd505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05fd4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3868e8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3868e8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3868cd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a38657ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a38657cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05fd4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05fd4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05fd4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38657ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (1690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/24990) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056280479ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562804799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056280479d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f668f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f668f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f668f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f668f231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562804732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562804732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628047178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628043c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628043c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f668f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f668f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f668f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628043c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (1691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (1692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598b6c1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598b6c19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598b6c1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1a5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598b6bb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598b6bb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598b6b978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598b6846e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598b6846b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598b6846a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (1693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f28ad10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f28ad0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f28ad1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bf5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bf538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bf5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bf531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f28aca6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f28aca6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f28ac8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f28a93ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f28a93ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bf531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bf531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bf531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f28a93aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (1694 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056100c9bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056100c9bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056100c9c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f037c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f037c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f037c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f037c6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056100c955bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056100c955a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056100c93a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056100c5e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056100c5e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f037c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f037c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f037c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056100c5e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (1695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (1696 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586cd4d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586cd4d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586cd4d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac31a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac31aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac31a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac31a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586cd46cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586cd46ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586cd4518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586cd100e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586cd100b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac31a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac31a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac31a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586cd100a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (1697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e6871eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e6871be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e6871f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f941ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f941ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f941ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f941ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e686b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e686b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e686998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e68348e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e68348b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f941ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f941ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f941ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e68348a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (1698 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a410a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a4109ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a410a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9436b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9436b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9436b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9436b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a41037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a41037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a4101c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a40ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a40ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9436b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9436b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9436b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a40ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (1699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e86667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e86664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e8666862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aee249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aee2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aee249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aee231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e865fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e865fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e865e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e86291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e86291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9aee232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aee2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aee2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e86291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (1700 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559eb9bbfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559eb9bbce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559eb9bc062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54e2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54e238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54e2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54e231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559eb9b55bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559eb9b55a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559eb9b3a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559eb97e9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559eb97e9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54e231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54e231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54e231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559eb97e9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (1701 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5e93b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b5e93b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b5e93b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74d5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74d50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74d5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74d5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5e934bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b5e934ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b5e93308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b5e8fdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b5e8fdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74d5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74d50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74d50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5e8fdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (1702 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (1703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d85e53eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d85e50e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d85e5462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7778f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7778f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7778f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7778eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d85de9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d85de9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d85dce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d85a7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d85a7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7778eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7778eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7778eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d85a7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (1704 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (1705 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align # | ... # `---data was truncated (10240/97506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558fb2dd3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558fb2dd0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558fb2dd462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf9a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558fb2d69bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558fb2d69a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558fb2d4e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558fb29fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558fb29fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cf9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf9a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558fb29fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (1706 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055750c4b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055750c4b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055750c4b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f867b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f867b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f867b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f867b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055750c44bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055750c44ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055750c4308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055750c0dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055750c0dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f867b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f867b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f867b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055750c0dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (1707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (1708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555627062eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055562705fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055562706362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0cac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555626ff8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555626ff8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555626fdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555626c8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555626c8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0cac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555626c8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (1709 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565103f64eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565103f61e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565103f6562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff1f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff1f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff1f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff1f631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565103efabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565103efaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565103edf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565103b8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565103b8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff1f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff1f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff1f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565103b8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (1710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a38540eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a3853de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a3854162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce86133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce8618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce86133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce8611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a384d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a384d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a384bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a3816ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a3816ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce8611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce8611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce8611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a3816aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (1711 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d53704eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d53704be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d53704f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70c9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70c96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70c9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70c9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d536fe4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d536fe4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d536fc98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d536c78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d536c78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70c9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70c96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70c96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d536c78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (1712 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560daecb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560daecb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560daecb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc888e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc888ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc888e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc888e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560daec4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560daec4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560daec318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560dae8e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560dae8e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc888e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc888e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc888e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dae8e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (1713 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e474030eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e47402de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e47403162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f1bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f1bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f1bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f1bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e473fc6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e473fc6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e473fab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e473c5ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e473c5ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f1bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f1bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f1bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e473c5aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (1714 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (1715 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/62752) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596b406deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596b406ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596b406e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43a7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43a738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43a7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43a731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596b4003bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596b4003a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596b3fe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596b3c97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596b3c97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43a731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43a731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43a731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596b3c97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (1716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, # | ... # `---data was truncated (10240/288103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559af2a79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559af2a76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559af2a7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5ec249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5ec2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5ec249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5ec231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559af2a0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559af2a0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559af29f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559af26a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559af26a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5ec232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5ec2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5ec2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559af26a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (1717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596d1d1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596d1d17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596d1d1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3238c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3238ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3238c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3238c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596d1cb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596d1cb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596d1c958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596d1944e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596d1944b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3238c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3238c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3238c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596d1944a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (1718 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (1719 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4e54efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4e54ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4e54f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b1021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b102725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b1021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b10203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4e5485bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4e5485a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4e546a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4e5119e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4e5119b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b10204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b102050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b102050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4e5119a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (1720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056481b407eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056481b404e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056481b40862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde98f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde98f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde98f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde98f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056481b39dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056481b39da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056481b3828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056481b031e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056481b031b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde98f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde98f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde98f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056481b031a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (1721 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/24982) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0ab814eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0ab811e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0ab81562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5851849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5851849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5851831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0ab7aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0ab7aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0ab78f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0ab43ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0ab43eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5851832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58518330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0ab43ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (1722 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583543a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055835439de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583543a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e02e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e02ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e02e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e02e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558354336bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558354336a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055835431b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558353fcae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558353fcab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e02e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e02e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e02e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558353fcaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (1723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d965c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d965c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d965c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b57333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b5738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b57333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b5731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d9655abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d9655aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d9653f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d961eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d961eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b5731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b5731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b5731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d961eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (1724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eb44c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eb44c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eb44c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8d7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8d775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8d7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8d76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eb445abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eb445aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eb443f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564eb40eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564eb40eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8d76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8d76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8d76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eb40eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (1725 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055894aedfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055894aedce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055894aee062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe64ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe64ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe64ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe64ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055894ae75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055894ae75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055894ae5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055894ab09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055894ab09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe64ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe64ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe64ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055894ab09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (1726 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret # | ... # `---data was truncated (10240/25287) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056080c240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056080c23de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056080c24162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f829fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f829fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f829fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f829fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056080c1d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056080c1d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056080c1bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056080be6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056080be6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f829fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f829fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f829fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056080be6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (1727 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f60f136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f60f133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f60f13762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43f7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43f718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43f7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43f711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f60f0ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f60f0cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f60f0b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f60ed60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f60ed60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43f711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43f711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43f711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f60ed60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (1728 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596329b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596329afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596329b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcca7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcca70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcca7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcca7031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559632948bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559632948a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055963292d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596325dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596325dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcca7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcca70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcca70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596325dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (1729 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633ddadeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633ddadbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633ddadf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37e761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37e76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37e761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37e7603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633dda74bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633dda74a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633dda598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633dd708e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633dd708b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37e7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37e76050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37e76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633dd708a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (1730 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bfcac9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bfcac6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bfcaca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaba61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaba6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaba61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaba603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bfca5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bfca5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bfca448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bfc6f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bfc6f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaba604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaba6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaba6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bfc6f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1731 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = # | ... # `---data was truncated (10240/154509) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0e8b83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0e8b80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0e8b8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e7c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e7c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e7c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e7c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0e8b19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0e8b19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0e8afe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0e87ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0e87adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e7c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e7c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e7c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0e87ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (1732 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600fe4b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600fe4afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600fe4b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9925449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99254a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9925449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9925431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600fe448bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600fe448a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600fe42d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600fe0dce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600fe0dcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9925432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99254330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99254330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600fe0dca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (1733 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c51a8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c51a8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c51a8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c2ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c2eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c2ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c2ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c51a23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c51a23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c51a088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c516b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c516b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c2ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c2ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c2ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c516b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (1734 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (1735 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vsqrth_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %vsqrt, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %c.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %__s2 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load half, ptr %__s0, align 2 # | %4 = load half, ptr %__s1, align 2 # | %5 = load half, ptr %__s2, align 2 # | %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %6, ptr %ref.tmp, align 2 # | %7 = load half, ptr %ref.tmp, align 2 # | store half %7, ptr %__ret, align 2 # | %8 = load half, ptr %__ret, align 2 # | store half %8, ptr %tmp, align 2 # | %9 = load half, ptr %tmp, align 2 # | ret half %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # | #0 0x000055b04b833eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b04b830e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b04b83462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08ae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08ae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08ae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08ae71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b04b7c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b04b7c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b04b7ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b04b45de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b04b45db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08ae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08ae71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08ae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b04b45da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (1736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (1737 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056178adf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056178adefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056178adf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b2b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b2b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b2b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b2b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056178ad88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056178ad88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056178ad6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056178aa1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056178aa1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b2b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b2b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b2b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056178aa1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (1738 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1739 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align # | ... # `---data was truncated (10240/26572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557898cfaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557898cf7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557898cfb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde14f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde14f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde14f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde14f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557898c90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557898c90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557898c758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557898924e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557898924b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde14f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde14f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde14f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557898924a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (1740 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (1741 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu # | ... # `---data was truncated (10240/156765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f673f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f673f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f673fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e10333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e1038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e10333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e1031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6738fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f6738fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f673748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f67023e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f67023b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e1031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e1031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e1031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f67023a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (1742 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569bedb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005569bedb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005569bedb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba32305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba3235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba32305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba322ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569bed4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005569bed4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569bed2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005569be9dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005569be9deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba322eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba322ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba322ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569be9dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (1743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (1744 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc1da5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc1da5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc1da5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f026dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f026dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f026dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f026dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc1d9f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc1d9f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc1d9d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc1d688e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc1d688b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f026dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f026dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f026dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc1d688a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (1745 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eb9859eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eb9856e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eb985a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7026449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7026449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7026431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eb97efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eb97efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eb97d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564eb9483e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564eb9483b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7026432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eb9483a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (1746 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %v # | ... # `---data was truncated (10240/110062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559119c41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559119c3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559119c4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a16d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a16d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a16d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a16d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559119bd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559119bd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559119bbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055911986be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055911986bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a16d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a16d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a16d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055911986ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (1747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056292fb85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056292fb82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056292fb8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeb8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeb858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeb8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeb851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056292fb1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056292fb1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056292fb008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056292f7afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056292f7afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feeb851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeb851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeb851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056292f7afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (1748 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, # | ... # `---data was truncated (10240/30635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b21751eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b2174ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b2175262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b51b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b51b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b51b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b51b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b216e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b216e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b216cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b2137be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b2137bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b51b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b51b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b51b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b2137ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (1749 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <1 x double>, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> # | store <1 x double> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/20383) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fd0d36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fd0d33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fd0d3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c5741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c574725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c5741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c57403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fd0cccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fd0ccca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fd0cb18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fd0960e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fd0960b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c57404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c574050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c574050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fd0960a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (1750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (1751 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560db80feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560db80fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560db80ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6df9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6df9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6df9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6df9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560db8094bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560db8094a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560db80798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560db7d28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560db7d28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6df9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6df9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6df9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560db7d28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (1752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561970291eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056197028ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056197029262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37ce849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37ce8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37ce849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37ce831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561970227bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561970227a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056197020c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056196febbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056196febbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37ce832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37ce8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37ce8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056196febba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (1753 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559cbbf2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559cbbf29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559cbbf2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc60d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc60d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc60d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc60d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cbbec2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559cbbec2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559cbbea78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559cbbb56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559cbbb56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc60d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc60d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc60d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cbbb56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (1754 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = al # | ... # `---data was truncated (10240/40137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b405526eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b405523e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b40552762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca3e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca3e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca3e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca3e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4054bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4054bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4054a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b405150e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b405150b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca3e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca3e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca3e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b405150a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (1755 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623acbceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623acbcbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623acbcf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7d8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7d8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7d8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7d8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623acb64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623acb64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623acb498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623ac7f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623ac7f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7d8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7d8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7d8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623ac7f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (1756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1795b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1795b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1795b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dd1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dd18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dd1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dd1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c17954abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c17954aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c17952f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1791dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1791deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0dd1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dd18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dd18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1791dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (1757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4 # | ... # `---data was truncated (10240/96257) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a08195beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a081958e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a08195c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe54d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe54d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe54d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe54d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0818f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0818f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0818d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a081585e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a081585b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe54d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe54d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe54d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a081585a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (1758 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055faf55edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faf55eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faf55ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff02bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff02bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff02bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff02bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faf5583bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faf5583a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faf55688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055faf5217e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055faf5217b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff02bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff02bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff02bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faf5217a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (1759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc85bfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bc85bfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bc85bff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa43e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa43e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa43e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa43e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc85b94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bc85b94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bc85b798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bc85828e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bc85828b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa43e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa43e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa43e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc85828a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (1760 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbb0cc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbb0cbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbb0cc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c94f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c94f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c94f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c94f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbb0c57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbb0c57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbb0c3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbb08ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbb08ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c94f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c94f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c94f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbb08eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (1761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1e47eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1e47e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1e47ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb9f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb9f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb9f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb9f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1e4782bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1e4782a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1e47678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1e4416e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1e4416b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb9f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb9f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb9f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1e4416a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (1762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cf0ddceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556cf0dd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556cf0ddd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54b0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54b0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54b0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54b0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cf0d72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556cf0d72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556cf0d578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556cf0a06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556cf0a06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54b0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54b0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54b0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cf0a06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (1763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587a94f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587a94f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587a94f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5594849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55948a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5594849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5594831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587a948dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587a948da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587a94728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587a9121e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587a9121b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5594832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55948330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55948330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587a9121a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (1764 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647c090aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647c0907e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647c090b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc168049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1680a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc168049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc168031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647c08a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005647c08a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005647c08858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647c0534e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647c0534b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc168032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1680330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1680330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647c0534a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (1765 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643bc108eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643bc105e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643bc10962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe39a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe39a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe39a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe39a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643bc09ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643bc09ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643bc0838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643bbd32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643bbd32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe39a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe39a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe39a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643bbd32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (1766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (1767 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26710) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056111684beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561116848e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056111684c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ae1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ae1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ae1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ae1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611167e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611167e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611167c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561116475e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561116475b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ae1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ae1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ae1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561116475a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (1768 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d3a384eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d3a381e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d3a38562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3647533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f364758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3647533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f364751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d3a31abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d3a31aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d3a2ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d39faee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d39faeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f364751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f364751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f364751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d39faea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (1769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637dab66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637dab63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637dab6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c31933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c3198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c31933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c3191b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637daafcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637daafca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637daae18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637da790e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637da790b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c3191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c3191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c3191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637da790a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (1770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b392cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b392c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b392cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c9961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c996725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c9961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c99603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b39262bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b39262a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b392478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b38ef6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b38ef6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c99604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c996050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c996050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b38ef6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (1771 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562d20b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562d20aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562d20b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfd4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfd46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfd4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfd4631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562d2047bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562d2047a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562d202c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562d1cdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562d1cdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfd4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfd46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfd46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562d1cdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (1772 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i6 # | ... # `---data was truncated (10240/67158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a52d957eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a52d954e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a52d95862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd090933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd09098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd090933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd09091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a52d8edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a52d8eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a52d8d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a52d581e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a52d581b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd09091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd09091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd09091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a52d581a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (1773 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557be0fc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557be0fbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557be0fc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f89249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f892a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f89249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f89231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557be0f57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557be0f57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557be0f3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557be0bebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557be0bebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f89232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f892330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f892330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557be0beba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (1774 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (1775 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 # | ... # `---data was truncated (10240/35980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x00005616e222deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616e222ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616e222e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc9801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc980725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc9801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc98003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616e21c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616e21c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616e21a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616e1e57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616e1e57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc98004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc980050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc980050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616e1e57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (1776 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nou # | ... # `---data was truncated (10240/25034) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b9f094eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b9f091e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b9f09562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d8e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d8e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d8e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d8e231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b9f02abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b9f02aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b9f00f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b9ecbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b9ecbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0d8e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d8e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d8e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b9ecbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (1777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (1778 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d308b18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d308b15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d308b1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7abff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7abff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7abff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7abff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d308aaebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d308aaea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d308a938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d308742e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d308742b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7abff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7abff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7abff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d308742a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (1779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (1780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a398a18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a398a15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a398a1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81f0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81f055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81f0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81f04ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3989aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3989aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3989938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a398642e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a398642b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f81f04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81f04ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81f04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a398642a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (1781 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ce2d65eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ce2d62e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ce2d6662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce8a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce8a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce8a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce8a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ce2cfbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ce2cfba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ce2ce08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ce298fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ce298fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce8a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce8a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce8a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ce298fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (1782 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue # | ... # `---data was truncated (10240/81764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615bf640eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615bf63de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615bf64162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4092049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4092049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4092031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615bf5d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615bf5d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615bf5bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615bf26ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615bf26ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4092032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40920330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615bf26aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (1783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f100fa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f100fa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f100faa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3903b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3903b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3903b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3903b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f100f3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f100f3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f100f248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f100bd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f100bd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3903b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3903b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3903b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f100bd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (1784 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563baaff3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563baaff0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563baaff462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0bce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0bcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0bce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0bce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563baaf89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563baaf89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563baaf6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563baac1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563baac1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0bce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0bce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0bce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563baac1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (1785 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b83eaeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b83eabe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b83eaf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f673b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f673b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f673b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f673b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b83e44bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b83e44a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b83e298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b83ad8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b83ad8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f673b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f673b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f673b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b83ad8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (1786 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e2becdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e2becae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e2bece62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75e451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e2be63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e2be63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e2be488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e2baf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e2baf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f75e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75e451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e2baf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (1787 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7987a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7987a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7987a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cd7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cd7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cd7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cd7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d79873cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d79873ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7987218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7983d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7983d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cd7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cd7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cd7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7983d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (1788 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willre # | ... # `---data was truncated (10240/273697) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d07d469eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d07d466e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d07d46a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5e7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5e775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5e7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5e76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d07d3ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d07d3ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d07d3e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d07d093e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d07d093b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5e76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5e76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5e76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d07d093a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (1789 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/cx-complex-range-real.c (1790 of 27910) ******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %mul.rl = fmul float %a.real, %0 # | %mul.il = fmul float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.il, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul.rl = fmul float %.real, %0 # | %mul.il = fmul float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %mul.rl, ptr %.realp1, align 4 # | store float %mul.il, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %a.addr = alloca float, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul.rl = fmul float %0, %b.real # | %mul.ir = fmul float %0, %b.imag # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.ir, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = fdiv float %a.real, %0 # | %2 = fdiv float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %1, ptr %retval.realp, align 4 # | store float %2, ptr %retval.imagp, align 4 # | %3 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %2 = fdiv float %.real, %0 # | %3 = fdiv float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %2, ptr %.realp1, align 4 # | store float %3, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | store double %b, ptr %b.addr, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load double, ptr %a.imagp, align 8 # | %2 = load double, ptr %b.addr, align 8 # | %3 = fdiv double %a.real, %2 # | %4 = fdiv double %a.imag, %2 # | %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1 # | store double %3, ptr %retval.realp, align 8 # | store double %4, ptr %retval.imagp, align 8 # | %5 = load { double, double }, ptr %retval, align 8 # | ret { double, double } %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { double, double }, align 8 # | %a.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %1, align 8 # | store double %a, ptr %a.addr, align 8 # | %2 = load double, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | %b.real = load double, ptr %b.realp, align 8 # | %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | %b.imag = load double, ptr %b.imagp, align 8 # | %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2 # | %3 = extractvalue { double, double } %call, 0 # | %4 = extractvalue { double, double } %call, 1 # | %conv = fptrunc double %3 to float # | %conv1 = fptrunc double %4 to float # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %conv, ptr %retval.realp, align 4 # | store float %conv1, ptr %retval.imagp, align 4 # | %5 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %5 # | } # | # | declare { double, double } @__divdc3(double, double, double, double) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca double, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load double, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.real = load double, ptr %.realp, align 8 # | %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | %.imag = load double, ptr %.imagp, align 8 # | %2 = fdiv double %.real, %0 # | %3 = fdiv double %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | store double %2, ptr %.realp1, align 8 # | store double %3, ptr %.imagp2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 { # | entry: # | %retval = alloca { x86_fp80, x86_fp80 }, align 16 # | %b.addr = alloca x86_fp80, align 16 # | store x86_fp80 %b, ptr %b.addr, align 16 # | %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0 # | %a.real = load x86_fp80, ptr %a.realp, align 16 # | %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1 # | %a.imag = load x86_fp80, ptr %a.imagp, align 16 # | %0 = load x86_fp80, ptr %b.addr, align 16 # | %1 = fdiv x86_fp80 %a.real, %0 # | %2 = fdiv x86_fp80 %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1 # | store x86_fp80 %1, ptr %retval.realp, align 16 # | store x86_fp80 %2, ptr %retval.imagp, align 16 # | %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16 # | ret { x86_fp80, x86_fp80 } %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 { # | entry: # | %a.addr # | ... # `---data was truncated (10240/11567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000557282308eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557282305e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055728230962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff220d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff220d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff220d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff220d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055728229ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055728229ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572822838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557281f32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557281f32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff220d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff220d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff220d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557281f32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (1791 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (1792 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570a14a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570a149de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570a14a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2553333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f255338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2553333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f255331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570a1436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570a1436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570a141b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570a10cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570a10cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f255331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f255331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f255331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570a10caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (1793 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056362cab7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056362cab4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056362cab862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f215d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f215d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f215d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f215d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056362ca4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056362ca4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056362ca328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056362c6e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056362c6e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f215d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f215d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f215d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056362c6e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (1794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (1795 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056372b22deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056372b22ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056372b22e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa19a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa19a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa19a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa19a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056372b1c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056372b1c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056372b1a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056372ae57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056372ae57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa19a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa19a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa19a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056372ae57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (1796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056301ca30eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056301ca2de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056301ca3162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe610049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6100a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe610049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe610031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056301c9c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056301c9c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056301c9ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056301c65ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056301c65ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe610032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6100330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6100330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056301c65aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (1797 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test # | ... # `---data was truncated (10240/156773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0b10cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0b10c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0b10cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3eec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3eeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3eec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3eec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0b1061bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c0b1061a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0b10468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c0b0cf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c0b0cf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3eec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3eec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3eec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0b0cf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (1798 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f535f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f535f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f535f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27c0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27c038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27c0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27c031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f5358abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f5358aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f5356f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f5321ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f5321eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27c031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27c031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27c031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f5321ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (1799 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/32701) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622864bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005622864b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005622864bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5489c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5489c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5489c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5489c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562286451bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562286451a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622864368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622860e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622860e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5489c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5489c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5489c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622860e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (1800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fafabf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fafabf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fafabfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc13e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc13ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc13e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc13e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fafab8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fafab8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fafab748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fafa823e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fafa823b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc13e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc13e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc13e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fafa823a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (1801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/47720) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055910dfe6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055910dfe3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055910dfe762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ea6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ea6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ea6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ea6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055910df7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055910df7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055910df618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055910dc10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055910dc10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ea6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ea6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ea6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055910dc10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (1802 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ae5d35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ae5d32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ae5d3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6fe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6fe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6fe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6fe831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ae5ccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ae5ccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ae5cb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ae595fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ae595fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6fe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6fe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6fe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ae595fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (1803 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563781972eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056378196fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056378197362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7b611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563781908bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563781908a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637818ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056378159ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056378159cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa7b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7b611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056378159ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (1804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614f3273eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614f3270e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614f327462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa15de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa15dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa15de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa15de31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614f3209bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614f3209a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614f31ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614f2e9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614f2e9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa15de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa15de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa15de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614f2e9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (1805 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, # | ... # `---data was truncated (10240/20307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe99f6aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe99f67e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe99f6b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7e4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7e4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7e4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7e4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe99f00bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe99f00a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe99ee58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe99b94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe99b94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff7e4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7e4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7e4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe99b94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (1806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056409c623eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056409c620e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056409c62462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eaab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eaab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eaab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eaab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056409c5b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056409c5b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056409c59e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056409c24de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056409c24db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5eaab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eaab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eaab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056409c24da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (1807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587d0846eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005587d0843e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005587d084762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2bd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2bd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2bd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2bd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587d07dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587d07dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587d07c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005587d0470e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005587d0470b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2bd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2bd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2bd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587d0470a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (1808 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644d63c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644d63bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644d63c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f02a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f02a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f02a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f02a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644d6358bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644d6358a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644d633d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644d5fece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644d5fecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f02a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f02a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f02a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644d5feca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (1809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( p # | ... # `---data was truncated (10240/24606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a109b89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a109b86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a109b8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0e3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0e378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0e3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0e371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a109b1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a109b1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a109b048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1097b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1097b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0e371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0e371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0e371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1097b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (1810 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e203f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e203f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e203fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab88f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab88f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab88f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab88f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e2038fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e2038fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e203748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e20023e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e20023b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab88f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab88f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab88f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e20023a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (1811 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563125915eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563125912e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056312591662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78cb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78cb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78cb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78cb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631258abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631258aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631258908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056312553fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056312553fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78cb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78cb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78cb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056312553fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (1812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/78164) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c95101beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c951018e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c95101c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4375933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f437598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4375933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f437591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c950fb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c950fb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c950f968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c950c45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c950c45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f437591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f437591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f437591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c950c45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (1813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633c8c66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005633c8c63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005633c8c6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a67905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a6795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a67905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a678ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633c8bfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633c8bfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633c8be18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005633c8890e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005633c8890b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a678eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a678ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a678ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633c8890a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (1814 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f457d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f457d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f457d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe24ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe24eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe24ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe24ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f45769bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f45769a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f4574e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f453fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f453fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe24ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe24ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe24ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f453fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (1815 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (1816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562919868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562919865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056291986962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f29733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f2978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f29733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f2971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629197febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629197fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629197e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562919492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562919492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f2971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f2971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f2971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562919492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (1817 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607cd05feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607cd05ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607cd06062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c67449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c67449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c67431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607ccff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607ccff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607ccfda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607ccc89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607ccc89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c67432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c674330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607ccc89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (1818 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | % # | ... # `---data was truncated (10240/201226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f206296eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f206293e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f20629762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18f9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18f978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18f9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18f971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f20622cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f20622ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2062118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f205ec0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f205ec0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18f971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18f971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18f971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f205ec0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (1819 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626f84f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626f84f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626f84f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19fa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19fa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19fa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19fa831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626f8489bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626f8489a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626f846e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626f811de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626f811db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19fa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19fa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19fa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626f811da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (1820 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/11851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fbfc2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fbfc2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fbfc2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb94f41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb94f4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb94f41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb94f403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fbfbc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fbfbc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fbfba88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fbf857e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fbf857b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb94f404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb94f4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb94f4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fbf857a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (1821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e41cf2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e41cefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e41cf362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb09ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb09eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb09ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb09ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e41c88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e41c88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e41c6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e4191ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e4191cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb09ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb09ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb09ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e4191ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (1822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582556f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582556f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582556f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe032c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe032ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe032c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe032c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055825568abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055825568aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055825566f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055825531ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055825531eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe032c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe032c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe032c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055825531ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (1823 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce4b235eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce4b232e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce4b23662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2211849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22118a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2211849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2211831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce4b1cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce4b1cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce4b1b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce4ae5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce4ae5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2211832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22118330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22118330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce4ae5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eed61f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eed61f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eed61f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bdf305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bdf35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bdf305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bdf2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eed618cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eed618ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eed61718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eed5e20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eed5e20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bdf2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bdf2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bdf2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eed5e20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (1825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd4596eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd4596be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd4596f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59fbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59fbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59fbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59fbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd45904bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd45904a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd458e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd45598e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd45598b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59fbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59fbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59fbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd45598a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (1826 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e875f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e875eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e875f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ed2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ed2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ed2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ed2aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e87587bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e87587a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e8756c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e8721be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e8721bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ed2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ed2aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ed2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e8721ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (1827 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055874320deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055874320ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055874320e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f527c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f527c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f527c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f527c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587431a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587431a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587431888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558742e37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558742e37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f527c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f527c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f527c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558742e37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (1828 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f526fe2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f526fdfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f526fe362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28a1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28a1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28a1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28a1c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f526f78bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f526f78a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f526f5d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f526c0ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f526c0cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28a1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28a1c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28a1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f526c0ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (1829 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648a4866eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648a4863e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648a486762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f40d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f40d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f40d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f40d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648a47fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648a47fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648a47e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648a4490e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648a4490b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6f40d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f40d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f40d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648a4490a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (1830 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a1de44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a1de41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a1de4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa32ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa32ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa32ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa32aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a1dddabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a1dddaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a1ddbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a1da6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a1da6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa32aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa32aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa32aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a1da6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (1831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582e7b4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582e7b47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582e7b4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55f7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55f7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55f7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55f7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582e7ae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005582e7ae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582e7ac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582e7774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582e7774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55f7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55f7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55f7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582e7774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (1832 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.r # | ... # `---data was truncated (10240/53678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fddcc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fddcc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fddcca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bc2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bc28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bc2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bc2831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fddc5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fddc5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fddc448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fdd8f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fdd8f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5bc2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bc28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bc28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fdd8f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (1833 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | # | ... # `---data was truncated (10240/15969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b57460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b5745de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b5746162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c0f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c0f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c0f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c0f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b573f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b573f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b573db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b5708ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b5708ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c0f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c0f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c0f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b5708aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (1834 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9937a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c99379de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9937a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8166c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8166ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8166c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8166c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c993736bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c993736a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c99371b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9933cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9933cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8166c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8166c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8166c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9933caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (1835 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563835087eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563835084e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056383508862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd623d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd623d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd623d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd623d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056383501dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056383501da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638350028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563834cb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563834cb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd623d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd623d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd623d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563834cb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (1836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9904e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9904e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9904ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ff6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ff6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ff6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ff6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b99047fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b99047fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9904648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b990113e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b990113b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ff6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ff6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ff6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b990113a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (1837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i # | ... # `---data was truncated (10240/51295) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d727d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d727d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d727d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f232bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f232bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f232bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f232bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d7276cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d7276ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d727518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d72400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d72400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f232bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f232bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f232bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d72400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (1838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d64e19eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d64e16e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d64e1a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d6d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d64dafbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d64dafa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d64d948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d64a43e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d64a43b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d64a43a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (1839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f41020eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f41020be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f41020f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e1d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e1d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e1d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e1d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4101a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4101a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4101898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f40fe38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f40fe38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e1d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e1d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e1d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f40fe38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (1840 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0a5bf3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0a5bf0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0a5bf462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4590133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f459018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4590133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f459011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0a5b89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0a5b89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0a5b6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0a581de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0a581db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f459011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f459011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f459011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0a581da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (1841 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564007de6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564007de3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564007de762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca2d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca2d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca2d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca2d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564007d7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564007d7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564007d618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564007a10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564007a10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca2d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca2d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca2d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564007a10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (1842 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614bf8f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614bf8f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614bf8f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c95a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c95a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c95a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c95a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614bf88ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614bf88ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614bf8738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614bf522e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614bf522b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c95a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c95a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c95a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614bf522a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (1843 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556fc8b1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556fc8aee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556fc8b262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1ee933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1ee98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1ee933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1ee91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556fc847bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556fc847a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556fc82c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556fc4dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556fc4dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1ee91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1ee91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1ee91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556fc4dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (1844 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596cfad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596cfad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596cfada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f41133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f4118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f41133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f4111b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596cfa6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596cfa6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596cfa548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596cf703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596cf703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f4111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f4111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f4111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596cf703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (1845 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056484c8d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056484c8d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056484c8d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96f761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96f76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96f761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96f7603507 abort ./stdlib/abort.c:85:3 # | #7 0x000056484c86cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056484c86ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056484c8518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056484c500e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056484c500b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f96f7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96f76050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96f76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056484c500a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (1846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load p # | ... # `---data was truncated (10240/28353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f921f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f921f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f921f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff034133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff03418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff034133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff03411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f9218dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f9218da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f921728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f91e21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f91e21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff03411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff03411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff03411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f91e21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (1847 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i # | ... # `---data was truncated (10240/120468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055986b443eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055986b440e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055986b44462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fc4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fc4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fc4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fc4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055986b3d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055986b3d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055986b3be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055986b06de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055986b06db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8fc4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fc4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fc4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055986b06da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1848 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca targe # | ... # `---data was truncated (10240/53556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056352be68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056352be65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056352be6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47c6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47c698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47c6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47c691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056352bdfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056352bdfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056352bde38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056352ba92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056352ba92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47c691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47c691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47c691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056352ba92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (1849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561eb505eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561eb502e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561eb50662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e10249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e102a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e10249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e10231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561eb49bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005561eb49ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561eb4808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561eb12fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561eb12fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e10232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e102330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e102330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561eb12fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1850 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.add # | ... # `---data was truncated (10240/86739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4d6ea5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d4d6ea2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d4d6ea662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff55a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff55a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff55a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff55a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4d6e3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d4d6e3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4d6e208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4d6acfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4d6acfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff55a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff55a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff55a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4d6acfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (1851 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx # | ... # `---data was truncated (10240/78682) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d79540eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d7953de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d7954162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1f7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1f7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1f7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1f7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d794d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d794d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d794bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d7916ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d7916ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1f7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1f7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1f7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d7916aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (1852 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = ca # | ... # `---data was truncated (10240/67474) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f43587eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f43584e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f4358862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6fa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6fa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6fa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6fa031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f4351dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f4351da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f435028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f431b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f431b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6fa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6fa0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6fa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f431b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (1853 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (1854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (1855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc17e58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc17e55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc17e5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3665533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f366558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3665533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f366551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc17deebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc17deea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc17dd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc17a82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc17a82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f366551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f366551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f366551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc17a82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (1856 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c51393eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c51390e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c5139462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cfd105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cfd15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cfd105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cfd0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c51329bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c51329a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c5130e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c50fbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c50fbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2cfd0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cfd0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cfd0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c50fbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (1857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557288825eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557288822e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055728882662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff96ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff96baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff96ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff96ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572887bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572887bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572887a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055728844fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055728844fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff96ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff96ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff96ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055728844fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1858 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (1859 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, %1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (1860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556581d5deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556581d5ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556581d5e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47dfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47dfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47dfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47dfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556581cf3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556581cf3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556581cd88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556581987e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556581987b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47dfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47dfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47dfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556581987a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (1861 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/135345) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560b815beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560b8158e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560b815c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd335133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd33518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd335133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd33511b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560b80f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560b80f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560b80d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560b7d85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560b7d85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd33511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd33511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd33511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560b7d85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (1863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc07ad9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dc07ad6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dc07ada62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf8e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf8e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf8e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf8e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc07a6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dc07a6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dc07a548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dc07703e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dc07703b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf8e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf8e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf8e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc07703a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (1864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/18595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617cc50ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617cc509e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617cc50d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90f7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90f7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90f7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90f7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617cc4a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617cc4a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617cc4878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617cc136e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617cc136b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90f7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90f7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90f7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617cc136a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (1865 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0aea3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0aea39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0aea3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e78449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e78449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e78431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0ae9d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0ae9d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0ae9b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0ae666e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0ae666b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e78432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e784330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0ae666a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (1866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cee3fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563cee3f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563cee3fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa70e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa70e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa70e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa70e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cee391bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563cee391a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563cee3768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563cee025e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563cee025b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa70e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa70e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa70e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cee025a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (1867 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556354507eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556354504e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055635450862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6217b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6217b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6217b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6217b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055635449dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055635449da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563544828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556354131e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556354131b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6217b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6217b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6217b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556354131a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (1868 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595f187feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595f187ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595f188062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d6f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d6f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d6f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d6f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595f1815bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595f1815a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595f17fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595f14a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595f14a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d6f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d6f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d6f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595f14a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (1869 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d44140eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d4413de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d4414162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9df8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9df858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9df8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9df851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d440d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d440d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d440bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d43d6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d43d6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9df851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9df851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9df851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d43d6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (1870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c7485ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c74859e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c7485d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3185733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f318578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3185733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f318571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c747f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c747f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c747d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c74486e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c74486b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f318571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f318571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f318571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c74486a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056197d530eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056197d52de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056197d53162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c75333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c7538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c75333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c7531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056197d4c6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056197d4c6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056197d4ab8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056197d15ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056197d15ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9c7531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c7531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c7531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056197d15aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (1872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4 # | ... # `---data was truncated (10240/25575) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ef7eceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ef7ecbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ef7ecf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcecee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fceceea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcecee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcecee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ef7e64bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ef7e64a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ef7e498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ef7af8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ef7af8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcecee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcecee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcecee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ef7af8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (1873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a54c8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a54c8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a54c8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ae3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ae338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ae3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ae331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a54c24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a54c24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a54c098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a548b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a548b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ae331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ae331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ae331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a548b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (1874 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5d79dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a5d79dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a5d79e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d15905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d1595c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d15905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d158ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5d7975bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a5d7975a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a5d795a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a5d7609e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a5d7609b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d158eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d158ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d158ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5d7609a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (1875 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb4fdbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb4fdb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb4fdbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7392a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7392aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7392a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7392a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb4fd51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb4fd51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb4fd368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb4f9e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb4f9e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7392a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7392a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7392a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb4f9e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (1876 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556660f58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556660f55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556660f5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0b6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0b6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0b6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0b6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556660eeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556660eeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556660ed38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556660b82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556660b82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0b6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0b6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0b6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556660b82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (1877 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559da5896eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559da5893e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559da589762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e92d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e92d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e92d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e92d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559da582cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559da582ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559da58118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559da54c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559da54c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e92d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e92d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e92d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559da54c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (1878 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b99d58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b99d55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b99d5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30aa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30aa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30aa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30aa231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b99ceebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b99ceea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b99cd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b99982e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b99982b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f30aa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30aa2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30aa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b99982a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (1879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055718f041eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055718f03ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055718f04262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f74933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f7498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f74933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f7491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055718efd7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055718efd7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055718efbc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055718ec6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055718ec6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f7491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f7491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f7491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055718ec6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (1880 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | %1 = fpext bfloat %0 to float # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | %1 = fptrunc float %0 to bfloat # | ret bfloat %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f690f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f690eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f690f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c21333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c2138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c21333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c2131b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f69087bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f69087a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f6906c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f68d1be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f68d1bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c2131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c2131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c2131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f68d1ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (1881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564eb7fe5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564eb7fe2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564eb7fe662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb9dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb9dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb9dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb9dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564eb7f7bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564eb7f7ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564eb7f608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564eb7c0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564eb7c0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb9dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb9dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb9dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564eb7c0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (1882 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (1883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bdd69ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558bdd699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558bdd69d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2491f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2491f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2491f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2491f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bdd632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558bdd632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558bdd6178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bdd2c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bdd2c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2491f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2491f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2491f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bdd2c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (1884 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63b44feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c63b44ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c63b45062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93a471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63b3e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c63b3e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c63b3ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c63b079e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c63b079b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93a471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63b079a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (1885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bbc10eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555bbc10be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555bbc10f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89ce449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89ce4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89ce449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89ce431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bbc0a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555bbc0a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555bbc0898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555bbbd38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555bbbd38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f89ce432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89ce4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89ce4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bbbd38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (1886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ee8946eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ee8943e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ee894762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5256933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f525698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5256933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f525691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ee88dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ee88dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ee88c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ee8570e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ee8570b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f525691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f525691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f525691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ee8570a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (1887 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7c6dc1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7c6dbee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7c6dc262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa2e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa2e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa2e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa2e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7c6d57bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7c6d57a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7c6d3c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7c69ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7c69ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa2e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa2e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa2e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7c69eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (1888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055596ecafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055596ecace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055596ecb062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd537e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd537ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd537e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd537e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055596ec45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055596ec45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055596ec2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055596e8d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055596e8d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd537e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd537e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd537e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055596e8d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (1889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a285c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a285c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a285ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f95733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f9578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f95733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f9571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a2855fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a2855fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a285448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a281f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a281f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f9571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f9571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f9571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a281f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (1890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055873621beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558736218e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055873621c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdef0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdef0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdef0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdef0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587361b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587361b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587361968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558735e45e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558735e45b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdef0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdef0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdef0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558735e45a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (1891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm # | ... # `---data was truncated (10240/35597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593ccea0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593cce9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593ccea162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8856705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f885675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8856705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88566ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593cce36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593cce36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593cce1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593ccacae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593ccacab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88566eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88566ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88566ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593ccacaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (1892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf4236feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cf4236ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cf4237062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb12831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf42305bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cf42305a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cf422ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cf41f99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cf41f99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb128330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf41f99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (1893 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd1c01feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd1c01ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd1c02062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0d8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0d818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0d8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0d811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd1bfb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd1bfb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd1bf9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd1bc49e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd1bc49b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc0d811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0d811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0d811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd1bc49a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (1894 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055780a6cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055780a6cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055780a6ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83faf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83faf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83faf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83faf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055780a663bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055780a663a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055780a6488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055780a2f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055780a2f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83faf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83faf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83faf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055780a2f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (1895 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ae7fa9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ae7fa6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ae7faa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc08bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc08bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc08bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc08bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ae7f3fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ae7f3fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ae7f248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ae7bd3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ae7bd3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc08bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc08bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc08bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ae7bd3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (1896 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556980f46eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556980f43e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556980f4762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fded8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fded835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fded8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fded82ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556980edcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556980edca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556980ec18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556980b70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556980b70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fded82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fded82ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fded82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556980b70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (1897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055781d55eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055781d55be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055781d55f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b25733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b2578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b25733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b2571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055781d4f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055781d4f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055781d4d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055781d188e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055781d188b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b2571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b2571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b2571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055781d188a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (1898 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1ca596eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1ca593e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1ca59762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72a8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72a82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72a8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72a8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1ca52cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1ca52ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1ca5118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1ca1c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1ca1c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f72a8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72a82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72a82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1ca1c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (1899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056047085feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056047085ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056047086062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ef1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ef1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ef1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ef1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604707f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604707f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604707da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560470489e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560470489b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ef1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ef1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ef1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560470489a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1900 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (1901 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562900386eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562900383e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056290038762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4a3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4a338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4a3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4a331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056290031cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056290031ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629003018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628fffb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628fffb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4a331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4a331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4a331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628fffb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (1902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(< # | ... # `---data was truncated (10240/119297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fc3b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fc3b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fc3b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8338533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f833858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8338533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f833851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fc3ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fc3ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fc3a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fc3749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fc3749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f833851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f833851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f833851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fc3749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (1903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555911c10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555911c0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555911c1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc677849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6778a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc677849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc677831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555911ba6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555911ba6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555911b8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055591183ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055591183ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc677832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6778330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6778330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055591183aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (1904 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd8c980eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd8c97de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd8c98162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f867c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f867c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f867c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f867c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd8c916bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd8c916a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd8c8fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd8c5aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd8c5aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f867c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f867c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f867c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd8c5aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (1905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64im(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.aes64im(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ds(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64im(i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dc487aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557dc4877e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557dc487b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f057be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f057bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f057be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f057be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dc4810bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557dc4810a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557dc47f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557dc44a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557dc44a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f057be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f057be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f057be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dc44a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (1906 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | # | ... # `---data was truncated (10240/26460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c3fd2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c3fd29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c3fd2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0a9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0a918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0a9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0a911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c3fcc2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c3fcc2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c3fca78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c3f956e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c3f956b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0a911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0a911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0a911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c3f956a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (1907 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5d326aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5d3267e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5d326b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb599733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb59978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb599733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb59971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5d3200bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5d3200a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5d31e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5d2e94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5d2e94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb59971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb59971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb59971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5d2e94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (1908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab710dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab710dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab710e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98d0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98d08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98d0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98d0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab71075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab71075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab7105a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab70d09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab70d09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f98d0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98d08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98d08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab70d09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (1909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4ae89feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4ae89ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4ae8a062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37e1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37e1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37e1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37e1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4ae835bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4ae835a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4ae81a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4ae4c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4ae4c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37e1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37e1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37e1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4ae4c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (1910 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558deee90eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558deee8de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558deee9162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf27333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf2738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf27333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf2731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558deee26bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558deee26a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558deee0b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558deeabae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558deeabab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf2731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf2731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf2731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558deeabaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: Modules/pr93497.cppm (1911 of 27910) ******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 3 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.Thing = type { i32 } # | %struct.C = type { i32 } # | %struct.NonConstexprDtor = type { i32 } # | # | $needed = comdat any # | # | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4 # | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4 # | @_ZW3mod11ConstantPtr = external global ptr, align 8 # | @_ZW3mod16NonConstantValue = external global %struct.C, align 4 # | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4 # | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }] # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z3usev() #0 { # | entry: # | %t1 = alloca %struct.Thing, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | declare noundef i32 @_Z7consumei(i32 noundef) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use2v() #0 { # | entry: # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %0 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0) # | ret i32 %call # | } # | # | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use3v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ptr = alloca ptr, align 8 # | %agg.tmp = alloca %struct.C, align 4 # | %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8 # | store ptr %0, ptr %Ptr, align 8 # | %1 = load ptr, ptr %Ptr, align 8 # | %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0 # | %2 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %2, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %3 = load ptr, ptr %Ptr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %4 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr i32 @needed() #0 comdat { # | entry: # | %call = call noundef i32 @_Z7consumei(i32 noundef 43) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use4v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ref = alloca %struct.C, align 4 # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false) # | %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0 # | %0 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %1 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use5v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %V = alloca %struct.NonConstexprDtor, align 4 # | %cleanup.dest.slot = alloca i32, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %1 = load i32, ptr %raw1, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %1) # | store i32 %call, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | if.end: ; preds = %entry # | %call2 = call i32 @needed() # | store i32 %call2, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | cleanup: ; preds = %if.end, %if.then # | call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5 # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind # | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3 # | # | declare void @_ZGIW3mod() # | # | ; Function Attrs: noinline nounwind # | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" { # | entry: # | call void @_ZGIW3mod() # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #5 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # | #0 0x00005598ebf28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598ebf25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598ebf2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecef031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598ebebebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598ebebea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598ebea38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598ebb52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598ebb52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecef0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598ebb52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (1912 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c303a00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3039fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c303a0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b19933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b1998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b19933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b1991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c303996bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c303996a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c30397b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c30362ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c30362ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b1991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b1991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b1991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c30362aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (1913 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | s # | ... # `---data was truncated (10240/69534) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556757406eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556757403e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055675740762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb60eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb60eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb60eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb60eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055675739cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055675739ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005567573818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556757030e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556757030b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb60eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb60eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb60eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556757030a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (1914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e51951aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e519517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e51951b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0109849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01098a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0109849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0109831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5194b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5194b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5194958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e519144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e519144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0109832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01098330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01098330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e519144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (1915 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637f1f8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637f1f8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637f1f9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa332f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa332f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa332f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa332f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637f1f25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637f1f25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637f1f0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637f1bb9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637f1bb9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa332f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa332f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa332f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637f1bb9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (1916 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055731bbd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055731bbd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055731bbda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3cf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055731bb6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055731bb6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055731bb548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055731b803e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055731b803b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa3cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055731b803a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (1917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e12050eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e1204de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e1205162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22eb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22eb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22eb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22eb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e11fe6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e11fe6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e11fcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e11c7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e11c7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22eb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22eb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22eb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e11c7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (1918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (1919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d4953beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d49538e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d4953c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbf101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbf10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbf101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbf1003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d494d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d494d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d494b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d49165e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d49165b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbf1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbf10050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbf10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d49165a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (1920 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557a4ba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557a4ba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557a4ba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f642b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f642b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f642b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f642b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557a4b3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557a4b3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557a4b208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557a47cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557a47cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f642b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f642b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f642b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557a47cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (1921 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604d0fd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005604d0fd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005604d0fda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25a2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25a26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25a2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25a2631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604d0f6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604d0f6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604d0f548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604d0c03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604d0c03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25a2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25a26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25a26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604d0c03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (1922 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4f8cfceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4f8cf9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4f8cfd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa06dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa06dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa06dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa06dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4f8c92bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4f8c92a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4f8c778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4f8926e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4f8926b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa06dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa06dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa06dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4f8926a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (1923 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b65638aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b656387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b65638b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f049fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f049fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f049fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f049fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b656320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b656320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6563058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b655fb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b655fb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f049fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f049fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f049fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b655fb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (1924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloc # | ... # `---data was truncated (10240/27533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca4060deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca4060ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca4060e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44f3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44f395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44f3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44f38ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca405a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca405a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca405888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca40237e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca40237b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44f38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44f38ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44f38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca40237a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (1925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612801a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612801a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612801a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ab3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ab358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ab3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ab351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056128013dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056128013da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612801228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056127fdd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056127fdd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ab351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ab351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ab351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056127fdd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (1926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a641d27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a641d24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a641d2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09e6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09e678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09e6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09e671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a641cbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a641cbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a641ca28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a641951e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a641951b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09e671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09e671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09e671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a641951a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (1927 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = or <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = or <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = or <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = or <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32 # | ... # `---data was truncated (10240/10897) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc407a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc407a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc407a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcd5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcd52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcd5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcd5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc4073abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc4073aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc4071f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc403cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc403ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcd5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcd52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcd52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc403cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (1928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557153c4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557153c4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557153c4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82f4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82f478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82f4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82f471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557153be3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557153be3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557153bc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557153877e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557153877b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82f471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82f471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82f471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557153877a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (1929 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd1f029eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd1f026e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd1f02a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf0a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf0a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf0a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf0a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd1efbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd1efbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd1efa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd1ec53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd1ec53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf0a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf0a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf0a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd1ec53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (1930 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588d2601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588d25fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588d260262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe310649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3106a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe310649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe310631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588d2597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588d2597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588d257c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588d222be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588d222bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe310632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3106330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3106330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588d222ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (1931 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (1932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/273705) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c771236eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c771233e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c77123762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c16505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c1655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c16505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c164ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7711ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c7711cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7711b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c770e60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c770e60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c164eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c164ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c164ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c770e60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (1933 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 % # | ... # `---data was truncated (10240/20326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576c115eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576c115be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576c115f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1299849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1299849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1299831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576c10f4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576c10f4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576c10d98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576c0d88e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576c0d88b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1299832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12998330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576c0d88a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (1934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (1935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056079d482eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056079d47fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056079d48362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f23f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f23f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f23f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f23eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056079d418bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056079d418a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056079d3fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056079d0ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056079d0acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f23eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f23eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f23eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056079d0aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (1936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b3a143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b3a140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b3a14462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd557249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5572a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd557249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd557231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b3a0d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b3a0d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b3a0be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b39d6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b39d6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd557232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5572330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5572330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b39d6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (1937 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbff880eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbff87de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbff88162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb26821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2682725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb26821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb268203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbff816bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbff816a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbff7fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbff4aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbff4aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb268204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2682050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2682050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbff4aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (1938 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3) # | %5 = and <8 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3) # | %5 = and <4 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3) # | %5 = and <2 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3) # | %5 = and <16 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = xor i16 %0, -1 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = load <8 x half>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = load <4 x float>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <2 x i64>, ptr %a.addr, align 8 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | %5 = load <2 x i64>, ptr %b.addr, align 8 # | %6 = bitcast <2 x i64> %5 to <4 x i32> # | %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6 # | %8 = bitcast <4 x i32> %7 to <2 x i64> # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, ali # | ... # `---data was truncated (10240/13928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055647da75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055647da72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055647da7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61d9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61d918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61d9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61d911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055647da0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055647da0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055647d9f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055647d69fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055647d69fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61d911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61d911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61d911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055647d69fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (1939 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (1940 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586d41cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005586d41c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005586d41cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e4ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e4ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e4ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e4ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586d4162bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005586d4162a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586d41478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005586d3df6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005586d3df6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e4ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e4ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e4ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586d3df6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (1941 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e58f7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e58f7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e58f7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6e7231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e58f13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e58f13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e58ef88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e58ba7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e58ba7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6e72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e58ba7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (1942 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/26996) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c04aa83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c04aa80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c04aa8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8756449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8756449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8756431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c04aa19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c04aa19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c04a9fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c04a6ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c04a6adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8756432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87564330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c04a6ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (1943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv # | ... # `---data was truncated (10240/75133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b06c966eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b06c963e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b06c96762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5ba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5ba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5ba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5ba71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b06c8fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b06c8fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b06c8e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b06c590e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b06c590b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5ba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5ba71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5ba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b06c590a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (1944 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_ran # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8b3c78eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8b3c75e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8b3c7962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f131e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f131e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f131e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f131e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8b3c0ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8b3c0ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8b3bf38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8b38a2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8b38a2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f131e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f131e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f131e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8b38a2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (1945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630ac808eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630ac805e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630ac80962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c1f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c1f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c1f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c1f803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630ac79ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630ac79ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630ac7838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630ac432e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630ac432b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c1f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c1f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c1f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630ac432a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (1946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/126428) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e30223ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e302239e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e30223d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee1b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee1b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee1b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee1b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3021d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3021d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3021b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e301e66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e301e66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee1b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee1b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee1b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e301e66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (1947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4005cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4005cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4005ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5113533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f511358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5113533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f511351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a400563bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a400563a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4005488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4001f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4001f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f511351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f511351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f511351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4001f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (1948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c0fa67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c0fa64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c0fa6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d9f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d9f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d9f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d9f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c0f9fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c0f9fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c0f9e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c0f691e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c0f691b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d9f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d9f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d9f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c0f691a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (1949 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d062af6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d062af3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d062af762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb97f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb97f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb97f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb97f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d062a8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d062a8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d062a718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d062720e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d062720b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb97f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb97f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb97f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d062720a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (1950 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f44594feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f44594ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f44595062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f806ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f806ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f806ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f806ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4458e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4458e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4458ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f445579e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f445579b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f806ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f806ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f806ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f445579a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (1951 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (1952 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056356edb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056356edb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056356edb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc237f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc237f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc237f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc237f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056356ed4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056356ed4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056356ed338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056356e9e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056356e9e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc237f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc237f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc237f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056356e9e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (1953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (1954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/63510) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564aa31d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564aa31cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564aa31d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7030d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7030d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7030d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7030d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564aa3167bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564aa3167a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564aa314c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564aa2dfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564aa2dfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7030d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7030d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7030d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564aa2dfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (1955 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 # | ... # `---data was truncated (10240/27063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583a18a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583a18a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583a18a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04a9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04a9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04a9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04a9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583a183dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583a183da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583a18228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583a14d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583a14d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04a9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04a9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04a9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583a14d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (1956 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556483fbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556483fb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556483fbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73f9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556483f52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556483f52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556483f378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556483be6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556483be6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556483be6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (1957 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (1958 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vaddh = fadd half %2, %3 # | store half %vaddh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vsubh = fsub half %2, %3 # | store half %vsubh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmulh = fmul half %2, %3 # | store half %vmulh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vdivh = fdiv half %2, %3 # | store half %vdivh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3) # | store half %vmax, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3) # | store half %vmaxnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3) # | store half %vmin, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3) # | store half %vminnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabsh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vabs = call half @llvm.fabs.f16(half %1) # | store half %vabs, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.fabs.f16(half) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = all # | ... # `---data was truncated (10240/27802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f971933eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f971930e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f97193462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3a4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3a48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3a4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3a4831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9718c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9718c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9718ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f97155de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f97155db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3a4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3a48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3a48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f97155da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (1959 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align # | ... # `---data was truncated (10240/102872) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d6ff41eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d6ff3ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d6ff4262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a33c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a33c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a33c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a33c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d6fed7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d6fed7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d6febc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d6fb6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d6fb6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a33c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a33c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a33c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d6fb6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (1960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (1961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (1962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056035e5aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056035e5abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056035e5af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4913049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49130a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4913049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4913031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056035e544bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056035e544a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056035e5298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056035e1d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056035e1d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4913032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49130330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49130330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056035e1d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (1963 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560971c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560971bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560971c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dff849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dff8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dff849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dff831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556097157bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556097157a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055609713c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556096debe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556096debb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dff832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dff8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dff8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556096deba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (1964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d260f04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d260f01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d260f0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f8df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f8df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f8df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f8df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d260e9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d260e9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d260e7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d260b2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d260b2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f8df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f8df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f8df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d260b2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (1965 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (1966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4d0a36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f4d0a33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4d0a3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62af849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62af8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62af849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62af831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4d09ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f4d09cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f4d09b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f4d0660e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f4d0660b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62af832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62af8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62af8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4d0660a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (1967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3a12cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f3a12cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f3a12d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8da1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8da178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8da1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8da171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3a1265bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f3a1265a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f3a124a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f3a0ef9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f3a0ef9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8da171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8da171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8da171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3a0ef9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (1968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d1ea2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d1ea2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d1ea2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9db533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9db58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9db533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9db51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d1e9c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d1e9c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d1e9a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d1e658e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d1e658b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9db51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9db51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9db51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d1e658a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (1969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056128fbd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056128fbd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056128fbd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe295a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe295aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe295a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe295a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056128fb6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056128fb6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056128fb4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056128f7fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056128f7feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe295a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe295a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe295a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056128f7fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (1970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561df636feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561df636ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561df637062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f75d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f75d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f75d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f75d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561df6305bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561df6305a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561df62ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561df5f99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561df5f99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f75d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f75d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f75d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561df5f99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (1971 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (1972 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1d99a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1d99a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1d99a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e41e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e41ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e41e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e41e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1d993ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1d993ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1d99238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1d95d2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1d95d2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e41e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e41e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e41e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1d95d2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (1973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560241877eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560241874e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056024187862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9a5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9a52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9a5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9a5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056024180dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056024180da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602417f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602414a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602414a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9a5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9a52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9a52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602414a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (1974 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576c5ad2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576c5acfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576c5ad362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76e7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76e778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76e7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76e771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576c5a68bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576c5a68a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576c5a4d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576c56fce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576c56fcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76e771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76e771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76e771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576c56fca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (1975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff. # | ... # `---data was truncated (10240/78156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae7feeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae7fee7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae7feeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9775a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9775aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9775a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9775a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae7fe80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae7fe80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae7fe658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae7fb14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae7fb14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9775a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9775a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9775a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae7fb14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (1976 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f934c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f934c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f934c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f109d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f109d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f109d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f109d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f93459bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f93459a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f9343e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f930ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f930edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f109d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f109d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f109d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f930eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (1977 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d52e80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d52e7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d52e8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb52d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb52d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb52d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb52ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d52e16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d52e16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d52dfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d52aaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d52aaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb52ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb52cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb52cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d52aaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (1978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz # | ... # `---data was truncated (10240/58675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055885ecb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055885ecb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055885ecb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6759849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67598a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6759849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6759831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055885ec49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055885ec49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055885ec2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055885e8dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055885e8ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6759832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67598330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67598330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055885e8dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1979 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564030892eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056403088fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056403089362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc93bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc93bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc93bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc93bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564030828bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564030828a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056403080d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640304bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640304bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc93bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc93bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc93bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640304bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (1980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571e7216eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571e7213e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571e721762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38a021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38a02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38a021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38a0203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571e71acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571e71aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571e71918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571e6e40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571e6e40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38a0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38a02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38a02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571e6e40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (1981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617c39f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617c39efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617c39f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9c4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9c4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9c4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9c4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617c3988bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617c3988a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617c396d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617c361ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617c361cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd9c4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9c4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9c4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617c361ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (1982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, a # | ... # `---data was truncated (10240/29450) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577ee4a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577ee4a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577ee4a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1459b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1459b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1459b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1459b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577ee43dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005577ee43da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005577ee4228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005577ee0d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005577ee0d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1459b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1459b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1459b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577ee0d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (1983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (1984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (1985 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564933f63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564933f60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564933f6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbee6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbee6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbee6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbee6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564933ef9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564933ef9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564933ede8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564933b8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564933b8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbee6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbee6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbee6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564933b8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (1986 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055989ab02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055989aaffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055989ab0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdeff61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdeff6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdeff61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdeff603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055989aa98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055989aa98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055989aa7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055989a72ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055989a72cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdeff604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdeff6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdeff6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055989a72ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (1987 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b80c6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b80c6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b80c7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06f5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06f5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06f5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06f5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b80c05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b80c05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b80bea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b80899e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b80899b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f06f5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06f5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06f5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b80899a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (1988 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | defin # | ... # `---data was truncated (10240/13035) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c400a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c4009de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c400a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6ab733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6ab78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6ab733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6ab71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c40036bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c40036a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c4001b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c3fccae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c3fccab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6ab71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6ab71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6ab71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c3fccaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (1989 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eef35beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561eef358e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561eef35c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c30649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c306a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c30649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c30631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eef2f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561eef2f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561eef2d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561eeef85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561eeef85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c30632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c306330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c306330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561eeef85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (1990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"Sma # | ... # `---data was truncated (10240/10293) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ec4dc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ec4dc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ec4dc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f791f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f791f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f791f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f791f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ec4d5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ec4d5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ec4d428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ec49f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ec49f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f791f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f791f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f791f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ec49f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (1991 of 27910) ******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | @con_unify_unimap_p1 = global ptr null, align 8 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @con_unify_unimap_q1() #0 { # | entry: # | %p.addr.i = alloca ptr, align 8 # | %q.addr.i = alloca ptr, align 8 # | %size.addr.i = alloca i64, align 8 # | %0 = load ptr, ptr @con_unify_unimap_p1, align 8 # | store ptr %0, ptr %p.addr.i, align 8 # | store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8 # | store i64 4, ptr %size.addr.i, align 8 # | %1 = load ptr, ptr %p.addr.i, align 8 # | %2 = load ptr, ptr %q.addr.i, align 8 # | %3 = load i64, ptr %size.addr.i, align 8 # | %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2 # | ret i32 %call.i # | } # | # | ; Function Attrs: alwaysinline nobuiltin nounwind # | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #2 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # | #0 0x0000563294701eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632946fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056329470262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d61933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d61933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563294697bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563294697a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056329467c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056329432be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056329432bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d6191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056329432ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-cde-gpr.c (1992 of 27910) ******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 { # | entry: # | %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 { # | entry: # | %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567) # | %1 = extractvalue { i32, i32 } %0, 1 # | %2 = zext i32 %1 to i64 # | %3 = shl i64 %2, 32 # | %4 = extractvalue { i32, i32 } %0, 0 # | %5 = zext i32 %4 to i64 # | %6 = or i64 %3, %5 # | ret i64 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33) # | %2 = extractvalue { i32, i32 } %1, 1 # | %3 = zext i32 %2 to i64 # | %4 = shl i64 %3, 32 # | %5 = extractvalue { i32, i32 } %1, 0 # | %6 = zext i32 %5 to i64 # | %7 = or i64 %4, %6 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = load i32, ptr %m.addr, align 4 # | %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3) # | %3 = extractvalue { i32, i32 } %2, 1 # | %4 = zext i32 %3 to i64 # | %5 = shl i64 %4, 32 # | %6 = extractvalue { i32, i32 } %2, 0 # | %7 = zext i32 %6 to i64 # | %8 = or i64 %5, %7 # | ret i64 %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = load i32, ptr %m.addr, align 4 # | %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ef565beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ef5658e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ef565c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f426c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f426c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f426c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f426c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ef55f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ef55f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ef55d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ef5285e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ef5285b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f426c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f426c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f426c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ef5285a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (1993 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 # | ... # `---data was truncated (10240/11237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639e6084eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639e6081e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639e608562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9746c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9746ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9746c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9746c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639e601abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639e601aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639e5fff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639e5caee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639e5caeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9746c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9746c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9746c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639e5caea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (1994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (1995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d747beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d747bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d747bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa06ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa06aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa06ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa06ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d74754bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d74754a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d747398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d743e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d743e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa06ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa06ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa06ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d743e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (1996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; # | ... # `---data was truncated (10240/14699) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555afc1eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555afc1be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555afc1f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde41249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde41249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde41231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555afbb4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555afbb4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555afb998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555af848e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555af848b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fde41232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde412330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555af848a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (1997 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563668b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563668ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563668b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52bb449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52bb4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52bb449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52bb431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556366846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556366846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055636682b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563664dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563664dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52bb432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52bb4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52bb4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563664daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (1998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055adf4a06eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055adf4a03e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055adf4a0762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0a2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0a2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0a2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0a2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055adf499cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055adf499ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055adf49818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055adf4630e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055adf4630b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0a2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0a2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0a2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055adf4630a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (1999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9b537feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9b537ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9b538062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8470b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8470b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8470b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8470b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9b5315bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9b5315a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9b52fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9b4fa9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9b4fa9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8470b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8470b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8470b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9b4fa9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (2000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb774a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cb774a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cb774a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd802f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd802f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd802f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd802f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb7743abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cb7743aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cb7741f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cb770cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cb770ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd802f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd802f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd802f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb770cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (2001 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6da04ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6da049e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6da04d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9418d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9418d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9418d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9418d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6d9fe2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6d9fe2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6d9fc78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6d9c76e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6d9c76b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9418d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9418d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9418d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6d9c76a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (2002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560412d74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560412d71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560412d7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82e921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82e92725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82e921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82e9203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560412d0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560412d0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560412cef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056041299ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056041299eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82e9204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82e92050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82e92050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056041299ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (2003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056190bf25eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056190bf22e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056190bf2662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3645849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36458a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3645849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3645831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056190bebbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056190bebba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056190bea08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056190bb4fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056190bb4fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3645832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36458330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36458330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056190bb4fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (2004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsa # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ffb321eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ffb31ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ffb32262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47b0d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47b0d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47b0d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47b0ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ffb2b7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ffb2b7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ffb29c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ffaf4be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ffaf4bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47b0ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47b0cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47b0cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ffaf4ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (2005 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/92362) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9e3549eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9e3546e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9e354a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4348b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4348b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4348b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4348b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9e34dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9e34dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9e34c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9e3173e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9e3173b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4348b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4348b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4348b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9e3173a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (2006 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055714ddc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055714ddc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055714ddc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4bde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4bdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4bde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4bde31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055714dd5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055714dd5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055714dd438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055714d9f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055714d9f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4bde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4bde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4bde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055714d9f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (2007 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056554c460eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056554c45de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056554c46162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f603e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f603e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f603e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f603e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056554c3f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056554c3f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056554c3db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056554c08ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056554c08ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f603e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f603e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f603e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056554c08aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (2008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556209fbaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556209fb7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556209fbb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf52933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf5298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf52933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf5291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556209f50bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556209f50a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556209f358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556209be4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556209be4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf5291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf5291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf5291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556209be4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (2009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056484528deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056484528ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056484528e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ebdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ebdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ebdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ebdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564845223bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564845223a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648452088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564844eb7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564844eb7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3ebdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ebdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ebdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564844eb7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (2010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (2011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c38c2dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c38c2d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c38c2dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee53a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee53aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee53a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee53a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c38c271bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c38c271a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c38c2568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c38bf05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c38bf05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fee53a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee53a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee53a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c38bf05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (2012 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628f82f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628f82f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628f82f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dd7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dd72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dd7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dd7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628f828ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628f828ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628f82738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628f7f22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628f7f22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8dd7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dd72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dd72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628f7f22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (2013 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627e46cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627e46cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627e46d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff073849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff073849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff073831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627e4665bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627e4665a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627e464a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627e42f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627e42f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff073832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0738330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627e42f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (2014 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp ule <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp ule <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp ule <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8e7dd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d8e7dcee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d8e7dd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39d9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39d955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39d9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39d94ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8e7d67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8e7d67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8e7d4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d8e79fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d8e79fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39d94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39d94ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39d94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8e79fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (2015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstrid # | ... # `---data was truncated (10240/17118) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e1d11ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560e1d119e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560e1d11d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fa5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fa518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fa5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fa511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e1d0b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560e1d0b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560e1d0978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560e1cd46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560e1cd46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1fa511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fa511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fa511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e1cd46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (2016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (2017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d3260ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556d32609e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556d3260d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff351533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff35158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff351533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff35151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d325a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556d325a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556d325878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556d32236e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556d32236b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff35151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff35151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff35151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d32236a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (2018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %v # | ... # `---data was truncated (10240/86747) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2d9956eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2d9953e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2d995762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7efb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7efb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7efb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7efaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2d98ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2d98eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2d98d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2d9580e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2d9580b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7efaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7efaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7efaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2d9580a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (2019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv. # | ... # `---data was truncated (10240/16654) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559168067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559168064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055916806862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca7a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca7a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca7a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca7a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559167ffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559167ffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559167fe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559167c91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559167c91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca7a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca7a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca7a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559167c91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (2020 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # | #0 0x000055705a879eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055705a876e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055705a87a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef18ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055705a80fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055705a80fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055705a7f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055705a4a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055705a4a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbef18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef18ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055705a4a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (2021 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnda.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i) # | store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndp.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i) # | store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) # | store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %3, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x half> # | store <4 x half> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__ret.i3 = alloca <8 x half>, align 16 # | %__p0.addr.i.i = alloca <4 x float>, align 16 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 16 # | %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %5 = bitcast <16 x i8> %4 to <4 x float> # | %6 = fptrunc <4 x float> %5 to <4 x half> # | store <4 x half> %6, ptr %ref.tmp.i.i, align 8 # | %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %7, ptr %__ret.i.i, align 8 # | %8 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %2, ptr %__p0.addr.i1, align 8 # | store <4 x half> %8, ptr %__p1.addr.i2, align 8 # | %9 = load <4 x half>, ptr %__p0.addr.i1, align 8 # | %10 = load <4 x half>, ptr %__p1.addr.i2, align 8 # | %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i3, align 16 # | %11 = load <8 x half>, ptr %__ret.i3, align 16 # | store <8 x half> %11, ptr %__ret.i, align 16 # | %12 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fpext <4 x half> %2 to <4 x float> # | store <4 x float> %3, ptr %ref.tmp.i, align 16 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %4, ptr %__ret.i, align 16 # | %5 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__ret.i2 = alloca <4 x half>, align 8 # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x half>, ptr %__ret.i2, align 8 # | store <4 x half> %4, ptr %__p0.addr.i.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %7 = fpext <4 x half> %6 to <4 x float> # | store <4 x float> %7, ptr %ref.tmp.i.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %8, ptr %__ret.i.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i.i, align 16 # | store <4 x float> %9, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000555c19aeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c19ae7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c19aeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfed81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfed8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfed81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfed803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c19a80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c19a80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c19a658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c19714e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c19714b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfed804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfed8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfed8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c19714a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (2022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (2023 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (2024 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef %rs1, i # | ... # `---data was truncated (10240/14325) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056034ec1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056034ec1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056034ec2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d46333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d4638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d46333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d4631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056034ebb5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056034ebb5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056034eb9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056034e849e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056034e849b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d4631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d4631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d4631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056034e849a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (2025 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4f25eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4f25ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4f25ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f276cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f276cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f276cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f276cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4f2584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4f2584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4f25698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4f2218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4f2218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f276cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f276cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f276cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4f2218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (2026 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4e0650eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4e064de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4e065162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa38fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa38fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa38fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa38fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4e05e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4e05e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4e05cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4e027ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4e027ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa38fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa38fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa38fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4e027aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (2027 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570f0c38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570f0c35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570f0c3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b8641bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b864725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b8641ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b86403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570f0bcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570f0bcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570f0bb38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570f0862e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570f0862b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b86404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b864050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b864050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570f0862a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (2028 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (2029 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec8ed76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec8ed73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec8ed7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f417c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f417c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f417c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f417c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec8ed0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec8ed0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec8ecf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec8e9a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec8e9a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f417c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f417c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f417c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec8e9a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (2030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (2031 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd61934eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd61931e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd6193562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd492f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd492f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd492f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd492f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd618cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd618caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd618af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd6155ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd6155eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd492f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd492f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd492f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd6155ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mfp8.c (2032 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 { # | entry: # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 { # | entry: # | %mfp8.addr = alloca <1 x i8>, align 1 # | %f1n = alloca [10 x <1 x i8>], align 1 # | store <1 x i8> %mfp8, ptr %mfp8.addr, align 1 # | %0 = load <1 x i8>, ptr %mfp8.addr, align 1 # | %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | store <1 x i8> %0, ptr %arrayidx, align 1 # | %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | %1 = load <1 x i8>, ptr %arrayidx1, align 1 # | ret <1 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | ret <1 x i8> %mfp8ext # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | %v.addr = alloca <1 x i8>, align 1 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | store <1 x i8> %v, ptr %v.addr, align 1 # | %0 = load <1 x i8>, ptr %v.addr, align 1 # | %1 = load i32, ptr %i.addr, align 4 # | %2 = load <16 x i8>, ptr %x.addr, align 16 # | %3 = bitcast <1 x i8> %0 to i8 # | %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1 # | store <16 x i8> %vecins, ptr %x.addr, align 16 # | %4 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # | #0 0x0000562d91b6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d91b6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d91b7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb8e01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb8e0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb8e01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb8e003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d91b05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d91b05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d91aea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d91799e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d91799b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb8e004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb8e0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb8e0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d91799a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (2033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | s # | ... # `---data was truncated (10240/12680) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056133a358eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056133a355e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056133a35962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc8ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc8eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc8ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc8ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056133a2eebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056133a2eea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056133a2d38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561339f82e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561339f82b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc8ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc8ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc8ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561339f82a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (2034 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0cbbe8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b0cbbe5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b0cbbe962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b4d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0cbb7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b0cbb7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b0cbb638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0cb812e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0cb812b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b4d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0cb812a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (2035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/41659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b175c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b175c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b175c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6492249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64922a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6492249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6492231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b1755ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b1755ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b175438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b171f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b171f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6492232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64922330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64922330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b171f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (2036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec1889deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec1889ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec1889e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc49f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc49f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc49f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc49f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec18833bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec18833a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec188188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec184c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec184c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc49f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc49f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc49f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec184c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (2037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (2038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (2039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (2040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558af8ca3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558af8ca0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558af8ca462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73fd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558af8c39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558af8c39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558af8c1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558af88cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558af88cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f73fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558af88cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (2041 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634c4cd1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634c4ccee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634c4cd262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd10b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd10b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd10b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd10b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634c4c67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634c4c67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634c4c4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634c48fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634c48fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd10b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd10b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd10b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634c48fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (2042 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("ris # | ... # `---data was truncated (10240/26965) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac1ee7aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac1ee77e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac1ee7b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0962133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f096218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0962133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f096211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac1ee10bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac1ee10a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac1edf58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac1eaa4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac1eaa4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f096211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f096211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f096211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac1eaa4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (2043 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056099593ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560995939e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056099593d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8441c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8441ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8441c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8441c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609958d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609958d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609958b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560995566e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560995566b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8441c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8441c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8441c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560995566a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (2044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dce9189eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dce9186e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dce918a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff56b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff56b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dce911fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dce911fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dce91048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dce8db3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dce8db3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff56b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dce8db3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (2045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (2046 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c4d247eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c4d244e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c4d24862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9885133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f988518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9885133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f988511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c4d1ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c4d1dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c4d1c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c4ce71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c4ce71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f988511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f988511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f988511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c4ce71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (2047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function A # | ... # `---data was truncated (10240/68067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e75661ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e756619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e75661d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74d1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74d12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74d1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74d1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7565b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7565b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7565978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e756246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e756246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74d1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74d12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74d12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e756246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2048 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (2049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056090324beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560903248e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056090324c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a5f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a5f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a5f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a5f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609031e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609031e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609031c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560902e75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560902e75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a5f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a5f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a5f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560902e75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (2050 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fc8d9ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560fc8d99e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560fc8d9d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae96c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae96c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae96c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae96c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fc8d32bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560fc8d32a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560fc8d178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560fc89c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560fc89c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae96c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae96c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae96c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fc89c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (2051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc0e644eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc0e641e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc0e64562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d81b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d81b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d81b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d81b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc0e5dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc0e5daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc0e5bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc0e26ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc0e26eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d81b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d81b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d81b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc0e26ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (2052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.v # | ... # `---data was truncated (10240/53192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf8d6b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf8d6b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf8d6b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcaca305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcaca35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcaca305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcaca2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf8d64dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf8d64da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf8d6328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf8d2e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf8d2e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcaca2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcaca2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcaca2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf8d2e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (2053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2bbc0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a2bbc09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a2bbc0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36d2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36d2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36d2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36d2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2bbba2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a2bbba2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a2bbb878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a2bb836e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a2bb836b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f36d2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36d2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36d2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2bb836a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (2054 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | ret <8 x half> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 { # | entry: # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | ret <4 x float> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca half, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store half %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %3, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store float %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %3, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, # | ... # `---data was truncated (10240/17297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000557b921b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b921b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b921b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbbe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbbe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbbe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbbe91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b9214cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b9214ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b921318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b91de0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b91de0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcbbe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbbe91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbbe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b91de0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (2055 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579d890aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579d8907e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579d890b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6778b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6778b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6778b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6778b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579d88a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579d88a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579d88858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579d8534e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579d8534b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6778b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6778b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6778b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579d8534a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (2056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (2057 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %value.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576) # | %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1 # | store <2 x i64> %3, ptr %0, align 8 # | %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = load <4 x i32>, ptr %value.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2) # | store <4 x i32> %3, ptr %0, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4 # | # | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631e1081eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631e107ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631e108262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb51e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb51e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb51e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb51e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631e1017bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631e1017a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631e0ffc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631e0cabe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631e0cabb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb51e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb51e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb51e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631e0caba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (2058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558d2a94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558d2a91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558d2a9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0fff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0fff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0fff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0fff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558d2a2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558d2a2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558d2a0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558d26bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558d26beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0fff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0fff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0fff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558d26bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (2059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b55a9b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b55a9b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b55a9b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd30733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd3078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd30733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd3071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b55a94dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b55a94da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b55a9328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b55a5e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b55a5e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd3071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd3071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd3071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b55a5e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (2060 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, # | ... # `---data was truncated (10240/157475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625079cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005625079cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005625079d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa595305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa59535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa595305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5952ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562507965bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562507965a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056250794a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625075f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625075f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5952eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5952ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5952ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625075f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (2061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559627100eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596270fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055962710162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559627096bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559627096a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055962707b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559626d2ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559626d2ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9b671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559626d2aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (2062 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load < # | ... # `---data was truncated (10240/84810) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056374121eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056374121be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056374121f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4134133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f413418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4134133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f413411b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637411b4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637411b4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637411998b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563740e48e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563740e48b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f413411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f413411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f413411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563740e48a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (2063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f46c13ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f46c139e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f46c13d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa48b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa48b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa48b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa48b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f46c0d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f46c0d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f46c0b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f46bd66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f46bd66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa48b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa48b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa48b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f46bd66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (2064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ddbab4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ddbab1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ddbab562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f195c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f195c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f195c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f195c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ddba4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ddba4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ddba2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ddb6dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ddb6deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f195c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f195c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f195c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ddb6dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (2065 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %low.addr = alloca <4 x half>, align 8 # | %high.addr = alloca <4 x half>, align 8 # | store <4 x half> %low, ptr %low.addr, align 8 # | store <4 x half> %high, ptr %high.addr, align 8 # | %0 = load <4 x half>, ptr %low.addr, align 8 # | %1 = load <4 x half>, ptr %high.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 { # | entry: # | %__p0.addr. # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a5a326eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a5a323e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a5a32762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f544d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f544d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f544d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f544d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a5a2bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a5a2bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a5a2a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a59f50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a59f50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f544d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f544d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f544d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a59f50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (2066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (2067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (2068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (2069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573cb311eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005573cb30ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005573cb31262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97ecc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97ecca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97ecc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97ecc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573cb2a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005573cb2a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005573cb28c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005573caf3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005573caf3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f97ecc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97ecc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97ecc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573caf3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (2070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (2071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a029d0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a029d0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a029d0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f3cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f3cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f3cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f3cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a029ca3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a029ca3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a029c888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a029937e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a029937b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f3cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f3cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f3cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a029937a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (2072 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (2073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (2074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (2075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e46f453eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e46f450e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e46f45462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd382a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd382a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd382a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd382a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e46f3e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e46f3e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e46f3ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e46f07de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e46f07db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd382a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd382a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd382a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e46f07da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (2076 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fe6ecfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563fe6ecce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563fe6ed062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc07849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc07849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc07831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fe6e65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563fe6e65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563fe6e4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563fe6af9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563fe6af9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc07832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc078330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fe6af9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (2077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558879d2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558879d2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558879d2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3893649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38936a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3893649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3893631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558879cc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558879cc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558879ca88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558879957e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558879957b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3893632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38936330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38936330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558879957a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (2078 of 27910) ******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %class.Foo = type { i8 } # | %class.HasTrivialDestructor = type { i8 } # | %struct.Data = type { ptr } # | %struct.HasNonTrivialCopyConstructor = type { i8 } # | %struct.HasNonTrivialCopyConstructor2 = type { i8 } # | %struct.LargeWithCopyConstructor = type { [32 x i8] } # | %class.anon = type { i8 } # | # | $_Z12TemplateFuncIiET_S0_ = comdat any # | # | $_Z6Func10IiEii = comdat any # | # | $_Z6Func12IiET_S0_ = comdat any # | # | @pmf = global { i64, i64 } zeroinitializer, align 8 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 { # | entry: # | %retval = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %entry # | %1 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1) # | ret i32 %call # | # | 2: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | if.else: ; preds = %entry # | %3 = load i32, ptr %x.addr, align 4 # | %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3) # | ret i32 %call1 # | # | 4: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %4, %2 # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | declare noundef i32 @_Z3Bari(i32 noundef) #1 # | # | declare noundef i32 @_Z3Bazi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z3Bari(i32 noundef %0) # | %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call) # | ret i32 %call1 # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.Foo, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local void @_Z5Func5v() #0 { # | entry: # | musttail call void @_Z11ReturnsVoidv() # | ret void # | # | 0: ; No predecessors! # | ret void # | } # | # | declare void @_Z11ReturnsVoidv() #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.HasTrivialDestructor, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 { # | entry: # | %data.addr = alloca ptr, align 8 # | store ptr %data, ptr %data.addr, align 8 # | %0 = load ptr, ptr %data.addr, align 8 # | %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %fptr, align 8 # | %2 = load ptr, ptr %data.addr, align 8 # | %call = musttail call noundef i32 %1(ptr noundef %2) # | ret i32 %call # | # | 3: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat { # | entry: # | %.addr = alloca i32, align 4 # | store i32 %0, ptr %.addr, align 4 # | ret i32 5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | %t = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 { # | entry: # | %x.ad # | ... # `---data was truncated (10240/18685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # | #0 0x000055578165ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555781659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055578165d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5727b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5727b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5727b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5727b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557815f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557815f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557815d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555781286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555781286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5727b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5727b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5727b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555781286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (2079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603923a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005603923a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005603923a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4092c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4092ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4092c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4092c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056039233bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056039233ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603923208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560391fcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560391fcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4092c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4092c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4092c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560391fcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (2080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579a9a51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579a9a4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579a9a5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50ae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50ae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50ae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50ae71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579a99e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579a99e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579a99cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579a967be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579a967bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50ae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50ae71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50ae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579a967ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (2081 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dd1e2eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559dd1e2be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559dd1e2f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9409333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f940938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9409333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f940931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dd1dc4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559dd1dc4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559dd1da98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559dd1a58e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559dd1a58b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f940931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f940931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f940931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dd1a58a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056279cd76eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056279cd73e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056279cd7762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30d3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30d3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30d3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30d3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056279cd0cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056279cd0ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056279ccf18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056279c9a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056279c9a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f30d3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30d3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30d3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056279c9a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (2083 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (2084 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 # | ... # `---data was truncated (10240/39417) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562333ba0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562333b9de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562333ba162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e27249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e272a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e27249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e27231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562333b36bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562333b36a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562333b1b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623337cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623337cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e27232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e272330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e272330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623337caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (2085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e213a91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e213a8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e213a9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46f1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46f14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46f1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46f1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e213a27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e213a27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e213a0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2136bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2136bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46f1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46f14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46f14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2136bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (2086 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e75c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646e75c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646e75c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0d7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0d7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0d7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0d7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e7559bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646e7559a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646e753e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646e71ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646e71edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff0d7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0d7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0d7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e71eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (2087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8e393eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a8e393be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a8e393f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8e38d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a8e38d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8e38b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a8e3568e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a8e3568b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8e3568a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (2088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609581f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609581f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609581f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0631049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0631049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0631031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056095818bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056095818ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609581708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560957e1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560957e1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0631032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06310330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560957e1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (2089 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e476ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e476fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e4770062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8039249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80392a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8039249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8039231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e47695bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e47695a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e4767a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e47329e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e47329b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8039232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80392330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80392330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e47329a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (2090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9faf80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9faf7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9faf8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd04733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd0478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd04733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd0471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9faf16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9faf16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9faefb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9fabaae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9fabaab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd0471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd0471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd0471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9fabaaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (2091 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <4 x bfloat>, ptr %__promote, align 8 # | store <4 x bfloat> %1, ptr %__ret, align 8 # | %2 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %2, ptr %tmp, align 8 # | %3 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x bfloat>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %low.addr = alloca <4 x bfloat>, align 8 # | %high.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %low, ptr %low.addr, align 8 # | store <4 x bfloat> %high, ptr %high.addr, align 8 # | %0 = load <4 x bfloat>, ptr %low.addr, align 8 # | %1 = load <4 x bfloat>, ptr %high.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <4 x bfloat>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store bfloat %a, ptr %a.addr, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1, align 8 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x bfloat>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | store bfloat %a, ptr %a.addr, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1, align 16 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | ret <8 x bfloat> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055b26945aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b269457e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b26945b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95ea649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95ea6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95ea649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95ea631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2693f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2693f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2693d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b269084e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b269084b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f95ea632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95ea6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95ea6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b269084a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (2092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | ... # `---data was truncated (10240/78234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630b7ddbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630b7dd8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630b7ddc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15f761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15f76725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15f761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15f7603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630b7d71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630b7d71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630b7d568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630b7a05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630b7a05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f15f7604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15f76050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15f76050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630b7a05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-neon-vst.c (2093 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <4 x i16> # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x3_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0 # | store [3 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %4 = bitcast <8 x i8> %1 to <4 x i16> # | %5 = bitcast <8 x i8> %2 to <4 x i16> # | %6 = bitcast <8 x i8> %3 to <4 x i16> # | call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x4_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0 # | store [4 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3 # | %4 = load <8 x i8>, ptr %arrayidx6, align 8 # | %5 = bitcast <8 x i8> %1 to <4 x i16> # | %6 = bitcast <8 x i8> %2 to <4 x i16> # | %7 = bitcast <8 x i8> %3 to <4 x i16> # | %8 = bitcast <8 x i8> %4 to <4 x i16> # | call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float32x2x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <2 x float> # | %4 = bitcast <8 x i8> %2 to <2 x float> # | call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %s # | ... # `---data was truncated (10240/108866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056373c1d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056373c1d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056373c1d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27b0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27b06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27b0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27b0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056373c16dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056373c16da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056373c1528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056373be01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056373be01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f27b0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27b06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27b06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056373be01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578fb73aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578fb737e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578fb73b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f542ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f542ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f542ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f542ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578fb6d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578fb6d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578fb6b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578fb364e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578fb364b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f542ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f542ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f542ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578fb364a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (2095 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556751e2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556751e2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556751e2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a1d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a1d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a1d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a1d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556751dc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556751dc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556751da88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556751a57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556751a57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a1d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a1d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a1d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556751a57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (2096 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, pt # | ... # `---data was truncated (10240/79679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fca8245eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fca8242e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fca824662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c85a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c85aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c85a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c85a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fca81dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fca81dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fca81c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fca7e6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fca7e6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c85a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c85a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c85a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fca7e6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (2097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6df455eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6df452e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6df45662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12b0105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12b015c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12b0105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12b00ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6df3ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6df3eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6df3d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6df07fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6df07fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f12b00eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12b00ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12b00ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6df07fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (2098 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2c50cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2c50c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2c50cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffafc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffafc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffafc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffafc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2c5061bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2c5061a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2c50468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2c4cf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2c4cf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffafc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffafc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffafc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2c4cf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (2099 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloc # | ... # `---data was truncated (10240/122004) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000561ed4edbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ed4ed8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ed4edc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18b0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18b058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18b0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18b051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ed4e71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ed4e71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ed4e568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ed4b05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ed4b05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18b051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18b051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18b051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ed4b05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (2100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %m # | ... # `---data was truncated (10240/41661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557250677eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557250674e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055725067862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f306e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f306e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f306e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f306e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055725060dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055725060da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572505f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572502a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572502a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f306e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f306e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f306e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572502a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (2101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559703a69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559703a66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559703a6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f4d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f4d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f4d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f4d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597039ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597039ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597039e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559703693e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559703693b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f4d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f4d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f4d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559703693a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (2102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562961e0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562961dde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562961e162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8008b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8008b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8008b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8008b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556296176bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556296176a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055629615b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556295e0ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556295e0ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8008b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8008b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8008b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556295e0aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (2103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e3e051eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e3e04ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e3e05262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb980133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb98018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb980133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb98011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e3dfe7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e3dfe7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e3dfcc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e3dc7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e3dc7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb98011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb98011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb98011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e3dc7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (2104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = loa # | ... # `---data was truncated (10240/23447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9cc4b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9cc4b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9cc4ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ee8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ee86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ee8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ee8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9cc44fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9cc44fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9cc4348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9cc0e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9cc0e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ee8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ee86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ee86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9cc0e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (2105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (2106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (2107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | ... # `---data was truncated (10240/170489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fd2499eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562fd2496e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562fd249a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4de6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4de618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4de6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4de611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fd242fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562fd242fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562fd24148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562fd20c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562fd20c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4de611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4de611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4de611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fd20c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Fun # | ... # `---data was truncated (10240/40883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b9ddc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b9ddc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b9ddca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb6fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb6fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb6fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb6fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b9dd5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b9dd5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b9dd448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b9d9f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b9d9f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb6fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb6fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb6fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b9d9f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (2109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e1430eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e1430be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e1430f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9136849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91368a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9136849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9136831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e142a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e142a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e142898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e13f38e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e13f38b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9136832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91368330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91368330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e13f38a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (2110 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i) # | store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i) # | store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i) # | store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i) # | store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i) # | store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i) # | store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i) # | store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i) # | store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i) # | store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i) # | store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i) # | store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i) # | st # | ... # `---data was truncated (10240/16770) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562e8dc68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e8dc65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e8dc6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50f4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50f418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50f4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50f411b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e8dbfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e8dbfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e8dbe38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e8d892e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e8d892b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50f411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50f411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50f411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e8d892a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (2111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605f6d7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605f6d7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605f6d7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8179249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81792a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8179249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8179231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605f6d13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605f6d13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605f6cf88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605f69a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605f69a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8179232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81792330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81792330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605f69a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (2112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5eddfeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5eddfbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5eddff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d88a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d88aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d88a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d88a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5edd94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5edd94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5edd798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5eda28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5eda28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d88a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d88a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d88a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5eda28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (2113 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/13255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e578e98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e578e95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e578e9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fa2905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fa295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fa2905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fa28ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e578e2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e578e2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e578e138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e578ac2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e578ac2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fa28eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fa28ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fa28ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e578ac2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (2115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, al # | ... # `---data was truncated (10240/223137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa9e9c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa9e9c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa9e9c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a06449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a06449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a06431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa9e95ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa9e95ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa9e9438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa9e5f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa9e5f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a06432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a064330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa9e5f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (2116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define d # | ... # `---data was truncated (10240/25350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055592b6f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055592b6efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055592b6f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f007a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f007a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f007a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f007a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055592b688bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055592b688a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055592b66d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055592b31ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055592b31cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f007a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f007a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f007a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055592b31ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (2117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nx # | ... # `---data was truncated (10240/83629) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cff5e11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cff5e0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cff5e1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5282905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f528295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5282905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52828ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff5da7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cff5da7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cff5d8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cff5a3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cff5a3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52828eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52828ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52828ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff5a3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (2118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639c709ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005639c7099e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005639c709d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba03649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba036a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba03649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba03631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639c7032bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005639c7032a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005639c70178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005639c6cc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005639c6cc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba03632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba036330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba036330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639c6cc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (2119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a9c0d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a9c0cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a9c0d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd197649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1976a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd197649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd197631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a9c067bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a9c067a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a9c04c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a9bcfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a9bcfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd197632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1976330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1976330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a9bcfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (2120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564191c04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564191c01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564191c0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9d8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9d818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9d8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9d811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564191b9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564191b9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564191b7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056419182ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056419182eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9d811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9d811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9d811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056419182ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (2121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d45373eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d45370e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d4537462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1dc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1dc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1dc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1dc631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d45309bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d45309a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d452ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d44f9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d44f9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1dc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1dc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1dc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d44f9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (2122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594f02daeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594f02d7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594f02db62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb58d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb58d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb58d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb58d231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594f0270bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594f0270a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594f02558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594eff04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594eff04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb58d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb58d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb58d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594eff04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (2123 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f690555eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f690552e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f69055662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6844a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6844aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6844a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6844a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6904ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6904eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6904d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f69017fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f69017fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6844a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6844a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6844a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f69017fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (2124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dcdb89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555dcdb86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555dcdb8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b0101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b010725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b0101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b01003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dcdb1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555dcdb1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555dcdb048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555dcd7b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555dcd7b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b01004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b010050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b010050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dcd7b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (2125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/15211) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c6a668eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c6a665e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c6a66962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41b3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41b3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41b3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41b3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c6a5febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c6a5fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c6a5e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c6a292e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c6a292b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41b3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41b3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41b3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c6a292a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (2126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629ce942eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629ce93fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629ce94362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5f0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5f04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5f0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5f0431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629ce8d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629ce8d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629ce8bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629ce56ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629ce56cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5f0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5f04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5f04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629ce56ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (2127 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d2bb5eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561d2bb5be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561d2bb5f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad20133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad2018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad20133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad2011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d2baf4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561d2baf4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561d2bad98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561d2b788e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561d2b788b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad2011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad2011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad2011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d2b788a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (2128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/18925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d6dcb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d6dcb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d6dcb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e04b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e04b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e04b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e04b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d6dc4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d6dc4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d6dc2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d6d8dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d6d8deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e04b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e04b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e04b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d6d8dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (2129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597f0415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597f0412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597f041662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb073d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb073d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb073d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb073d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597f03abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597f03aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597f03908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597f003fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597f003fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb073d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb073d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb073d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597f003fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (2130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a87d19deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a87d19ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a87d19e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa31e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa31e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa31e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa31e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a87d133bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a87d133a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a87d1188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a87cdc7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a87cdc7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa31e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa31e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa31e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a87cdc7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (2131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba25c7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba25c79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba25c7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78cb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78cb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78cb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78cb631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba25c12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba25c12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba25bf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba258a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba258a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78cb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78cb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78cb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba258a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (2132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560295be9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560295be6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560295bea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2914c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2914ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2914c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2914c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560295b7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560295b7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560295b648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560295813e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560295813b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2914c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2914c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2914c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560295813a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (2133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055affea95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055affea92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055affea9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45d891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055affea2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055affea2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055affea108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055affe6bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055affe6bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f45d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45d891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055affe6bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2134 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba8ed1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba8ed17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba8ed1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcaff733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcaff78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcaff733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcaff71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba8ecb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba8ecb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba8ec958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba8e944e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba8e944b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcaff71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcaff71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcaff71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba8e944a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (2135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055928e297eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055928e294e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055928e29862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f713f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f713f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f713f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f713f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055928e22dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055928e22da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055928e2128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055928dec1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055928dec1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f713f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f713f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f713f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055928dec1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e11688eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e11685e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e1168962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42c2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42c235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42c2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42c22ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e1161ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e1161ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e116038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e112b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e112b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f42c22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42c22ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42c22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e112b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056330134beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563301348e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056330134c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f722d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f722d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633012e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005633012e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005633012c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563300f75e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563300f75b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f722d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563300f75a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (2138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (2139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557270dc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557270dc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557270dc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e0e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e0e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e0e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e0e431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557270d5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557270d5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557270d438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572709f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572709f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8e0e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e0e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e0e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572709f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (2140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (2141 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edea267eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055edea264e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055edea26862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9498b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9498b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9498b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9498b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edea1fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055edea1fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055edea1e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ede9e91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ede9e91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9498b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9498b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9498b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ede9e91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | # | ... # `---data was truncated (10240/28350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e4a415eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e4a412e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e4a41662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7911133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f791118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7911133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f791111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e4a3abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e4a3aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e4a3908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e4a03fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e4a03fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f791111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f791111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f791111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e4a03fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (2143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591080aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591080a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591080ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f816f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f816f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f816f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f816f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559108040bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559108040a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591080258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559107cd4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559107cd4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f816f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f816f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f816f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559107cd4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (2144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e423cefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e423cece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e423cf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa635449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa635449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa635431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e423c85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e423c85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e423c6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e423919e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e423919b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa635432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6354330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e423919a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (2145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a6e3a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a6e3a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a6e3a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f690e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f690e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f690e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f690e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a6e33bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a6e33ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a6e3208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a6dfcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a6dfcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f690e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f690e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f690e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a6dfcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (2146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563dd3caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563dd3c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563dd3cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bbd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bbd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bbd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bbd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563dd360bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563dd360a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563dd3458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563dcff4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563dcff4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bbd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bbd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bbd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563dcff4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (2147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (2148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (2149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (2150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055908d514eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055908d511e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055908d51562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41a0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41a098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41a0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41a091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055908d4aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055908d4aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055908d48f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055908d13ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055908d13eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f41a091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41a091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41a091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055908d13ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (2151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) # | ... # `---data was truncated (10240/27055) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563cbaaaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563cbaa7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563cbaab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8072b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8072b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8072b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8072b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563cba40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563cba40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563cba258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563cb6d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563cb6d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8072b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8072b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8072b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563cb6d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (2152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055811a432eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055811a42fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055811a43362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f715a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f715a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f715a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f715a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055811a3c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055811a3c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055811a3ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055811a05ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055811a05cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f715a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f715a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f715a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055811a05ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (2153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056226668deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056226668ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056226668e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0354649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0354649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0354631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562266623bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562266623a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622666088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622662b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622662b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0354632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03546330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622662b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (2154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align # | ... # `---data was truncated (10240/39226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056405f5adeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056405f5aae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056405f5ae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e40649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e406a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e40649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e40631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056405f543bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056405f543a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056405f5288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056405f1d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056405f1d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e40632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e406330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e406330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056405f1d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (2155 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcde4e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcde4e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcde4e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d21533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d2158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d21533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d2151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcde47dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcde47da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcde4628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcde111e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcde111b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4d2151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d2151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d2151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcde111a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (2156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a9a56aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a9a567e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a9a56b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa11dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa11dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa11dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa11dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a9a500bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a9a500a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a9a4e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a9a194e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a9a194b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa11dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa11dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa11dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a9a194a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (2157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f6828aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f68287e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f6828b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc1dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc1dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc1dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc1dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f68220bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f68220a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f682058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f67eb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f67eb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc1dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc1dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc1dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f67eb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (2158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565394b20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565394b1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565394b2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78aa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78aa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78aa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78aa831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565394ab6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565394ab6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565394a9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056539474ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056539474ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f78aa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78aa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78aa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056539474aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (2159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7982d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7982d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7982da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbac9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbac9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbac9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbac9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c79826fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c79826fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7982548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c797f03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c797f03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbac9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbac9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbac9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c797f03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (2160 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590fc700eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005590fc6fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005590fc70162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02f1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02f135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02f1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02f12ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590fc696bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005590fc696a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590fc67b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005590fc32ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005590fc32ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02f12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02f12ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02f12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590fc32aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (2161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr % # | ... # `---data was truncated (10240/29809) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056271bad1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056271bacee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056271bad262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa579a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa579a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa579a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa579a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056271ba67bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056271ba67a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056271ba4c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056271b6fbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056271b6fbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa579a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa579a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa579a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056271b6fba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (2162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8d2ac9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8d2ac6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8d2aca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f092e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f092e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f092e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f092e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8d2a5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8d2a5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8d2a448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8d26f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8d26f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f092e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f092e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f092e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8d26f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (2163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bba4665eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bba4662e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bba466662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf1eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf1eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf1eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf1eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bba45fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bba45fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bba45e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bba428fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bba428fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faf1eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf1eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf1eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bba428fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612c90d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612c90d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612c90d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91adb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91adb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91adb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91adaed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612c906dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612c906da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612c90528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612c8d01e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612c8d01b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91adaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91adaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91adaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612c8d01a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (2165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f50c37ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f50c379e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f50c37d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e04f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e04f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e04f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e04f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f50c312bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f50c312a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f50c2f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f50bfa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f50bfa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e04f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e04f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e04f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f50bfa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (2166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055901308ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559013089e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055901308d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd882733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd88278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd882733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd88271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559013022bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559013022a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590130078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559012cb6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559012cb6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd88271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd88271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd88271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559012cb6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (2168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564878e54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564878e51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564878e5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc7fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc7fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc7fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc7fa03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564878deabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564878deaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564878dcf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564878a7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564878a7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc7fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc7fa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc7fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564878a7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (2169 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> % # | ... # `---data was truncated (10240/15051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9f6976eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9f6973e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9f697762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa45f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa45f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa45f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa45f203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9f690cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9f690ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9f68f18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9f65a0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9f65a0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa45f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa45f2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa45f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9f65a0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (2170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d800304eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d800301e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d80030562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc16e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc16e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc16e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc16e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d80029abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d80029aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d80027f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7fff2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7fff2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc16e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc16e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc16e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7fff2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (2171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (2172 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3) # | store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3) # | store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x2_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x2_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [2 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4) # | store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x2_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x2_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [2 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4) # | store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x3_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x3_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [3 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <8 x i8>, ptr %arrayidx4.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5) # | store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x3_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x3_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [3 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <16 x i8>, ptr %arrayidx4.i, align 16 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5) # | store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x4_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x4_t, align 8 # | %b.a # | ... # `---data was truncated (10240/125901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b63f0efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b63f0ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b63f0f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03dd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03dd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03dd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03dd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b63f085bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b63f085a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b63f06a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b63ed19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b63ed19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03dd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03dd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03dd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b63ed19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (2173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564344beaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564344be7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564344beb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6aad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6aad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6aad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6aad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564344b80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564344b80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564344b658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564344814e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564344814b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd6aad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6aad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6aad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564344814a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (2174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4fc293eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4fc290e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4fc29462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3741249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37412a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3741249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3741231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4fc229bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4fc229a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4fc20e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4fbebde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4fbebdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3741232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37412330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37412330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4fbebda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (2175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb3f1e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb3f1e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb3f1e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5fd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5fd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5fd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5fd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb3f179bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb3f179a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb3f15e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb3ee0de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb3ee0db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5fd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5fd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5fd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb3ee0da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (2176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (2177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e94ea6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e94ea3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e94ea762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bd7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bd718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bd7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bd711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e94e3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e94e3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e94e218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e94ad0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e94ad0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0bd711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bd711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bd711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e94ad0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (2178 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e62b55ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e62b559e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e62b55d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4de9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4de998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4de9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4de991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e62b4f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e62b4f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e62b4d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e62b186e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e62b186b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4de991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4de991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4de991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62b186a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (2179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed64274eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed64271e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed6427562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fead1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fead14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fead1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fead1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed6420abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed6420aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed641ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed63e9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed63e9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fead1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fead14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fead14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed63e9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (2180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (2181 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9d8359eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9d8356e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9d835a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc9db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc9db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc9db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc9db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9d82efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9d82efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9d82d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9d7f83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9d7f83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc9db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc9db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc9db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9d7f83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (2182 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575d2386eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575d2383e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005575d238762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dd8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dd898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dd8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dd891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575d231cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005575d231ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005575d23018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005575d1fb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005575d1fb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5dd891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dd891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dd891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575d1fb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (2183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b205c1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b205c18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b205c1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8b2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8b26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8b2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8b2631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b205bb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b205bb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b205b968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b205845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b205845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8b2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8b26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8b26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b205845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (2184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (2185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a0ec81eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a0ec7ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a0ec8262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7db7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7db78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7db7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7db7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a0ec17bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a0ec17a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a0ebfc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a0e8abe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a0e8abb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7db7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7db78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7db78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a0e8aba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (2186 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (2187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a64f4cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a64f4c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a64f4cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb547a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb547aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb547a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb547a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a64f461bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a64f461a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a64f4468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a64f0f5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a64f0f5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb547a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb547a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb547a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a64f0f5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (2188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eff5baaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eff5ba7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eff5bab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7273e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7273e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7273e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7273e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eff5b40bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eff5b40a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eff5b258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eff57d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eff57d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7273e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7273e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7273e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eff57d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (2189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d8f857eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d8f854e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d8f85862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4e0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4e08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4e0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4e0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d8f7edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d8f7eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d8f7d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d8f481e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d8f481b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb4e0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4e08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4e08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d8f481a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (2190 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2191 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2c46fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f2c46f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f2c46fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52dda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52dda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52dda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52dda03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2c4692bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2c4692a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2c46778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2c4326e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2c4326b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52dda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52dda050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52dda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2c4326a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (2192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (2193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9ba938eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9ba935e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9ba93962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e87e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e87e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e87e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e87e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9ba8cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9ba8cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9ba8b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9ba562e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9ba562b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e87e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e87e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e87e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9ba562a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (2194 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/32702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4a0b67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4a0b64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4a0b6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb8b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb8b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb8b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb8b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4a0afdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c4a0afda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4a0ae28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4a0791e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4a0791b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb8b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb8b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb8b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4a0791a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (2195 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %bas # | ... # `---data was truncated (10240/60209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b9b7a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b9b7a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b9b7a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb95a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb95aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb95a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb95a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b9b73abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b9b73aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b9b71f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b9b3cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b9b3ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb95a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb95a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb95a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b9b3cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (2196 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (2197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f05b67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f05b64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f05b6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0909b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0909b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0909b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0909aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f05afdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f05afda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f05ae28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f05791e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f05791b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0909aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0909aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0909aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f05791a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (2198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560faf164eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560faf161e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560faf16562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4afa105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4afa15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4afa105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4afa0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560faf0fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560faf0faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560faf0df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560faed8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560faed8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4afa0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4afa0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4afa0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560faed8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (2199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056080488ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560804889e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056080488d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84aeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84aeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84aeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84aeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560804822bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560804822a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005608048078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005608044b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005608044b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84aeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84aeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84aeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608044b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (2200 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e30f5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e30f5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e30f6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb1ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb1ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb1ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb1ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e30ef5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e30ef5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e30eda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e30b89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e30b89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb1ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb1ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb1ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e30b89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (2201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556eb469ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556eb4699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556eb469d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaee533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaee58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaee533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaee51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556eb4632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556eb4632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556eb46178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556eb42c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556eb42c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feaee51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaee51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaee51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556eb42c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (2202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f89e20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f89e1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f89e2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17fd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17fd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17fd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17fd231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f89db6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f89db6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f89d9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f89a4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f89a4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17fd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17fd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17fd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f89a4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (2203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c1f84deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c1f84ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c1f84e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f240aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f240aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f240aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f240aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c1f7e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c1f7e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c1f7c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c1f477e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c1f477b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f240aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f240aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f240aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c1f477a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (2204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (2205 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579dcce8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579dcce5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579dcce962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe812249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8122a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe812249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe812231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579dcc7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005579dcc7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005579dcc638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005579dc912e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005579dc912b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe812232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8122330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8122330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579dc912a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (2206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c23140eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c23140be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c23140f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85d4c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85d4c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85d4c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85d4c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2313a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2313a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2313898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c231038e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c231038b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85d4c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85d4c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85d4c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c231038a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (2207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c6b1deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c6b1dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c6b1df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb6b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb6b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb6b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb6b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c6b174bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c6b174a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c6b1598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c6ae08e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c6ae08b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb6b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb6b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb6b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c6ae08a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (2208 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650c12c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005650c12bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005650c12c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3db533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3db58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3db533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3db51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650c1256bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005650c1256a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005650c123b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005650c0eeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005650c0eeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb3db51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3db51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3db51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650c0eeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (2209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564934d3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564934d3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564934d4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04c2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04c235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04c2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04c22ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564934cd5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564934cd5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564934cba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564934969e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564934969b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04c22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04c22ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04c22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564934969a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (2210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565197435eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565197432e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056519743662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd63df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd63df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd63df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd63df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651973cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651973cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651973b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056519705fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056519705fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd63df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd63df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd63df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056519705fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (2211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558fc1a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005558fc1a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005558fc1a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f871d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f871d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f871d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f871d431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558fc139bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005558fc139a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005558fc11e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005558fbdcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005558fbdcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f871d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f871d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f871d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558fbdcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (2212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e25a75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e25a72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e25a7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb672133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb67218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb672133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb67211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e25a0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e25a0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e259f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e2569fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e2569fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb67211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb67211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb67211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e2569fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (2213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c5645aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558c56457e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558c5645b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17cbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17cbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17cbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17cbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c563f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558c563f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558c563d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558c56084e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558c56084b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17cbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17cbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17cbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c56084a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (2214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1a7e2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1a7e28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1a7e2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d24249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d24249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d24231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1a7dc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1a7dc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1a7da68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1a7a55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1a7a55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d24232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d242330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1a7a55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2215 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/53686) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055992044deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055992044ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055992044e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a86733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a8678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a86733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a8671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599203e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599203e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599203c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559920077e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559920077b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a8671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a8671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a8671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559920077a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (2216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (2217 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d53f4eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d53f4be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d53f4f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc022849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0228a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc022849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc022831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d53ee4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d53ee4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d53ec98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d53b78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d53b78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc022832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0228330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0228330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d53b78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (2218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29128) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b91120eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b9111de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b9112162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f629f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f629f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f629f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f629f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b910b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b910b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b9109b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b90d4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b90d4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f629f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f629f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f629f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b90d4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (2219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfec25deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfec25ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfec25e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4098c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4098c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4098c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4098c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfec1f3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfec1f3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfec1d88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfebe87e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfebe87b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4098c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4098c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4098c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfebe87a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (2220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611a8803eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611a8800e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611a880462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0694b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0694b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0694b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0694aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611a8799bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611a8799a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611a877e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611a842de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611a842db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0694aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0694aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0694aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611a842da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (2222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b947588eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b947585e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b94758962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cd2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cd28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cd2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cd2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b94751ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b94751ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9475038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9471b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9471b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1cd2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cd28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cd28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9471b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (2223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fadfd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fadfcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fadfd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3b5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3b538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3b5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3b531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fadf66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fadf66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fadf4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fadbfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fadbfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3b531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3b531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3b531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fadbfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (2224 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/151253) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f83fd9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f83fd6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f83fda62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5be6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5be6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5be6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5be6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f83f6fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f83f6fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f83f548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f83c03e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f83c03b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5be6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5be6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5be6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f83c03a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (2225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1f3d74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1f3d71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1f3d7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f3b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f3b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f3b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f3b403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1f3d0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c1f3d0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1f3cef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c1f399ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c1f399eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f3b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f3b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f3b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1f399ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (2226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (2227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (2228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = loa # | ... # `---data was truncated (10240/18917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d44dadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558d44daae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558d44dae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61dac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61dac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61dac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61dac03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d44d43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558d44d43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558d44d288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558d449d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558d449d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61dac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61dac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61dac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d449d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (2229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1c8006eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b1c8003e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b1c800762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa163733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa16378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa163733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa16371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1c7f9cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1c7f9ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b1c7f818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b1c7c30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b1c7c30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa16371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa16371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa16371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1c7c30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (2230 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e52cd7beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e52cd78e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e52cd7c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8964d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8964d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8964d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8964d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e52cd11bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e52cd11a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e52ccf68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e52c9a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e52c9a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8964d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8964d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8964d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e52c9a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (2231 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (2232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627e4086eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627e4083e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627e408762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbc9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbc978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbc9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbc971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627e401cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627e401ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627e40018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627e3cb0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627e3cb0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbc971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbc971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbc971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627e3cb0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (2233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc35c01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc35bfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc35c0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ec2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ec2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ec2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ec2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc35b97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc35b97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc35b7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc3582be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc3582bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5ec2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ec2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ec2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc3582ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (2234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588dc32feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588dc32ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588dc33062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe749e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe749ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe749e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe749e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588dc2c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588dc2c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588dc2aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588dbf59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588dbf59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe749e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe749e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe749e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588dbf59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (2235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9c97c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b9c97bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b9c97c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc94d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc94d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc94d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc94d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9c9757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b9c9757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b9c973c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b9c93ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b9c93ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc94d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc94d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc94d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9c93eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (2236 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align # | ... # `---data was truncated (10240/30281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000561ee5c26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ee5c23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ee5c2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5e8505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5e855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5e8505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5e84ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ee5bbcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ee5bbca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ee5ba18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ee5850e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ee5850b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5e84eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5e84ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5e84ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ee5850a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (2237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (2238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca # | ... # `---data was truncated (10240/43515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593614a2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055936149fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593614a362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55cef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55cef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55cef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55cef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559361438bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559361438a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055936141d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593610cce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593610ccb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55cef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55cef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55cef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593610cca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (2239 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %class.anon = type { i8 } # | # | $_Z15template_functyIiET_S0_ = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_caller() #0 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | declare i32 @normal_callee() #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_callee() #0 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret i32 %call # | } # | # | declare i32 @streaming_decl() #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_caller() #3 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_callee() #3 { # | entry: # | %call = call i32 @streaming_compatible_decl() #16 # | ret i32 %call # | } # | # | declare i32 @streaming_compatible_decl() #4 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_caller() #5 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_callee() #5 { # | entry: # | %call = call i32 @locally_streaming_caller() #17 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_caller() #6 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_callee() #6 { # | entry: # | %call = call i32 @shared_za_decl() #18 # | ret i32 %call # | } # | # | declare i32 @shared_za_decl() #7 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_caller() #8 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_callee() #8 { # | entry: # | %call = call i32 @preserves_za_decl() #19 # | ret i32 %call # | } # | # | declare i32 @preserves_za_decl() #9 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_caller() #10 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_callee() #10 { # | entry: # | %call = call i32 @private_za_decl() # | ret i32 %call # | } # | # | declare i32 @private_za_decl() #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_caller() #11 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee() #12 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | declare i32 @agnostic_za_decl() #13 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee_live_za() #6 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #16 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #18 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #19 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %fptr.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %fptr, ptr %fptr.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %fptr.addr, align 8 # | %1 = load ptr, ptr %0, align 8 # | %2 = load ptr, ptr %1, align 8 # | %3 = load i32, ptr %x.addr, align 4 # | %4 = load i32, ptr %y.addr, align 4 # | call void %2(i32 noundef %3, i32 noundef %4) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @_Z24test_same_type_streamingv() #12 { # | entry: # | call void @_Z10streaming1v() #15 # | call void @_Z10streaming2v() #15 # | call void @_Z20same_type_streaming1v() #15 # | call void @_Z20same_type_streaming2v() #15 # | ret void # | } # | # | declare void @_Z10streaming1v() #2 # | # | declare void @_Z10streaming2v() #2 # | # | declare void @_Z20same_type_streaming1v() #2 # | # | declare void @_Z20same_type_streaming2v() #2 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | ret float %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | %call = call noundef float @_Z12overloadedfnf(float noundef %0) # | ret float %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | %F = alloca %class.anon, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 { # | entry: # | %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z25locally_streaming_inheritv() #5 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret void # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define dso_local noundef i32 @_Z4callv() #14 { # | entry: # | ret i32 0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 { # | entry: # | %f.addr.i16 = alloca ptr, align 8 # | %f.addr.i12 = alloca ptr, align 8 # | %other.addr.i13 = alloca ptr, align 8 # | %f.addr.i7 = alloca ptr, align 8 # | %other.addr.i8 = alloca ptr, align 8 # | %other.addr2.i9 = alloca ptr, align 8 # | %f.addr.i1 = alloca ptr, align 8 # | %other.addr.i2 = alloca ptr, align 8 # | %other.addr2.i3 = alloca ptr, align 8 # | %other.addr4.i4 = alloca ptr, align 8 # | %f.addr.i = alloca ptr, align 8 # | %other.addr.i = alloca ptr, align 8 # | %other.addr2.i = alloca ptr, align 8 # | %other.addr4.i = alloca ptr, align 8 # | %other.addr6.i = alloca ptr, align 8 # | store ptr @normal_callee, ptr %f.addr.i, align 8 # | store ptr @streaming_decl, ptr %other.addr.i, align 8 # | store ptr @streaming_compatible_decl # | ... # `---data was truncated (10240/15241) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8bde37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8bde34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8bde3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f630d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f630d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f630d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f630d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8bddcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8bddcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8bddb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8bda61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8bda61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f630d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f630d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f630d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8bda61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x0000564366f54eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564366f51e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564366f5562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09fcd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09fcd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09fcd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09fcd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564366eeabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564366eeaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564366ecf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564366b7ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564366b7eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09fcd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09fcd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09fcd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564366b7ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (2240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd # | ... # `---data was truncated (10240/215044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559907f2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559907f2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559907f3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f836af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f836af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f836af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f836af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559907ec5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559907ec5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559907eaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559907b59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559907b59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f836af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f836af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f836af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559907b59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (2241 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7c0ec2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7c0ebfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7c0ec362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d9dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d9dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d9dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d9dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7c0e58bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a7c0e58a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a7c0e3d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7c0aece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7c0aecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d9dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d9dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d9dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7c0aeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (2242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056060dd8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056060dd8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056060dd8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb227d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb227d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb227d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb227ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000056060dd24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056060dd24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056060dd098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056060d9b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056060d9b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb227ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb227cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb227cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056060d9b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (2243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562966c55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562966c52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562966c5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc443305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc44335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc443305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4432ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562966bebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562966beba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562966bd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056296687fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056296687fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4432eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4432ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4432ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056296687fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (2244 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562897a1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562897a18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562897a1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25cb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25cb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25cb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25cb631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628979b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628979b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628979968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562897645e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562897645b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25cb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25cb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25cb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562897645a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (2245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635e3e01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635e3dfee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635e3e0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0fae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635e3d97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635e3d97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635e3d7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635e3a2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635e3a2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe0fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0fae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635e3a2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (2246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3a262eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e3a262be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e3a262f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda7af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda7af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda7af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda7af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3a25c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e3a25c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e3a25a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e3a2258e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e3a2258b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda7af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda7af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda7af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3a2258a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (2247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (2248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056057cfc4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056057cfc1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056057cfc562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe492f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe492f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe492f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe492f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056057cf5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056057cf5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056057cf3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056057cbeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056057cbeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe492f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe492f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe492f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056057cbeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (2249 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2caec4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2caec1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2caec562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f9f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f9f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f9f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f9f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2cae5abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2cae5aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2cae3f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2caaeee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2caaeeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f9f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f9f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f9f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2caaeea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (2250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align # | ... # `---data was truncated (10240/29111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583458cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583458cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583458d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09b2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09b2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09b2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09b2a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558345865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558345865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055834584a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583454f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583454f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09b2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09b2a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09b2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583454f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (2251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = # | ... # `---data was truncated (10240/26564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055955d291eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055955d28ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055955d29262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb467133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb46718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb467133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb46711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055955d227bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055955d227a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055955d20c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055955cebbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055955cebbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb46711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb46711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb46711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055955cebba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (2252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056328eb01eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056328eafee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056328eb0262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff73dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff73dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff73dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff73dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056328ea97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056328ea97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056328ea7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056328e72be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056328e72bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff73dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff73dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff73dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056328e72ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (2253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583d9e1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583d9e17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583d9e1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe41e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe41e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe41e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe41e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583d9db0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583d9db0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583d9d958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583d9a44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583d9a44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe41e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe41e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe41e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583d9a44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (2254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (2255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b10142eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563b1013fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563b1014362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63c211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b100d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563b100d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563b100bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563b0fd6ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563b0fd6cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63c211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b0fd6ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (2256 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560771acceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560771ac9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560771acd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1cfe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1cfe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1cfe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1cfe03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560771a62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560771a62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560771a478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607716f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607716f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1cfe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1cfe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1cfe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607716f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2257 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # | #0 0x000055885edf8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055885edf5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055885edf962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04b5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04b5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04b5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04b5c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055885ed8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055885ed8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055885ed738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055885ea22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055885ea22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04b5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04b5c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04b5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055885ea22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (2258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559954a73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559954a70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559954a7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bfc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bfc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bfc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bfc631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559954a09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559954a09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599549ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055995469de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055995469db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bfc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bfc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bfc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055995469da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (2259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbcfacceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbcfac9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbcfacd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f310f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f310f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f310f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f310f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbcfa62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbcfa62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbcfa478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbcf6f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbcf6f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f310f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f310f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f310f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbcf6f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (2260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/12648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a323a2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a323a2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a323a3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1338533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f133858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1338533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f133851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3239c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3239c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3239aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a323659e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a323659b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f133851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f133851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f133851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a323659a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (2261 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | # | ... # `---data was truncated (10240/17536) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a478940eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a47893de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a47894162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2126d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2126d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2126d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2126ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4788d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4788d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4788bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a47856ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a47856ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2126ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2126cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2126cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a47856aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (2262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ # | ... # `---data was truncated (10240/18570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565193fa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565193fa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565193fa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb36733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb3678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb36733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb3671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565193f3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565193f3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565193f208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565193bcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565193bcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb3671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb3671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb3671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565193bcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (2263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0af8b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0af8ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0af8b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f778b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f778b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f778b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f778b203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0af846bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0af846a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0af82b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0af4dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0af4dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f778b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f778b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f778b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0af4daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (2264 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560991456eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560991453e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056099145762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86c4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86c478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86c4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86c471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609913ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609913eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609913d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560991080e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560991080b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86c471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86c471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86c471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560991080a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (2265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (2266 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557fa849eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557fa846e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557fa84a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f0bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f0bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f0bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f0beed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557fa7dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557fa7dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557fa7c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557fa473e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557fa473b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5f0beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f0beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f0beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557fa473a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (2267 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -252) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 -243) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 195) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 8978432) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 { # | entry: # | ret <8 x i16> splat (i16 27391) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 { # | entry: # | ret <4 x i32> splat (i32 -5570561) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 { # | entry: # | ret <8 x i16> splat (i16 -18689) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 { # | entry: # | ret <4 x i32> splat (i32 1023410175) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -11265) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -13893633) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -37) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -1644167169) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 13568) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 654311424) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 175) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 89) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %inactive.addr, align 8 # | %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> % # | ... # `---data was truncated (10240/13125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564322156eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564322153e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056432215762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2ad333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2ad38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2ad333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2ad31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643220ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643220eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643220d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564321d80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564321d80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe2ad31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2ad31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2ad31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564321d80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (2268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (2269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a46fe4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a46fe4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a46fe5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff35f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff35f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff35f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff35f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a46fde5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a46fde5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a46fdca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a46fa79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a46fa79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff35f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff35f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff35f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a46fa79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (2270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e1adf9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e1adf6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e1adfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf31049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf31049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf31031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e1ad8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e1ad8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e1ad748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e1aa23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e1aa23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf31032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf310330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e1aa23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (2271 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad25abeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad25abbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad25abf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8da7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8da798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8da7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8da791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad25a54bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad25a54a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad25a398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad256e8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad256e8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8da791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8da791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8da791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad256e8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (2272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset, i64 no # | ... # `---data was truncated (10240/287205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea74660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea7465de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea7466162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b7905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b795c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b7905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b78ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea745f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea745f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea745db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea7428ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea7428ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9b78eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b78ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b78ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea7428aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (2273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627668cfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627668cce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627668d062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c12733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c1278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c12733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c1271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562766865bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562766865a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056276684a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627664f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627664f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c1271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c1271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c1271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627664f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (2274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9e025feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e9e025ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e9e026062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec7fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec7fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec7fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec7fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9e01f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e9e01f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e9e01da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9dfe89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9dfe89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec7fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec7fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec7fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9dfe89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (2275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580afe5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005580afe59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005580afe5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf27d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf27d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf27d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf27d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580afdf2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005580afdf2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005580afdd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005580afa86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005580afa86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf27d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf27d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf27d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580afa86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (2276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m4_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv32i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv32i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m4_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, p # | ... # `---data was truncated (10240/54546) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e1d349eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e1d346e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e1d34a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd19449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd19449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd19431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e1d2dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e1d2dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e1d2c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e1cf73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e1cf73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd19432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd194330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e1cf73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (2277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (2278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056021f985eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056021f982e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056021f98662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcccd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcccd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcccd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcccd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056021f91bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056021f91ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056021f9008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056021f5afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056021f5afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcccd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcccd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcccd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056021f5afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (2279 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb5ecd5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb5ecd2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb5ecd662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdb1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdb14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdb1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdb1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb5ec6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb5ec6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb5ec508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb5e8ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb5e8ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbdb1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdb14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdb14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb5e8ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (2280 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (2281 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64es(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64esm(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e079d23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e079d20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e079d2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e079cb9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e079cb9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e079c9e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e07994de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e07994db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e07994da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (2282 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e23ef04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e23ef01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e23ef0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc68b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc68b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc68b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc68b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e23ee9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e23ee9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e23ee7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e23eb2ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e23eb2eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc68b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc68b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc68b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e23eb2ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (2283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563c7239eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563c7236e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563c723a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46fdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46fdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46fdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46fdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563c71cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563c71cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563c71b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563c6e63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563c6e63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46fdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46fdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46fdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563c6e63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (2284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (2285 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down. # | ... # `---data was truncated (10240/14900) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056337b2d2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056337b2cfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056337b2d362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056337b268bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056337b268a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056337b24d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056337aefce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056337aefcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056337aefca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (2286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.ad # | ... # `---data was truncated (10240/13903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056160af8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056160af8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056160af8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc84b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc84b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc84b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc84b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160af24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056160af24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056160af098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056160abb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056160abb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc84b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc84b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc84b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056160abb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (2287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2288 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599ce59deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599ce59ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599ce59e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93b8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93b878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93b8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93b871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599ce533bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599ce533a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599ce5188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599ce1c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599ce1c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93b871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93b871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93b871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599ce1c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (2289 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055862b38eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055862b38be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055862b38f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93e1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93e14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93e1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93e1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055862b324bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055862b324a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055862b3098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055862afb8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055862afb8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93e1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93e14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93e14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055862afb8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (2290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (2291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa8af44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fa8af41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fa8af4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9974933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f997498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9974933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f997491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa8aedabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fa8aedaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fa8aebf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fa8ab6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fa8ab6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f997491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f997491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f997491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa8ab6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (2292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a47e409eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a47e406e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a47e40a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccebb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a47e39fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a47e39fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a47e3848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a47e033e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a47e033b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a47e033a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (2293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/205813) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556acf39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556acf36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556acf3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f60f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f60f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f60f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f60eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556acecfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556acecfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556aceb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556acb63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556acb63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f60eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f60eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f60eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556acb63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (2294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628ee164eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005628ee161e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005628ee16562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5e5231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628ee0fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005628ee0faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005628ee0df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005628edd8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005628edd8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5e52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628edd8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (2295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c3ec8deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c3ec8ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c3ec8e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f467d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f467d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f467d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f467d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c3ec23bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c3ec23a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c3ec088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c3e8b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c3e8b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f467d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f467d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f467d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c3e8b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (2296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (2297 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (2298 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4d0d55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4d0d52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4d0d5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f269ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f269cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f269ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f269ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4d0cebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4d0ceba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4d0cd08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4d097fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4d097fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f269ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f269ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f269ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4d097fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (2299 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561173aebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561173ae8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561173aec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe746649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe746649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe746631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561173a81bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561173a81a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561173a668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561173715e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561173715b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe746632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7466330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561173715a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (2300 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a62897eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a62894e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a6289862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f185ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f185eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f185ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f185ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a6282dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a6282da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a628128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a624c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a624c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f185ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f185ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f185ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a624c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (2301 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, %vs1, # | ... # `---data was truncated (10240/62087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630bbd92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630bbd8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630bbd9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f8fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f8faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f8fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f8fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630bbd28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630bbd28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630bbd0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630bb9bce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630bb9bcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f8fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f8fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f8fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630bb9bca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (2302 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/13625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ea2d09eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ea2d06e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ea2d0a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f666761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66676725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f666761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6667603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ea2c9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ea2c9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ea2c848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ea2933e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ea2933b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6667604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66676050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66676050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ea2933a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (2303 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v # | ... # `---data was truncated (10240/18520) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9c99dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a9c99d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a9c99dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3746733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f374678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3746733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f374671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9c9972bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a9c9972a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a9c99578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a9c9606e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a9c9606b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f374671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f374671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f374671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9c9606a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2304 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556abcf67eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556abcf64e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556abcf6862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2beff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2beff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2beff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2beff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556abcefdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556abcefda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556abcee28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556abcb91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556abcb91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2beff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2beff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2beff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556abcb91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (2305 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (2306 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566bcc83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566bcc80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566bcc8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5d3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5d3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5d3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5d3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566bcc19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005566bcc19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566bcbfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005566bc8ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005566bc8adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc5d3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5d3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5d3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566bc8ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (2307 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (2308 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3ce6c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a3ce6c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a3ce6c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f715c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f715c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f715c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f715c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ce65bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3ce65ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3ce6408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3ce2efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3ce2efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f715c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f715c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f715c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ce2efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (2309 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (2310 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556af7d28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556af7d25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556af7d2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44b8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44b8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44b8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44b8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556af7cbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556af7cbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556af7ca38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556af7952e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556af7952b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f44b8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44b8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44b8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556af7952a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (2311 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26b6e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c26b6e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c26b6e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d60333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d6038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d60333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d6031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c26b67dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c26b67da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c26b6628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c26b311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c26b311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d6031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d6031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d6031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26b311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (2312 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556974475eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556974472e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055697447662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31f7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31f738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31f7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31f731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055697440bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055697440ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005569743f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055697409fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055697409fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31f731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31f731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31f731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055697409fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (2313 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f0e874eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f0e871e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f0e87562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9038933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f903898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9038933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f903891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f0e80abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f0e80aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f0e7ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f0e49ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f0e49eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f903891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f903891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f903891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f0e49ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (2314 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/94149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056028e53ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056028e539e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056028e53d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa84e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa84e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa84e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa84e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056028e4d2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056028e4d2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056028e4b78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056028e166e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056028e166b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa84e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa84e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa84e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056028e166a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (2315 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6f4442eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6f443fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6f444362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dbf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dbf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dbf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dbf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6f43d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6f43d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6f43bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6f406ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6f406cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2dbf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dbf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dbf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6f406ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (2316 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1) # | store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.fptosi.sat.i64.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | st # | ... # `---data was truncated (10240/53064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557bb4fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557bb4f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557bb4fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcea9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcea918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcea9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcea911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557bb492bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557bb492a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557bb4778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557bb126e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557bb126b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcea911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcea911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcea911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557bb126a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2317 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562575b85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562575b82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562575b8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eebf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562575b1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562575b1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562575b008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625757afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625757afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8eebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625757afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (2318 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x half>, ptr %0, align 2 # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x float>, ptr %0, align 4 # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i8>, ptr %0, align 1 # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i8>, ptr %0, align 1 # | %2 = sext <4 x i8> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = a # | ... # `---data was truncated (10240/50873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604eaf89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005604eaf86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005604eaf8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21ba733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21ba78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21ba733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21ba71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604eaf1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604eaf1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604eaf048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604eabb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604eabb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f21ba71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21ba71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21ba71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604eabb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (2319 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 # | ... # `---data was truncated (10240/29175) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d209a24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d209a21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d209a2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08f4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08f418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08f4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08f411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2099babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2099baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d20999f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d20964ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d20964eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08f411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08f411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08f411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d20964ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (2320 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @test_vlenb() #0 { # | entry: # | %0 = call i32 @llvm.read_register.i32(metadata !4) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.read_register.i32(metadata) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"vlenb"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x00005572b469ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572b4699e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572b469d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86d0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572b4632bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572b4632a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572b46178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572b42c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572b42c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f86d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572b42c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (2321 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a618f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a618efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a618f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ab5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ab58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ab5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ab5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a61888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a61888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a6186d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a6151ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a6151cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ab5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ab58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ab58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a6151ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (2322 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb05a60eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb05a5de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb05a6162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe341049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3410a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe341049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe341031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb059f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb059f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb059db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb0568ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb0568ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe341032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3410330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3410330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb0568aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (2323 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649ccc44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649ccc41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649ccc4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f286fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f286fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f286fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f286fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649ccbdabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649ccbdaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649ccbbf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649cc86ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649cc86eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f286fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f286fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f286fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649cc86ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (2324 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f50283eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f50280e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f5028462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0525133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f052518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0525133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f052511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f50219bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f50219a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f501fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f4feade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f4feadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f052511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f052511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f052511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f4feada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2325 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = all # | ... # `---data was truncated (10240/41587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1eb136eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e1eb133e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e1eb13762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ab0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ab06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ab0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ab0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1eb0ccbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e1eb0cca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e1eb0b18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e1ead60e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e1ead60b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ab0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ab06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ab06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1ead60a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (2326 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (2327 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0323dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c0323d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c0323dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f348db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f348db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f348db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f348db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c032371bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c032371a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c0323568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c032005e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c032005b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f348db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f348db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f348db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c032005a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (2328 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, p # | ... # `---data was truncated (10240/33435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ba56d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ba56cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ba56d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e2bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e2bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e2bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e2bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ba5666bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ba5666a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ba564b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ba52fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ba52fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e2bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e2bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e2bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ba52faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (2329 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.a # | ... # `---data was truncated (10240/33190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055947cd9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055947cd98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055947cd9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f208f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f208f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f208f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f208f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055947cd31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055947cd31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055947cd168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055947c9c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055947c9c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f208f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f208f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f208f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055947c9c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (2330 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646fd6fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646fd6fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646fd6fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22da049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22da0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22da049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22da031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646fd693bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646fd693a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646fd6788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646fd327e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646fd327b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f22da032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22da0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22da0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646fd327a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (2331 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b710a79eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b710a76e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b710a7a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1252649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12526a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1252649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1252631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b710a0fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b710a0fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7109f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7106a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7106a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1252632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12526330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12526330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7106a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (2332 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634098c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634098bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634098c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff073c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff073ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff073c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff073c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563409858bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563409858a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056340983d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634094ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634094ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff073c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff073c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff073c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634094eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (2333 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562391a71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562391a6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562391a7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc197649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1976a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc197649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc197631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562391a07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562391a07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623919ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056239169be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056239169bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc197632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1976330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1976330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056239169ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (2334 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571f1695eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571f1692e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571f169662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bffc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bffca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bffc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bffc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571f162bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571f162ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571f16108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571f12bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571f12bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bffc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bffc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bffc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571f12bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (2335 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (2336 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563806cd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563806ccde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563806cd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd32b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd32b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd32b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd32b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563806c66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563806c66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563806c4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005638068fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005638068fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd32b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd32b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd32b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638068faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (2337 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561145550eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056114554de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056114555162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feeb5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feeb598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feeb5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feeb591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611454e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005611454e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611454cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056114517ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056114517ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feeb591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feeb591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feeb591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056114517aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (2338 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (2339 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bdfb4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562bdfb4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562bdfb4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfe2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfe2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfe2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfe2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bdfae3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562bdfae3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562bdfac88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562bdf777e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562bdf777b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfe2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfe2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfe2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bdf777a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (2340 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562221485eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562221482e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056222148662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed9c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed9c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed9c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed9c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056222141bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056222141ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622214008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005622210afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005622210afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed9c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed9c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed9c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622210afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (2341 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = # | ... # `---data was truncated (10240/33471) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf54997eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bf54994e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bf5499862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4f241bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4f24725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4f241ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4f2403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf5492dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bf5492da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bf549128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bf545c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bf545c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4f2404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4f24050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4f24050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf545c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2342 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/18873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f4ed68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f4ed65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f4ed6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facc6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facc6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facc6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facc6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f4ecfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f4ecfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f4ece38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f4e992e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f4e992b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007facc6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facc6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facc6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f4e992a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (2343 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f7d811eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f7d80ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f7d81262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8688f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8688f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8688f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8688f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f7d7a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f7d7a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f7d78c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f7d43be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f7d43bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8688f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8688f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8688f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f7d43ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (2344 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582394ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582394e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582394ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1c0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1c08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1c0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1c0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558239481bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558239481a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582394668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558239115e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558239115b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1c0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1c08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1c08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558239115a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (2345 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d744dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d744d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d744dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6cb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6cb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6cb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6cb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d74471bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d74471a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d744568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d74105e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d74105b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6cb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6cb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6cb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d74105a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (2346 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e366c3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e366c39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e366c3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbaaf249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbaaf2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbaaf249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbaaf231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e366bd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e366bd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e366bb78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e366866e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e366866b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbaaf232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbaaf2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbaaf2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e366866a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (2347 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (2348 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3980dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d3980dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d3980e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05b1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d398075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d398075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d39805a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d397d09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d397d09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f05b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d397d09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (2349 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # | #0 0x00005609b38d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609b38d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609b38da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14b2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609b386fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609b386fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609b38548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005609b3503e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005609b3503b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14b2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609b3503a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2350 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (2351 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/68247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df319b6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055df319b3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055df319b762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a52449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a524a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a52449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a52431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df3194cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055df3194ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055df319318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055df315e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055df315e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a52432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a524330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a524330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df315e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (2352 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (2353 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600a9e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600a9e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600a9e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ff2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ff2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ff2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ff2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600a9d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600a9d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600a9d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600a9a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600a9a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ff2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ff2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ff2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600a9a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (2354 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/30268) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d21ac4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d21ac47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d21ac4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff42f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff42f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff42f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff42f803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d21abe0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d21abe0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d21abc58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d21a874e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d21a874b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff42f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff42f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff42f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d21a874a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (2355 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055622f1cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055622f1cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055622f1ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c0fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c0fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c0fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c0fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055622f163bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055622f163a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055622f1488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055622edf7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055622edf7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5c0fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c0fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c0fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055622edf7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (2356 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (2357 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl # | ... # `---data was truncated (10240/27434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562056087eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562056084e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056205608862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb255249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2552a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb255249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb255231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056205601dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056205601da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620560028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562055cb1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562055cb1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb255232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2552330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2552330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562055cb1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (2358 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe13506eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe13503e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe1350762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5179b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5179b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5179b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5179b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe1349cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe1349ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe134818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe13130e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe13130b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5179b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5179b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5179b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe13130a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (2359 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | % # | ... # `---data was truncated (10240/47698) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f22260feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f22260ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f22261062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f846c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f846c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f846c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f846c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2225a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2225a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f22258a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f222239e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f222239b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f846c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f846c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f846c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f222239a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (2360 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (2361 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605705caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605705c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605705cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfefd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfefd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfefd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfefd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560570560bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560570560a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605705458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605701f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605701f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbfefd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfefd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfefd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605701f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (2362 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff17349eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff17346e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff1734a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dd7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dd72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dd7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dd7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff172dfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff172dfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff172c48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff16f73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff16f73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5dd7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dd72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dd72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff16f73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (2363 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562309ed5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562309ed2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562309ed662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbaffc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbaffca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbaffc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbaffc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562309e6bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562309e6ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562309e508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562309affe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562309affb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbaffc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbaffc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbaffc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562309affa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (2364 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/70979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556aae866eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556aae863e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556aae86762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f740ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f740ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f740ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f740ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556aae7fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556aae7fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556aae7e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556aae490e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556aae490b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f740ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f740ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f740ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556aae490a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (2365 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558364c87eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558364c84e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558364c8862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09b6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09b6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09b6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09b6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558364c1dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558364c1da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558364c028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583648b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583648b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09b6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09b6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09b6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583648b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (2366 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f12369eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f12366e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f1236a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb00fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb00fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb00fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb00fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f122ffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f122ffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f122e48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f11f93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f11f93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb00fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb00fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb00fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f11f93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (2367 of 27910) ******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | $__profc__Z6helperi = comdat any # | # | $__llvm_prf_unifcnt__Z6helperi = comdat any # | # | $__profc__Z6kernelPi = comdat any # | # | $__llvm_prf_unifcnt__Z6kernelPi = comdat any # | # | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0 # | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8 # | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8 # | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1 # | @__start___llvm_prf_names = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_names = external hidden addrspace(1) global i8 # | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__start___llvm_prf_data = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_data = external hidden addrspace(1) global i8 # | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__llvm_profile_raw_version = external addrspace(1) constant i64 # | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version } # | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata" # | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %x.addr = alloca i32, align 4, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store i32 %x, ptr %x.addr.ascast, align 4 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load i32, ptr %x.addr.ascast, align 4 # | %add = add nsw i32 %1, 1 # | ret i32 %add # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1) # | br label %po_cont # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone # | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %p = alloca ptr, align 8, addrspace(5) # | %p.addr = alloca ptr, align 8, addrspace(5) # | %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr # | store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8 # | %p1 = load ptr, ptr addrspace(5) %p, align 8 # | store ptr %p1, ptr %p.addr.ascast, align 8 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load ptr, ptr %p.addr.ascast, align 8 # | %2 = load i32, ptr %1, align 4 # | %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4 # | %3 = load ptr, ptr %p.addr.ascast, align 8 # | store i32 %call, ptr %3, align 4 # | ret void # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1) # | br label %po_cont # | } # | # | declare i32 @__llvm_profile_sampling_gpu(i32) # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3 # | # | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64) # | # | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { nounwind } # | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #4 = { convergent nounwind "uniform-work-group-size" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 2, !"EnableValueProfiling", i32 0} # | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # | #0 0x000055d899538eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d899535e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d89953962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d14f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d14f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d14f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d14f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8994cebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d8994cea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d8994b38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d899162e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d899162b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d14f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d14f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d14f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d899162a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2368 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( # | ... # `---data was truncated (10240/51185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4c096aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4c0967e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4c096b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cabb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cabb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cabb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cabb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4c0900bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4c0900a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4c08e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4c0594e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4c0594b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9cabb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cabb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cabb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4c0594a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (2369 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/47728) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7074b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a7074ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a7074b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16a9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16a998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16a9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16a991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a707446bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a707446a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a70742b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a7070dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a7070dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16a991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16a991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16a991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7070daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (2370 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/43507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558eeaee4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558eeaee1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558eeaee562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5876933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f587698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5876933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f587691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558eeae7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558eeae7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558eeae5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558eeab0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558eeab0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f587691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f587691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f587691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558eeab0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (2371 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b78df6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b78df68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b78df6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85b9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85b96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85b9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85b9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b78df01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b78df01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b78dee68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b78db95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b78db95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85b9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85b96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85b96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b78db95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (2372 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579791f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005579791ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005579791f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd7b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd7b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd7b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd7b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557979186bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557979186a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055797916b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557978e1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557978e1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd7b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd7b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd7b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557978e1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (2373 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626d916aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626d9167e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626d916b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2890049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28900a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2890049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2890031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626d9100bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626d9100a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626d90e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626d8d94e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626d8d94b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2890032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28900330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28900330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626d8d94a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (2374 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056229284beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562292848e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056229284c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f021f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f021f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f021f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f021f231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622927e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622927e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622927c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562292475e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562292475b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f021f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f021f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f021f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562292475a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (2375 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055792dac7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055792dac4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055792dac862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31ff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31ff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31ff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31ff11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055792da5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055792da5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055792da428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055792d6f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055792d6f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31ff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31ff11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31ff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055792d6f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (2376 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056470c1eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056470c1e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056470c1eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1baf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1baf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1baf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1baf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056470c180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056470c180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056470c1658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056470be14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056470be14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1baf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1baf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1baf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056470be14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (2377 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055604817feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055604817ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055604818062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4735f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4735f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4735f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4735f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556048115bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556048115a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560480fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556047da9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556047da9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4735f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4735f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4735f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556047da9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (2378 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056289becbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056289bec8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056289becc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe06733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe0678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe06733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe0671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056289be61bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056289be61a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056289be468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056289baf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056289baf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe0671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe0671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe0671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056289baf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (2379 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563361035eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563361032e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056336103662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f359b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f359b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f359b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f359b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563360fcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563360fcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563360fb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563360c5fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563360c5fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f359b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f359b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f359b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563360c5fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (2380 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d85fc58eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d85fc55e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d85fc5962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc45133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc4518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc45133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc4511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d85fbeebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d85fbeea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d85fbd38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d85f882e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d85f882b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc4511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc4511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc4511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d85f882a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (2381 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601651e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005601651e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005601651e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9725a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9725aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9725a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9725a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056016517dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056016517da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005601651628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560164e11e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560164e11b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9725a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9725a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9725a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560164e11a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (2382 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp ule <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp sle <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp ule <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056355d9c4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056355d9c1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056355d9c562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48a2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48a20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48a2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48a2031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056355d95abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056355d95aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056355d93f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056355d5eee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056355d5eeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f48a2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48a20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48a20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056355d5eea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (2383 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629c58a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629c589ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629c58a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f314cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f314cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f314cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f314cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629c5837bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005629c5837a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629c581c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629c54cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629c54cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f314cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f314cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f314cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629c54cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (2384 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd409f1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd409eee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd409f262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c8c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c8c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c8c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c8c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd40987bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd40987a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd4096c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd4061be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd4061bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c8c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c8c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c8c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd4061ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (2385 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a4c2a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a4c2a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4c2a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f858e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f858e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f858e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f858e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4c23abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4c23aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a4c21f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a4becee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a4beceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f858e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f858e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f858e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a4becea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (2386 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, # | ... # `---data was truncated (10240/12298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d10b22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d10b1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d10b2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66ebd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66ebd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66ebd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66ebd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d10ab8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d10ab8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d10a9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d1074ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d1074cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f66ebd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66ebd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66ebd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d1074ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (2387 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noin # | ... # `---data was truncated (10240/25042) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056093f1c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056093f1c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056093f1ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23e8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23e84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23e8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23e8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056093f15fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056093f15fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056093f1448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056093edf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056093edf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23e8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23e84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23e84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056093edf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2388 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611257a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056112579ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611257a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8115b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8115b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8115b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8115b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561125737bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561125737a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056112571c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005611253cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005611253cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8115b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8115b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8115b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611253cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (2389 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (2390 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e19a9bdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e19a9bae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e19a9be62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e36333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e3638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e36333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e3631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e19a953bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e19a953a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e19a9388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e19a5e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e19a5e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e3631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e3631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e3631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e19a5e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (2391 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595844a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055958449ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595844a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfd8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfd8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfd8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfd8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559584437bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559584437a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055958441c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595840cbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595840cbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfd8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfd8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfd8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595840cba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (2392 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entr # | ... # `---data was truncated (10240/18361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1ebb10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1ebb0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1ebb1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc39fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc39fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc39fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc39fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1ebaa6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1ebaa6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1eba8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1eb73ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1eb73ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc39fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc39fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc39fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1eb73aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (2393 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e999bcfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e999bcce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e999bd062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f748d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f748d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f748d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f748d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e999b65bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e999b65a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e999b4a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e9997f9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e9997f9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f748d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f748d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f748d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9997f9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (2394 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8eb54feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8eb54ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8eb55062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18be105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18be15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18be105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18be0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8eb4e5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8eb4e5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8eb4ca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8eb179e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8eb179b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f18be0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18be0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18be0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8eb179a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2395 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653be4ffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653be4fce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653be50062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0835733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f083578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0835733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f083571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653be495bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653be495a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653be47a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653be129e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653be129b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f083571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f083571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f083571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653be129a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (2396 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i6 # | ... # `---data was truncated (10240/182165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b16a6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b16a6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b16a6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5d2431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b16a04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b16a04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b169e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b16698e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b16698b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5d24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b16698a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (2397 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560483931eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056048392ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056048393262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3c3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3c3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3c3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3c3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604838c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604838c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604838ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056048355be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056048355bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3c3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3c3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3c3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056048355ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (2398 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557864efaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557864ef7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557864efb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efde8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efde8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efde8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efde8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557864e90bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557864e90a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557864e758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557864b24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557864b24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efde8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efde8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efde8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557864b24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (2399 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (2400 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e68d29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e68d26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e68d2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bd3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bd3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bd3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bd3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e68cbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e68cbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e68ca48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e68953e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e68953b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bd3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bd3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bd3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e68953a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (2401 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %v # | ... # `---data was truncated (10240/23064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bdeff3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557bdeff0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557bdeff462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc36a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc36a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc36a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc36a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bdef89bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557bdef89a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557bdef6e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557bdec1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557bdec1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc36a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc36a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc36a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bdec1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (2402 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ce3607eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ce3604e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ce360862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc46e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc46ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc46e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc46e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ce359dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ce359da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ce35828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ce3231e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ce3231b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc46e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc46e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc46e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ce3231a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (2403 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f388baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f388b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f388bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5703f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5703f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5703f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5703f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f38850bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f38850a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f388358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f384e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f384e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5703f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5703f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5703f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f384e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (2404 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e57edaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e57ed7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e57edb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1576e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1576ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1576e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1576e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e57e70bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e57e70a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e57e558b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e57b04e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e57b04b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1576e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1576e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1576e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e57b04a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (2405 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/12433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ff8ca6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ff8ca3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ff8ca762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6757049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67570a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6757049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6757031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ff8c3cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ff8c3ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ff8c218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ff88d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ff88d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6757032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67570330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67570330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ff88d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (2406 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618815a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618815a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618815aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4c5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4c5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4c5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4c5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056188153fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056188153fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618815248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618811d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618811d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4c5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4c5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4c5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618811d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (2407 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = l # | ... # `---data was truncated (10240/23247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627c0953eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627c0950e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627c095462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7276b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7276b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7276b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7276b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627c08e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627c08e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627c08ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627c057de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627c057db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7276b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7276b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7276b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627c057da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (2408 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 # | ... # `---data was truncated (10240/32186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7738f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c7738efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c7738f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c67505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c6755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c67505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c674ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c773888bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c773888a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c77386d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c77351ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c77351cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c674eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c674ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c674ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c77351ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2409 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627b1d0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627b1d0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627b1d0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb410e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb410e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb410e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb410e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627b1ca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627b1ca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627b1c898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627b1938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627b1938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb410e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb410e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb410e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627b1938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (2410 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582084d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005582084d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005582084d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae16249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae162a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae16249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae16231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055820846bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055820846ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582084508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582080ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582080ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fae16232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae162330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae162330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582080ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2411 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e455719eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e455716e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e45571a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9bba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9bbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9bba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9bba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4556afbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4556afa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4556948b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e455343e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e455343b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9bba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9bba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9bba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e455343a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (2412 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ecc65a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ecc65a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ecc65a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff328f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff328f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff328f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff328f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ecc653dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ecc653da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ecc65228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ecc61d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ecc61d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff328f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff328f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff328f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ecc61d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (2413 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eed93c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eed93bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eed93c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe30c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe30c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe30c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe30c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eed9357bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eed9357a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eed933c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eed8febe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eed8febb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe30c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe30c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe30c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eed8feba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (2414 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2415 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/40411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bae4b91eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bae4b8ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bae4b9262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f188d61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f188d6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f188d61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f188d603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bae4b27bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bae4b27a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bae4b0c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bae47bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bae47bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f188d604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f188d6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f188d6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bae47bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (2416 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9cbe0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9cbe08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9cbe0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1532c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1532ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1532c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1532c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9cbda1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9cbda1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9cbd868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9cba35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9cba35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1532c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1532c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1532c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9cba35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (2417 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (2418 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp uge <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp uge <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp uge <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597cac35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005597cac32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005597cac3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a6ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a6eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a6ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a6ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597cabcbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005597cabcba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005597cabb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005597ca85fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005597ca85fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a6ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a6ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a6ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597ca85fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (2419 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630f3e59eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630f3e56e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630f3e5a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cc5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cc5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cc5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cc5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630f3defbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630f3defa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630f3dd48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630f3a83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630f3a83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4cc5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cc5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cc5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630f3a83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (2420 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b18cfd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b18cfcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b18cfd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1426c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1426ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1426c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1426c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b18cf66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b18cf66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b18cf4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b18cbfae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b18cbfab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1426c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1426c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1426c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b18cbfaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (2421 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2574dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2574d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2574dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaa6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaa62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaa6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaa6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b257471bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b257471a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2574568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b257105e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b257105b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffaa6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaa62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaa62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b257105a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (2422 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i) # | store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i) # | store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055a4d5d40eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4d5d3de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4d5d4162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3565933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f356598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3565933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f356591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4d5cd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4d5cd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4d5cbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4d596ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4d596ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f356591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f356591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f356591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4d596aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (2423 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/12688) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dcd71beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556dcd718e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556dcd71c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa3c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa3c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa3c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa3c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dcd6b1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556dcd6b1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556dcd6968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556dcd345e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556dcd345b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa3c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa3c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa3c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dcd345a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (2424 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a68c760eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a68c75de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a68c76162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84e6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84e62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84e6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84e6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a68c6f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a68c6f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a68c6db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a68c38ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a68c38ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f84e6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84e62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84e62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a68c38aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (2425 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cc1916eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cc1913e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cc191762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14c1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14c198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14c1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14c191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cc18acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cc18aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cc18918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cc1540e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cc1540b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f14c191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14c191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14c191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cc1540a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (2426 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/101483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcb3609eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcb3606e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcb360a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb012133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb01218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb012133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb01211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcb359fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcb359fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcb35848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcb3233e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcb3233b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb01211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb01211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb01211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcb3233a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (2427 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556141888eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556141885e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055614188962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60fb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60fb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60fb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60fb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055614181ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055614181ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561418038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561414b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561414b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60fb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60fb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60fb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561414b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (2428 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, a # | ... # `---data was truncated (10240/43486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055faa8b36eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055faa8b33e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055faa8b3762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9901c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9901ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9901c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9901c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faa8accbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055faa8acca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055faa8ab18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055faa8760e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055faa8760b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9901c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9901c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9901c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faa8760a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (2429 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ecb253eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561ecb250e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561ecb25462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0841f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0841f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0841f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0841f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ecb1e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561ecb1e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561ecb1ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561ecae7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561ecae7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0841f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0841f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0841f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ecae7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (2430 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558178e1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558178e17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558178e1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94d661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94d66725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94d661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94d6603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558178db0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558178db0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558178d958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558178a44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558178a44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94d6604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94d66050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94d66050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558178a44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (2431 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c43b046eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c43b043e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c43b04762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1997333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f199738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1997333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f199731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c43afdcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c43afdca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c43afc18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c43ac70e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c43ac70b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f199731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f199731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f199731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c43ac70a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (2432 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c27ea5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c27ea2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c27ea662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcb3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcb3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcb3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcb3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c27e3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c27e3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c27e208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c27acfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c27acfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcb3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcb3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcb3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c27acfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (2433 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, ali # | ... # `---data was truncated (10240/58334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e96012eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e9600fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e9601362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9456049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94560a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9456049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9456031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e95fa8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e95fa8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e95f8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e95c3ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e95c3cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9456032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94560330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94560330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e95c3ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (2434 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, al # | ... # `---data was truncated (10240/72135) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63554beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c635548e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c63554c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd90933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd9098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd90933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd9091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6354e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6354e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6354c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c635175e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c635175b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd9091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd9091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd9091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c635175a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (2435 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd53b8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd53b8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd53b9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2edb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2edb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2edb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2edb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd53b25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd53b25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd53b0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd537b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd537b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd2edb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2edb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2edb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd537b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (2436 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618f2264eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005618f2261e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005618f226562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3643133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f364318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3643133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f364311b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618f21fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005618f21faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005618f21df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005618f1e8ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005618f1e8eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f364311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f364311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f364311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618f1e8ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-fma.c (2437 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-none-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %accum.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %accum, ptr %accum.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %accum.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %accum.addr = alloca <4 x float>, align 8 # | %lhs.addr = alloca <4 x float>, align 8 # | %rhs.addr = alloca <4 x float>, align 8 # | store <4 x float> %accum, ptr %accum.addr, align 8 # | store <4 x float> %lhs, ptr %lhs.addr, align 8 # | store <4 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x float>, ptr %accum.addr, align 8 # | %1 = load <4 x float>, ptr %lhs.addr, align 8 # | %2 = load <4 x float>, ptr %rhs.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store <4 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %10, ptr %__ret.i, align 8 # | %11 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <2 x float>, align 8 # | %__p1.addr.i.i = alloca <2 x float>, align 8 # | %__p2.addr.i.i = alloca <2 x float>, align 8 # | %__ret.i.i = alloca <2 x float>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | store <2 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <2 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <2 x float> %7, ptr %__p2.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %11 = bitcast <8 x i8> %8 to <2 x float> # | %12 = bitcast <8 x i8> %9 to <2 x float> # | %13 = bitcast <8 x i8> %10 to <2 x float> # | %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11) # | store <2 x float> %14, ptr %ref.tmp.i.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8 # | store <2 x float> %15, ptr %__ret.i.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i.i, align 8 # | store <2 x float> %16, ptr %__ret.i, align 8 # | %17 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x float>, align 8 # | %__p1.addr.i.i = alloca <4 x float>, align 8 # | %__p2.addr.i.i = alloca <4 x float>, align 8 # | %__ret.i.i = alloca <4 x float>, align 8 # | %ref.tmp.i.i = alloca <16 x i8>, align 8 # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 8 # | %.compoundliteral.i = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 8 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <4 x float> %9, ptr %__p2.addr.i.i, align 8 # | %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8 # | %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8 # | %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8 # | %13 = bitcast <16 x i8> %10 to <4 x float> # | %14 = bitcast <16 x i8> %11 to <4 x float> # | %15 = bitcast <16 x i8> %12 to <4 x float> # | %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13) # | store <4 x float> %16, ptr %ref.tmp.i.i, align 8 # | %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8 # | store <4 x float> %17, ptr %__ret.i.i, align 8 # | %18 = load <4 x float>, ptr %__ret.i.i, align 8 # | store <4 x float> %18, ptr %__ret.i, align 8 # | %19 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %19 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557b67ff4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557b67ff1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557b67ff562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdddef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdddef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdddef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdddef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b67f8abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557b67f8aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557b67f6f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557b67c1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557b67c1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdddef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdddef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdddef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b67c1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (2438 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/22074) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aecd144eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aecd141e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aecd14562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3297049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32970a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3297049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3297031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aecd0dabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aecd0daa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aecd0bf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aeccd6ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aeccd6eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3297032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32970330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32970330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aeccd6ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (2439 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ad8971eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ad896ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ad897262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9d611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ad8907bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ad8907a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ad88ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ad859be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ad859bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9d611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ad859ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (2440 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559907f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559907efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559907f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc93105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc9315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc93105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc930ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555990788bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555990788a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055599076d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055599041ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055599041cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc930eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc930ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc930ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055599041ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (2441 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 # | ... # `---data was truncated (10240/15508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600665b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600665b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600665b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca28333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca2838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca28333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca2831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056006654dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056006654da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600665328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600661e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600661e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca2831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca2831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca2831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600661e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (2442 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f9a21c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f9a21c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f9a21c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8040c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8040ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8040c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8040c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9a2159bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f9a2159a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f9a213e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f9a1dede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f9a1dedb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8040c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8040c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8040c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9a1deda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (2443 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbca779eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbca776e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbca77a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4cb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4cb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4cb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4cb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbca70fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbca70fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbca6f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbca3a3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbca3a3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4cb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4cb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4cb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbca3a3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (2444 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055badd92deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055badd92ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055badd92e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabf8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabf858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabf8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabf851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055badd8c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055badd8c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055badd8a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055badd557e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055badd557b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fabf851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabf851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabf851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055badd557a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (2445 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | % # | ... # `---data was truncated (10240/21774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056125488eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056125488be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056125488f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4680049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46800a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4680049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4680031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561254824bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561254824a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612548098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612544b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612544b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4680032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46800330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46800330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612544b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (2446 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vs # | ... # `---data was truncated (10240/10886) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a108d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a108d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a108d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f940d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f940d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f940d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f940d631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a1086bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a1086ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a108508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a104ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a104ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f940d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f940d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f940d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a104ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (2447 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556131d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556131cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556131d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc93333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc9338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc93333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc9331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556131c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556131c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556131c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055613192ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055613192ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc9331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc9331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc9331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055613192aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2448 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e414a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e414a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e414aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd612333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd61238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd612333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd61231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e4143fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e4143fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e414248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e410d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e410d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd61231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd61231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd61231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e410d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (2449 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2450 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (2451 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f4be16eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562f4be13e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562f4be1762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe37933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe3798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe37933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe3791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f4bdacbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562f4bdaca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562f4bd918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562f4ba40e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562f4ba40b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbe3791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe3791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe3791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f4ba40a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (2452 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad93641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad9363ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad9364262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f922f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f922f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f922f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f922f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad935d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad935d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad935bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad9326be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad9326bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f922f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f922f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f922f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad9326ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (2453 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ae004deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ae004ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ae004e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f333b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f333b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f333b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f333b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559adffe3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559adffe3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559adffc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559adfc77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559adfc77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f333b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f333b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f333b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559adfc77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (2454 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2455 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2a640ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d2a6409e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d2a640d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff013f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff013f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff013f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff013f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2a63a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2a63a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2a63878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d2a6036e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d2a6036b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff013f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff013f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff013f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2a6036a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (2456 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be9b74ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be9b749e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be9b74d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2182449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21824a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2182449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2182431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be9b6e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be9b6e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be9b6c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be9b376e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be9b376b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2182432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21824330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21824330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be9b376a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-multi-module.ll (2457 of 27910) ******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # | #0 0x000055d7a6784eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7a6781e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7a678562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb2cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb2cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb2cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb2ceed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7a671abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7a671aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7a66ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7a63aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7a63aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb2ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb2ceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb2ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7a63aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (2458 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d24ca51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d24ca4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d24ca5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff20bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff20bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff20bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff20bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d24c9e7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d24c9e7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d24c9cc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d24c67be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d24c67bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff20bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff20bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff20bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d24c67ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (2459 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.a # | ... # `---data was truncated (10240/41678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629596a9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005629596a6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005629596aa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcce281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcce28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcce281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcce2803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056295963fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056295963fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629596248b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005629592d3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005629592d3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcce2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcce28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcce28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629592d3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtin-align.c (2460 of 27910) ******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | @aligned_true = global i8 1, align 1 # | @aligned_false = global i8 0, align 1 # | @down_1 = global i32 992, align 4 # | @down_2 = global i32 256, align 4 # | @up_1 = global i32 1024, align 4 # | @up_2 = global i32 256, align 4 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @get_type() #0 { # | entry: # | ret ptr null # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %src_addr = ptrtoint ptr %0 to i64 # | %set_bits = and i64 %src_addr, %mask # | %is_aligned = icmp eq i64 %set_bits, 0 # | ret i1 %is_aligned # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005631c3fe8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631c3fe5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631c3fe962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4455649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4455649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4455631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631c3f7ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631c3f7ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631c3f638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631c3c12e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631c3c12b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4455632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44556330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631c3c12a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (2461 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562abf94ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562abf949e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562abf94d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0476733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f047678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0476733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f047671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562abf8e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562abf8e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562abf8c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562abf576e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562abf576b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f047671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f047671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f047671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562abf576a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (2462 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i) # | %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8> # | store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i) # | %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8> # | store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i) # | %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8> # | store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i) # | %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8> # | store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056155c2b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056155c2b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056155c2b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0241105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f024115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0241105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02410ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056155c24dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056155c24da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056155c2328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056155bee1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056155bee1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02410eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02410ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02410ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056155bee1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-arm64.c (2463 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load ptr, ptr %b.addr, align 8 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @tp() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbitl(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.bitreverse.i64(i64) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbit64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @hints() #0 { # | entry: # | call void @llvm.aarch64.hint(i32 0) # | call void @llvm.aarch64.hint(i32 1) # | call void @llvm.aarch64.hint(i32 2) # | call void @llvm.aarch64.hint(i32 3) # | call void @llvm.aarch64.hint(i32 4) # | call void @llvm.aarch64.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.aarch64.hint(i32) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @barriers() #0 { # | entry: # | call void @llvm.aarch64.dmb(i32 1) # | call void @llvm.aarch64.dsb(i32 2) # | call void @llvm.aarch64.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dmb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dsb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.isb(i32) #5 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch_x() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @read_intent_prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch.ir(ptr null) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @jcvt(double noundef %v) #7 { # | entry: # | %v.addr = alloca double, align 8 # | store double %v, ptr %v.addr, align 8 # | %0 = load double, ptr %v.addr, align 8 # | %1 = call i32 @llvm.aarch64.fjcvtzs(double %0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.fjcvtzs(double) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rsr() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = trunc i64 %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nounwind # | declare i64 @llvm.read_volatile_register.i64(metadata) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rsr64() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @rsrp() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = inttoptr i64 %0 to ptr # | ret ptr %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %1 = zext i32 %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: nocallback nounwind # | declare void @llvm.write_register.i64(metadata, i64) #8 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr64(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | call void @llvm.write_register.i64(metadata !7, i64 %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsrp(ptr noundef %v) #0 { # | entry: # | %v.addr = alloca ptr, align 8 # | store ptr %v, ptr %v.addr, align 8 # | %0 = load ptr, ptr %v.addr, align 8 # | %1 = ptrtoint ptr %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cls(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %cls = call i32 @llvm.aarch64.cls(i32 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsl(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls64(i64) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsll(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndr(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndr() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndr() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndrrs() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndrrs() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @trap() #0 { # | entry: # | call void @llvm.aarch64.break(i32 42) # | ret void # | } # | # | ; Function Attrs: cold noreturn nounwind # | declare void @llvm.aarch64.break(i32 immarg) #10 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca i64, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8 # | %2 = load ptr, ptr %a.addr, align 8 # | %3 = load i64, ptr %b.addr, a # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 243 | __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint # | | ^ ~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type] # | 305 | __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type] # | 306 | __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type] # | 307 | __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH); # | | ^ ~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 308 | return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5); # | | ^ ~ # | 5 warnings generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055588a295eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055588a292e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055588a29662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bd4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bd478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bd4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bd471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055588a22bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055588a22ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055588a2108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555889ebfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555889ebfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2bd471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bd471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bd471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555889ebfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (2464 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/11958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bdae41aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bdae417e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bdae41b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9feb305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9feb35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9feb305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9feb2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bdae3b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bdae3b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bdae3958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bdae044e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bdae044b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9feb2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9feb2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9feb2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bdae044a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (2465 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (2466 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/51751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d146b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d146b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d146b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04e6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04e658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04e6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04e651b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d1464bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d1464ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d146308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d142dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d142dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04e651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04e651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04e651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d142dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (2467 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/153905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055602b9bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055602b9b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055602b9bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54d9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54d918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54d9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54d911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055602b952bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055602b952a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055602b9378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055602b5e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055602b5e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54d911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54d911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54d911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055602b5e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (2468 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef9d040eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ef9d03de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ef9d04162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3443705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f344375c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3443705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34436ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef9cfd6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ef9cfd6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ef9cfbb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ef9cc6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ef9cc6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34436eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34436ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34436ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef9cc6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (2469 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0edf52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0edf4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0edf5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d7821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d782725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d7821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d78203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0edee8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0edee8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0edecd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0edb7ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0edb7cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d78204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d782050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d782050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0edb7ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (2470 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608037e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005608037e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005608037e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65ff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65ff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65ff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65ff431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056080377abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056080377aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056080375f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056080340ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056080340eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65ff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65ff4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65ff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056080340ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (2471 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8f42e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8f42e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8f42ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eb9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eb918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eb9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eb911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8f427fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8f427fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8f42648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8f3f13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8f3f13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4eb911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eb911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eb911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f3f13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (2472 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1ac4abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1ac4a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1ac4ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ef5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ef58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ef5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ef5831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1ac441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1ac441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1ac4268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1ac0d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1ac0d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ef5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ef58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ef58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1ac0d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (2473 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055def5ae9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055def5ae6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055def5aea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c92305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c9235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c92305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c922ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055def5a7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055def5a7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055def5a648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055def5713e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055def5713b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c922eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c922ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c922ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055def5713a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (2474 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560eb7eb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560eb7eb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560eb7eb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dbb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7dbb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dbb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dbb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560eb7e4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560eb7e4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560eb7e318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560eb7ae0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560eb7ae0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7dbb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dbb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dbb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560eb7ae0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2475 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, # | ... # `---data was truncated (10240/29451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbda4faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbda4f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbda4fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff6b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff6b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff6b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff6b803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbda490bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbda490a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbda4758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbda124e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbda124b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff6b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff6b8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff6b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbda124a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (2476 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2477 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (2478 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", , 2) %src) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 8 # | %1 = call @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", , 2) %dest, %val) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %val.addr = alloca , align 8 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 8 # | store %val, ptr %val.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 8 # | %1 = load , ptr %val.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2) %0, %1, i32 1) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fd0d6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fd0d69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fd0d6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4372849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43728a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4372849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4372831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fd0d02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fd0d02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fd0ce78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fd0996e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fd0996b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4372832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43728330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43728330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fd0996a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (2479 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056174b435eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056174b432e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056174b43662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f433dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f433dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f433dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f433dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056174b3cbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056174b3cba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056174b3b08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056174b05fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056174b05fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f433dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f433dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f433dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056174b05fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (2480 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd2225feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd2225ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd2226062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f0fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f0fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f0fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f0fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd221f5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd221f5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd221da8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd21e89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd21e89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f0fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f0fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f0fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd21e89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (2481 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1f5637eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d1f5634e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d1f563862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c7b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c7b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c7b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c7b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1f55cdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d1f55cda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d1f55b28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d1f5261e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d1f5261b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c7b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c7b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c7b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1f5261a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (2482 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdb0f07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdb0f04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdb0f0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f417b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f417b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f417b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f417b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdb0e9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdb0e9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdb0e828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdb0b31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdb0b31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f417b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f417b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f417b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdb0b31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (2483 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (2484 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (2485 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (2486 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f15754eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f15751e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f1575562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb77b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb77b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb77b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb77b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f156eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f156eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f156cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f1537ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f1537eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb77b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb77b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb77b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f1537ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (2487 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, alig # | ... # `---data was truncated (10240/32578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5f8b1deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d5f8b1ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d5f8b1e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1bef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1bef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1bef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1bef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5f8ab3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d5f8ab3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d5f8a988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d5f8747e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d5f8747b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1bef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1bef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1bef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5f8747a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (2488 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 # | ... # `---data was truncated (10240/67006) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b701133eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b701130e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b70113462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d0e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d0e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d0e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d0e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7010c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7010c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7010ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b700d5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b700d5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d0e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d0e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d0e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b700d5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (2489 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0f62e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0f62dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0f62e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b1f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b1f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b1f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b1f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0f6277bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0f6277a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0f625c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0f5f0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0f5f0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b1f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b1f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b1f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0f5f0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (2490 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055676a14deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055676a14ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055676a14e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3074733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f307478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3074733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f307471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055676a0e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055676a0e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055676a0c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556769d77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556769d77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f307471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f307471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f307471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556769d77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (2491 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | # | ... # `---data was truncated (10240/34641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb70185eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb70182e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb7018662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9d6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9d64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9d6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9d6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb7011bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb7011ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb701008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb6fdafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb6fdafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9d6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9d64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9d64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb6fdafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (2492 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606406b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005606406b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005606406b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa6c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa6c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa6c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa6c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056064064ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056064064ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005606406338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005606402e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005606402e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa6c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa6c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa6c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606402e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (2493 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 # | ... # `---data was truncated (10240/32570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c89badeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c89baae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c89bae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b6ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b6ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b6ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b6ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c89b43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c89b43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c89b288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c897d7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c897d7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9b6ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b6ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b6ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c897d7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (2494 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578a4d00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005578a4cfde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005578a4d0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb775533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb77558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb775533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb77551b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578a4c96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578a4c96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578a4c7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578a492ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578a492ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb77551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb77551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb77551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578a492aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (2495 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561557587eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561557584e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056155758862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50b3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50b318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50b3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50b311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056155751dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056155751da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615575028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615571b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615571b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50b311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50b311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50b311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615571b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (2496 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562681713eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562681710e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056268171462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fd381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fd38725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fd381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fd3803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626816a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626816a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056268168e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056268133de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056268133db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fd3804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fd38050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fd38050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056268133da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (2497 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ae6d7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ae6d79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ae6d7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda3d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda3d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda3d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda3d831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ae6d12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ae6d12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ae6cf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ae69a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ae69a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda3d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda3d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda3d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ae69a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (2498 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d818a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d818a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d818a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9cef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9cef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9cef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9cef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d81839bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d81839a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d8181e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d814cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d814cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9cef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9cef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9cef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d814cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (2499 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581cf4fdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581cf4fae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581cf4fe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb150333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb15038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb150333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb15031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581cf493bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581cf493a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581cf4788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581cf127e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581cf127b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb15031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb15031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb15031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581cf127a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (2500 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d884b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d884b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d884b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe070d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe070d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe070d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe070d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d8844bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d8844ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d884308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d880dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d880dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe070d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe070d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe070d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d880dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (2501 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cb4c9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557cb4c9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557cb4ca062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9662133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f966218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9662133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f966211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cb4c35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557cb4c35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557cb4c1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557cb48c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557cb48c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f966211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f966211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f966211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cb48c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (2502 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad72e8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad72e88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad72e8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0553f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0553f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0553f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0553eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad72e21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad72e21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad72e068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad72ab5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad72ab5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0553eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0553eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0553eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad72ab5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (2503 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (2504 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64 # | ... # `---data was truncated (10240/29259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056441b2c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056441b2c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056441b2c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8aa733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8aa78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8aa733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8aa71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056441b25bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056441b25ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056441b2408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056441aeefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056441aeefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8aa71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8aa71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8aa71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056441aeefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (2505 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a68aaefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a68aaece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a68aaf062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8be0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8be0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8be0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8be0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a68aa85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a68aa85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a68aa6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a68a719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a68a719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8be0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8be0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8be0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a68a719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/packed-structure.c (2506 of 27910) ******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | %struct.s0 = type { i32, i32 } # | %struct.s1 = type { i32, i32 } # | %struct.s2 = type { i32, i32 } # | %struct.s3 = type <{ i16, i32, [10 x i8] }> # | # | @s0_align_x = global i32 4, align 4 # | @s0_align_y = global i32 1, align 4 # | @s0_align = global i32 4, align 4 # | @s1_align_x = global i32 1, align 4 # | @s1_align_y = global i32 1, align 4 # | @s1_align = global i32 1, align 4 # | @s2_align_x = global i32 2, align 4 # | @s2_align_y = global i32 2, align 4 # | @s2_align = global i32 2, align 4 # | @s3_1 = global i32 1, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @test3(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %anInt, align 2 # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # | #0 0x000055fb5e3c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb5e3c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb5e3c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd78b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd78b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb5e35bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb5e35ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb5e3408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb5dfefe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb5dfefb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd78b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb5dfefa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (2507 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056419184eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056419184be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056419184f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2303533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f230358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2303533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f230351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641917e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641917e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641917c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564191478e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564191478b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f230351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f230351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f230351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564191478a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2508 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559de072deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559de072ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559de072e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09cd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09cd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09cd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09cd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559de06c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559de06c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559de06a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559de0357e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559de0357b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f09cd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09cd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09cd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559de0357a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (2509 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | de # | ... # `---data was truncated (10240/12091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613310b0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613310ade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613310b162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7918533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f791858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7918533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f791851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561331046bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561331046a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056133102b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561330cdae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561330cdab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f791851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f791851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f791851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561330cdaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (2510 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | ... # `---data was truncated (10240/30866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588829f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588829ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588829f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7af0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7af0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7af0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7af0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558882986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558882986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055888296b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055888261ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055888261ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7af0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7af0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7af0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055888261aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (2511 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b35cdd0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b35cdcde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b35cdd162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f641001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64100725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f641001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6410003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b35cd66bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b35cd66a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b35cd4b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b35c9fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b35c9fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6410004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64100050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64100050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b35c9faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (2512 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, # | ... # `---data was truncated (10240/47764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562502998eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562502995e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056250299962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e03e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e03ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e03e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e03e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056250292ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056250292ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005625029138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005625025c2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005625025c2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e03e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e03e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e03e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625025c2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (2513 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e44ce68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e44ce65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e44ce6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb009933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb00998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb009933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb00991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e44cdfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e44cdfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e44cde38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e44ca92e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e44ca92b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb00991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb00991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb00991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e44ca92a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (2514 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | # | ... # `---data was truncated (10240/19123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056281fe73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056281fe70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056281fe7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f355c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f355c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f355c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f355c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056281fe09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056281fe09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056281fdee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056281fa9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056281fa9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f355c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f355c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f355c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056281fa9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (2515 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (2516 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555c2991eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555c298ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555c299262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23aae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23aaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23aae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23aae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555c2927bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555c2927a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555c290c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555c25bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555c25bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f23aae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23aae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23aae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555c25bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (2517 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0807bbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0807b8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0807bc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc14aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc14aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc14aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc14aa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a080751bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a080751a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0807368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0803e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0803e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc14aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc14aa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc14aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0803e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (2518 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610d7127eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610d7124e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610d712862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa15ae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa15ae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa15ae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa15ae03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610d70bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610d70bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610d70a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610d6d51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610d6d51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa15ae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa15ae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa15ae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610d6d51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (2519 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1 # | store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %5, ptr %__ret, align 16 # | %6 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %6, ptr %tmp, align 16 # | %7 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0 # | store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %5, ptr %__ret, align 8 # | %6 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %6, ptr %tmp, align 8 # | %7 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca # | ... # `---data was truncated (10240/14230) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005568ea0f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568ea0efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568ea0f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c86933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c8698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c86933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c8691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568ea088bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568ea088a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568ea06d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568e9d1ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568e9d1cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c8691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c8691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c8691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568e9d1ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (2520 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align # | ... # `---data was truncated (10240/39586) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd050baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd050b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd050bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99cab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99cab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99cab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99cab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd05050bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd05050a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd050358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd04ce4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd04ce4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99cab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99cab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99cab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd04ce4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (2521 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (2522 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f34285eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f34282e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f3428662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb3b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb3b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb3b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb3b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f3421bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f3421ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f342008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f33eafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f33eafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb3b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb3b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb3b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f33eafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (2523 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.ad # | ... # `---data was truncated (10240/16274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3eb19ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c3eb199e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c3eb19d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e90d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e90d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e90d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e90d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3eb132bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c3eb132a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c3eb1178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c3eadc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c3eadc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e90d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e90d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e90d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3eadc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-vget.c (2524 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x float> @low_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr # | ... # `---data was truncated (10240/15571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556347fadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556347faae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556347fae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31ecb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31ecb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31ecb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31ecaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556347f43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556347f43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556347f288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556347bd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556347bd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f31ecaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31ecaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31ecaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556347bd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (2525 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613f2722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613f271fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613f272362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa55dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa55dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa55dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa55dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613f26b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613f26b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613f269d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613f234ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613f234cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa55dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa55dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa55dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613f234ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2526 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585a8c12eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005585a8c0fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005585a8c1362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e0ea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e0ea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e0ea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e0ea03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585a8ba8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005585a8ba8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005585a8b8d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005585a883ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005585a883cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3e0ea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e0ea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e0ea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585a883ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (2527 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b80236beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b802368e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b80236c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3ce049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3ce0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3ce049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3ce031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b802301bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b802301a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8022e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b801f95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b801f95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3ce032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3ce0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3ce0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b801f95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (2528 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2529 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056051c850eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056051c84de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056051c85162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe44dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe44dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe44dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe44dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056051c7e6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056051c7e6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056051c7cb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056051c47ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056051c47ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe44dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe44dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe44dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056051c47aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (2530 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6b94c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6b94c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6b94c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59d2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59d22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59d2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59d2231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6b945cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6b945ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6b94418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6b90f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6b90f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f59d2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59d22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59d22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6b90f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (2531 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align # | ... # `---data was truncated (10240/18311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d48498ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d484989e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d48498d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f057f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f057f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f057f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f057f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d484922bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d484922a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d4849078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d4845b6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d4845b6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f057f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f057f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f057f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4845b6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (2532 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (2533 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584dfc2aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005584dfc27e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005584dfc2b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38b6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584dfbc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584dfbc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005584dfba58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005584df854e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005584df854b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584df854a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (2534 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd0733aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd07337e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd0733b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7a4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7a42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7a4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7a4231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd072d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd072d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd072b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd06f64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd06f64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe7a4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7a42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7a42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd06f64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (2535 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebb83d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebb83cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebb83d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fc9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fc90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fc9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fc9031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebb8367bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebb8367a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebb834c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebb7ffbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebb7ffbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9fc9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fc90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fc90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebb7ffba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (2536 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (2537 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055761fd77eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055761fd74e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055761fd7862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb5dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb5dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb5dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb5dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055761fd0dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055761fd0da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055761fcf28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055761f9a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055761f9a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbb5dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb5dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb5dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055761f9a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (2538 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (2539 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c191e62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c191e5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c191e6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf00b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf00b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf00b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf00b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c191df8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c191df8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c191ddd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c191a8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c191a8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf00b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf00b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf00b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c191a8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (2540 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558275279eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558275276e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055827527a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f50e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f50ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f50e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f50e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055827520fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055827520fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005582751f48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558274ea3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558274ea3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f50e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f50e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f50e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558274ea3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (2541 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562596ffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562596ff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562596ffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd6d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd6d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd6d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd6d003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562596f91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562596f91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562596f768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562596c25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562596c25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd6d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd6d0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd6d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562596c25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (2542 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563443e4deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563443e4ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563443e4e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5cc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5cc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5cc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5cc231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563443de3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563443de3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563443dc88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563443a77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563443a77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5cc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5cc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5cc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563443a77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (2543 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c5730ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c57309e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c5730d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91deb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91deb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91deb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91deb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c572a2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c572a2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c572878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c56f36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c56f36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91deb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91deb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91deb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c56f36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (2544 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (2545 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (2546 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, a # | ... # `---data was truncated (10240/13410) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed88b85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed88b82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed88b8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed88b1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed88b1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed88b008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed887afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed887afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbef0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed887afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2547 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align # | ... # `---data was truncated (10240/19041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562235266eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562235263e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056223526762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe094933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe09498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe094933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe09491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622351fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005622351fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005622351e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562234e90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562234e90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe09491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe09491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe09491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562234e90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (2548 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/18895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1cf3ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1cf3cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1cf3cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5877133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f587718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5877133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f587711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1cf364bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a1cf364a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a1cf3498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1ceff8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1ceff8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f587711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f587711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f587711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1ceff8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (2549 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec8af34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec8af31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec8af3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6866933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f686698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6866933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f686691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec8aecabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec8aecaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec8aeaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec8ab5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec8ab5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f686691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f686691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f686691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec8ab5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (2550 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (2551 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1) # | ret float %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1) # | ret double %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1) # | ret float %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1) # | ret double %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1) # | ret float %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1) # | ret double %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1) # | ret float %frint64x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1) # | ret double %frint64x.i # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32x.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64x.f64(double) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055afe13dbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055afe13d8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055afe13dc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe76f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe76f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe76f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe76f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afe1371bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055afe1371a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055afe13568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055afe1005e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055afe1005b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe76f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe76f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe76f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afe1005a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (2552 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615fb67feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615fb67ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615fb68062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b11e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b11ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b11e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b11e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615fb615bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615fb615a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615fb5fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615fb2a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615fb2a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1b11e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b11e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b11e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615fb2a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-poly-add.c (2553 of 27910) ******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | store <8 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <4 x i16> # | store <4 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <1 x i64> # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | store <16 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <16 x i8>, ptr %ref.tmp.i, align 8 # | store <16 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <16 x i8>, ptr %__ret.i, align 8 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | store <8 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <8 x i16> # | store <8 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 8 # | store <8 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i16>, ptr %__ret.i, align 8 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 8 # | %__p1.addr.i = alloca <2 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = load <2 x i64>, ptr %b.addr, align 8 # | store <2 x i64> %0, ptr %__p0.addr.i, align 8 # | store <2 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | store <2 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i64>, ptr %ref.tmp.i, align 8 # | store <2 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i64>, ptr %__ret.i, align 8 # | ret <2 x i64> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ea0e659eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea0e656e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea0e65a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8718b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8718b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8718b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8718b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea0e5efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea0e5efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea0e5d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea0e283e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea0e283b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8718b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8718b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8718b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea0e283a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2554 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i # | ... # `---data was truncated (10240/14644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8ddf1ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8ddf19e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8ddf1d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0edaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0edaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0edaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0edaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8ddeb2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8ddeb2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8dde978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8ddb46e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8ddb46b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0edaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0edaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0edaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8ddb46a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2555 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559888411eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055988840ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055988841262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa560b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa560b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa560b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa560b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598883a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598883a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055988838c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055988803be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055988803bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa560b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa560b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa560b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055988803ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (2556 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619696d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619696d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619696d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f9e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f9e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f9e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f9e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056196966cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056196966ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619696518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561969300e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561969300b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f9e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f9e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f9e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561969300a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (2557 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> # | ... # `---data was truncated (10240/16951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056273958beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562739588e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056273958c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd30b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd30b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd30b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd30b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562739521bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562739521a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627395068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627391b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627391b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efd30b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd30b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd30b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627391b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (2558 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005651cfdcdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005651cfdcae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005651cfdce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec5a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec5a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec5a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec5a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651cfd63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651cfd63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651cfd488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651cf9f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651cf9f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec5a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec5a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec5a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651cf9f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2559 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c739872eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c73986fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c73987362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50fc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50fc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50fc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50fc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c739808bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c739808a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7397ed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c73949ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c73949cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f50fc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50fc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50fc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c73949ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2560 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610e80e6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610e80e3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610e80e762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2c5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2c538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2c5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2c531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610e807cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610e807ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610e80618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610e7d10e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610e7d10b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb2c531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2c531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2c531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610e7d10a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2561 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2a76c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c2a76bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c2a76c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bdac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bdaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bdac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bdac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2a7658bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c2a7658a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c2a763d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c2a72ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c2a72ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1bdac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bdac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bdac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2a72eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (2562 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560343f63eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560343f60e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560343f6462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5313c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5313c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5313c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5313c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560343ef9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560343ef9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560343ede8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560343b8de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560343b8db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5313c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5313c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5313c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560343b8da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (2563 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce36b4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce36b4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce36b5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a63933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a6398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a63933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a6391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce36ae5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce36ae5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce36aca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce36779e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce36779b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a6391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a6391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a6391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce36779a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (2564 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d50f59ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d50f599e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d50f59d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd154105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd15415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd154105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1540ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d50f532bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d50f532a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d50f5178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d50f1c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d50f1c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1540eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1540ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1540ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d50f1c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (2565 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d49d256eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d49d253e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d49d25762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a6ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a6ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a6ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a6feed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d49d1ecbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d49d1eca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d49d1d18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d49ce80e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d49ce80b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a6feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a6feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a6feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d49ce80a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (2566 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ce60f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ce60f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ce60fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38b5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38b558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38b5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38b551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ce608fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ce608fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ce60748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ce5d23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ce5d23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f38b551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38b551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38b551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ce5d23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (2567 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabi" # | # | %struct.Simple = type { i8, i8 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldrex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldaex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_strex(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %res = alloca i32, align 4 # | %var = alloca %struct.Simple, align 1 # | %tmp = alloca i64, align 8 # | %tmp8 = alloca double, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store i32 0, ptr %res, align 4 # | call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false) # | %0 = load ptr, ptr %addr.addr, align 4 # | %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0) # | %1 = load i32, ptr %res, align 4 # | %or = or i32 %1, %strex # | store i32 %or, ptr %res, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2) # | %3 = load i32, ptr %res, align 4 # | %or2 = or i32 %3, %strex1 # | store i32 %or2, ptr %res, align 4 # | %4 = load ptr, ptr %addr.addr, align 4 # | %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4) # | %5 = load i32, ptr %res, align 4 # | %or4 = or i32 %5, %strex3 # | store i32 %or4, ptr %res, align 4 # | store i64 42, ptr %tmp, align 8 # | %6 = load { i32, i32 }, ptr %tmp, align 8 # | %7 = extractvalue { i32, i32 } %6, 0 # | %8 = extractvalue { i32, i32 } %6, 1 # | %9 = load ptr, ptr %addr.addr, align 4 # | %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9) # | %10 = load i32, ptr %res, align 4 # | %or5 = or i32 %10, %strexd # | store i32 %or5, ptr %res, align 4 # | %11 = load ptr, ptr %addr.addr, align 4 # | %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11) # | %12 = load i32, ptr %res, align 4 # | %or7 = or i32 %12, %strex6 # | store i32 %or7, ptr %res, align 4 # | store double 3.141590e+00, ptr %tmp8, align 8 # | %13 = load { i32, i32 }, ptr %tmp8, align 8 # | %14 = extractvalue { i32, i32 } %13, 0 # | %15 = extractvalue { i32, i32 } %13, 1 # | %16 = load ptr, ptr %addr.addr, align 4 # | %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16) # | %17 = load i32, ptr %res, align 4 # | %or10 = or i32 %17, %strexd9 # | store i32 %or10, ptr %res, align 4 # | %18 = load ptr, ptr %addr.addr, ali # | ... # `---data was truncated (10240/16971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596c7b31eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596c7b2ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596c7b3262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f4da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f4daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f4da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f4da31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596c7ac7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005596c7ac7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005596c7aac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596c775be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596c775bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f4da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f4da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f4da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596c775ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (2568 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bd6815eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558bd6812e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558bd681662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feab0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feab0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feab0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feab0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bd67abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558bd67aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558bd67908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558bd643fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558bd643fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feab0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feab0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feab0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bd643fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (2569 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576fbb75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576fbb72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576fbb7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1c5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1c5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1c5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1c5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576fbb0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576fbb0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576fbaf08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576fb79fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576fb79fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1c5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1c5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1c5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576fb79fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2570 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (2571 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056397eb3deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056397eb3ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056397eb3e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f59133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f5918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f59133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f5911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056397ead3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056397ead3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056397eab88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056397e767e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056397e767b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3f5911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f5911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f5911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056397e767a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (2572 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = # | ... # `---data was truncated (10240/39218) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560404d8beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560404d88e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560404d8c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcf2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcf298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcf2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcf291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560404d21bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560404d21a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560404d068b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604049b5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604049b5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efcf291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcf291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcf291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604049b5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (2573 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056031cfd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056031cfd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056031cfd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcd3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcd36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcd3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcd3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056031cf6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056031cf6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056031cf4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056031cbfee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056031cbfeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbcd3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcd36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcd36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056031cbfea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (2574 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb08c9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb08c98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb08c9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03e7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03e738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03e7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03e731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb08c31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb08c31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb08c168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb088c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb088c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03e731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03e731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03e731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb088c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (2575 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local signext i32 @test() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0) # | %conv = trunc i64 %0 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5e2511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f5e250ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f5e251262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5643133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f564318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5643133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f564311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5e24a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f5e24a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f5e248c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f5e213be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f5e213bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f564311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f564311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f564311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5e213ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (2576 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, # | ... # `---data was truncated (10240/24959) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644eba4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644eba49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644eba4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf22133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf2218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf22133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf2211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644eb9e2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644eb9e2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644eb9c78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644eb676e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644eb676b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf2211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf2211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf2211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644eb676a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (2577 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (2578 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f37c0beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f37c08e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f37c0c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff419a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff419aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff419a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff419a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f37ba1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f37ba1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f37b868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f37835e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f37835b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff419a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff419a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff419a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f37835a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (2579 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/12050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640cc477eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640cc474e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640cc47862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd21dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd21dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd21dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd21dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640cc40dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640cc40da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640cc3f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640cc0a1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640cc0a1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd21dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd21dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd21dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640cc0a1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (2580 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c302ddeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c302dae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c302de62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d4c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d4c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d4c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d4c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c30273bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c30273a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c302588b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c2ff07e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c2ff07b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d4c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d4c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d4c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c2ff07a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (2581 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056538ca95eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056538ca92e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056538ca9662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c06533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c0658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c06533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c0651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056538ca2bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056538ca2ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056538ca108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056538c6bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056538c6bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7c0651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c0651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c0651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056538c6bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (2582 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a1b1feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615a1b1ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615a1b2062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd891d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd891d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd891d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd891ced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a1ab5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615a1ab5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615a1a9a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615a1749e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615a1749b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd891ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd891cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd891cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a1749a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2583 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616ec174eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616ec171e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616ec17562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b1d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b1d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b1d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b1d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616ec10abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616ec10aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616ec0ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616ebd9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616ebd9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8b1d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b1d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b1d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616ebd9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (2584 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2b186eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2b186be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2b186f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdac9105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdac915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdac9105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdac90ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2b1804bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2b1804a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2b17e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2b1498e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2b1498b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdac90eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdac90ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdac90ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2b1498a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (2585 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c416c0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c416c0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c416c0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0785133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f078518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0785133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f078511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c416ba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c416ba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c416b898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c416838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c416838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f078511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f078511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f078511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c416838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (2586 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (2587 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f38401eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f383fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f3840262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1d0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1d018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1d0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1d011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f38397bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f38397a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f3837c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f3802be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f3802bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1d011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1d011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1d011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f3802ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (2588 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %isneg.i = icmp slt i32 %1, 0 # | %not.i = xor i32 %1, -1 # | %2 = select i1 %isneg.i, i32 %not.i, i32 %1 # | %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false) # | %4 = sub nuw i32 %3, 1 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rev_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %2 = call i32 @llvm.bitreverse.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rd.addr.i, align 4 # | %4 = load i32, ptr %__rs1.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rs1.addr.i, align 4 # | %4 = load i32, ptr %__rd.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false) # | ret i32 %elt.abs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function At # | ... # `---data was truncated (10240/1228637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055fc60d73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fc60d70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fc60d7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88b7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88b7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88b7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88b7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc60d09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fc60d09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fc60cee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fc6099de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fc6099db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88b7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88b7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88b7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc6099da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (2589 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (2590 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561df3bb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561df3bb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561df3bb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faec9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faec975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faec9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faec96ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561df3b49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561df3b49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561df3b2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561df37dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561df37ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faec96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faec96ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faec96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561df37dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (2591 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c36e143eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c36e140e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c36e14462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c36e0d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c36e0d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c36e0be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c36dd6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c36dd6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd5b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c36dd6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (2592 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602f492eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005602f492be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005602f492f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4486b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4486b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4486b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4486b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602f48c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005602f48c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005602f48a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005602f4558e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005602f4558b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4486b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4486b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4486b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602f4558a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (2593 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561b8625eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561b8622e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561b862662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa08e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa08e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa08e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa08e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561b85bbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005561b85bba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005561b85a08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005561b824fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005561b824fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa08e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa08e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa08e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561b824fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (2594 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2595 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7a5e85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e7a5e82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e7a5e8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f056741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05674725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f056741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0567403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7a5e1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7a5e1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7a5e008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e7a5aafe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e7a5aafb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0567404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05674050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05674050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7a5aafa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (2596 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (2597 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0c2673eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0c2670e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0c267462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe75ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe75eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe75ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe75ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0c2609bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0c2609a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0c25ee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0c229de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0c229db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe75ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe75ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe75ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0c229da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (2598 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648731f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648731f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648731f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbf8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbf8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbf8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbf8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056487318ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056487318ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648731738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564872e22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564872e22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbf8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbf8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbf8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564872e22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (2599 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (2600 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559304b4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559304b47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559304b4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5562449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5562449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5562431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559304ae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559304ae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559304ac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559304774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559304774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5562432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559304774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (2601 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558405512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055840550fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055840551362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5287649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52876a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5287649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5287631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584054a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005584054a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055840548d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055840513ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055840513cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5287632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52876330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52876330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055840513ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (2602 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | # | ... # `---data was truncated (10240/43478) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055593e466eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055593e463e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055593e46762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc940733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc94078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc940733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc94071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055593e3fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055593e3fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055593e3e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055593e090e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055593e090b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc94071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc94071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc94071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055593e090a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (2603 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056438a3a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056438a39ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056438a3a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faef8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faef88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faef8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faef8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056438a337bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056438a337a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056438a31c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564389fcbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564389fcbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faef8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faef88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faef88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564389fcba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (2604 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6463bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6463b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6463bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99b0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99b0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99b0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99b0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e646352bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e646352a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6463378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e645fe6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e645fe6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f99b0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99b0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99b0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e645fe6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (2605 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d78218ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d782189e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d78218d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf22649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf22649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf22631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d782122bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d782122a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7821078b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d781db6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d781db6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf22632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf226330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d781db6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (2606 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574cd0d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574cd0cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574cd0d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef6a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef6a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef6a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef6a831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574cd067bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005574cd067a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574cd04c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574cccfbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574cccfbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fef6a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef6a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef6a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574cccfba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (2607 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (2608 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626b7a96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626b7a93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626b7a9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faeb2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faeb298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faeb2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faeb291b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626b7a2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626b7a2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626b7a118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626b76c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626b76c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faeb291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faeb291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faeb291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626b76c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (2609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c38240eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c3823de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c3824162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fc6933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fc698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fc6933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fc691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c381d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c381d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c381bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c37e6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c37e6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6fc691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fc691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fc691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c37e6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (2610 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056214e75beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056214e758e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056214e75c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa999533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa99958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa999533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa99951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056214e6f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056214e6f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056214e6d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056214e385e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056214e385b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa99951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa99951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa99951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056214e385a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (2611 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call < # | ... # `---data was truncated (10240/66998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056032d800eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056032d7fde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056032d80162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc77e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc77ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc77e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc77e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056032d796bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056032d796a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056032d77b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056032d42ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056032d42ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc77e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc77e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc77e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056032d42aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (2612 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (2613 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f215ab3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f215ab0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f215ab462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f215a49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f215a49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f215a2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f2156dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f2156ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f47b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2156dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (2614 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623b6848eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623b6845e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623b684962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bb9705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bb975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bb9705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bb96ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623b67debbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623b67dea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623b67c38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623b6472e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623b6472b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bb96eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bb96ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bb96ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623b6472a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (2615 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056227efefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056227efece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056227eff062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddbf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddbf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddbf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddbf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056227ef85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056227ef85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056227ef6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056227ec19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056227ec19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddbf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddbf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddbf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056227ec19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (2616 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.ris # | ... # `---data was truncated (10240/18562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e90f45eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561e90f42e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561e90f4662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3793b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3793b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3793b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3793b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e90edbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561e90edba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561e90ec08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561e90b6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561e90b6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3793b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3793b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3793b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e90b6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (2617 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565e62efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565e62ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565e62f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbefb649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbefb6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbefb649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbefb631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565e6285bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565e6285a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565e626a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565e5f19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565e5f19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbefb632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbefb6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbefb6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565e5f19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (2618 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e78b39beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e78b398e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e78b39c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fe6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fe618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fe6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fe611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e78b331bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e78b331a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e78b3168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e78afc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e78afc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2fe611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fe611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fe611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e78afc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2619 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b80586eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b80583e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b8058762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed34533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed3458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed34533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed3451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b8051cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b8051ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b805018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b801b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b801b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fed3451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed3451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed3451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b801b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2620 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056078b6a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056078b6a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056078b6a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe14f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe14f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe14f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe14f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056078b63dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056078b63da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056078b6228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056078b2d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056078b2d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe14f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe14f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe14f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056078b2d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (2621 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055796b72aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055796b727e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055796b72b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f51133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f5118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f51133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f5111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055796b6c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055796b6c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055796b6a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055796b354e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055796b354b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f5111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f5111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f5111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055796b354a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2622 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005631cd71deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005631cd71ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005631cd71e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5754249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57542a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5754249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5754231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005631cd6b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005631cd6b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005631cd6988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631cd347e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631cd347b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5754232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57542330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57542330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631cd347a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (2623 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Functi # | ... # `---data was truncated (10240/116949) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f95fccdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f95fccae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f95fcce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ccf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ccf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ccf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ccf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f95fc63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f95fc63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f95fc488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f95f8f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f95f8f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ccf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ccf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ccf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f95f8f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (2624 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %x.addr, align 8 # | %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> # | ret <8 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | %p.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | store <8 x i8> %p, ptr %p.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %p.addr, align 8 # | %mask = and <8 x i8> %1, splat (i8 7) # | %shuf_idx = extractelement <8 x i8> %mask, i64 0 # | %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <8 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <8 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <8 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <8 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <8 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <8 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <8 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | ret <8 x i8> %shuf_ins21 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %x.addr, align 16 # | %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> # | ret <16 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %p.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store <16 x i8> %p, ptr %p.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %p.addr, align 16 # | %mask = and <16 x i8> %1, splat (i8 15) # | %shuf_idx = extractelement <16 x i8> %mask, i64 0 # | %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <16 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <16 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <16 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <16 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <16 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <16 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <16 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | %shuf_idx22 = extractelement <16 x i8> %mask, i64 8 # | %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22 # | %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8 # | %shuf_idx25 = extractelement <16 x i8> %mask, i64 9 # | %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25 # | %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9 # | %shuf_idx28 = extractelement <16 x i8> %mask, i64 10 # | %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28 # | %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10 # | %shuf_idx31 = extractelement <16 x i8> %mask, i64 11 # | %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31 # | %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11 # | %shuf_idx34 = extractelement <16 x i8> %mask, i64 12 # | %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34 # | %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12 # | %shuf_idx37 = extractelement <16 x i8> %mask, i64 13 # | %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37 # | %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13 # | %shuf_idx40 = extractelement <16 x i8> %mask, i64 14 # | %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40 # | %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14 # | %shuf_idx43 = extractelement <16 x i8> %mask, i64 15 # | %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43 # | %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15 # | ret <16 x i8> %shuf_ins45 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a4bd9feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558a4bd9ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558a4bda062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25e8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25e8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25e8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25e8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a4bd35bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558a4bd35a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558a4bd1a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558a4b9c9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558a4b9c9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25e8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25e8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25e8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a4b9c9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (2625 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (2626 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a46f145eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a46f142e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a46f14662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc374133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc37418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc374133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc37411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a46f0dbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a46f0dba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a46f0c08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a46ed6fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a46ed6fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc37411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc37411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc37411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a46ed6fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2627 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b4063eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555b4063be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555b4063f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3476a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3476a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3476a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3476a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b405d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555b405d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555b405b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555b40268e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555b40268b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3476a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3476a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3476a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b40268a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (2628 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aaf4f98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aaf4f95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aaf4f9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb864533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb86458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb864533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb86451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aaf4f2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aaf4f2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aaf4f138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aaf4bc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aaf4bc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb86451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb86451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb86451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaf4bc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (2629 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe0bcc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe0bcc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe0bcc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1712f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1712f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1712f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1712f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe0bc5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe0bc5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe0bc438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe0b8f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe0b8f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1712f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1712f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1712f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe0b8f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (2630 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/18867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d5d4e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d5d4e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d5d4e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1f491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d5d47bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d5d47ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d5d4608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d5d10fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d5d10fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa1f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1f491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d5d10fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (2631 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloc # | ... # `---data was truncated (10240/71123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a9ca18eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a9ca15e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a9ca1962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c60533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c6058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c60533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c6051b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a9c9aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a9c9aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a9c9938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a9c642e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a9c642b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c6051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c6051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c6051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a9c642a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (2632 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/68073) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055723dff8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055723dff5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055723dff962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70b5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055723df8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055723df8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055723df738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055723dc22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055723dc22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055723dc22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (2633 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (2634 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f99b55eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559f99b52e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559f99b5662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb7ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb7eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb7ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb7ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f99aebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559f99aeba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559f99ad08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559f9977fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559f9977fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb7ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb7ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb7ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f9977fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (2635 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-unknown-linux-gnu" # | # | @__riscv_cpu_model = external dso_local global { i32, i64, i64 } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1808 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372035378380799 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 1152921505839391232 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775800 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 102892581 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775543 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 337970694 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d29c617eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d29c614e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d29c61862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb61f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb61f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb61f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb61eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d29c5adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d29c5ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d29c5928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d29c241e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d29c241b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcb61eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb61eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb61eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d29c241a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (2636 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594b982deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594b982ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594b982e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f084681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08468725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f084681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0846803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594b97c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594b97c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594b97a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594b9457e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594b9457b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0846804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08468050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08468050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594b9457a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (2637 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f6ee22eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f6ee1fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f6ee2362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8f2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8f2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8f2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8f2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f6edb8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f6edb8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f6ed9d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f6ea4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f6ea4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8f2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8f2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8f2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f6ea4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (2638 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594bdfeaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594bdfe7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594bdfeb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e41649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e41649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e41631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594bdf80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594bdf80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594bdf658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594bdc14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594bdc14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e41632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e416330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594bdc14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (2639 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b173d52eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b173d4fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b173d5362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb26681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2668725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb26681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb266803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b173ce8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b173ce8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b173ccd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b17397ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b17397cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb266804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2668050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2668050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b17397ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (2640 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de205f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de205f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de205f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6241649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62416a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6241649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6241631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de20589bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de20589a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de2056e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de2021de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de2021db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6241632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62416330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62416330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de2021da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (2641 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c00a9d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c00a9d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c00a9d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17ecd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17ecd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17ecd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17ecd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c00a96bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c00a96ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c00a9508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c00a5ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c00a5ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17ecd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17ecd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17ecd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c00a5ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (2642 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( po # | ... # `---data was truncated (10240/50898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfdd66deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfdd66ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfdd66e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6300f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6300f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6300f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6300f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfdd603bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfdd603a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfdd5e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfdd297e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfdd297b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6300f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6300f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6300f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfdd297a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2643 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589dba1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005589dba17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005589dba1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55c8905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55c895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55c8905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55c88ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589db9b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005589db9b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005589db9958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005589db644e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005589db644b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55c88eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55c88ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55c88ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589db644a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (2644 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vas # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563200e03eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563200e00e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563200e0462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a71249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a71249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a71231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563200d99bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563200d99a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563200d7e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563200a2de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563200a2db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a71232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a712330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563200a2da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (2645 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa746fbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa746f8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa746fc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0585c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0585c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0585c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0585c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa74691bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa74691a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa746768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa74325e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa74325b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0585c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0585c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0585c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa74325a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (2646 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (2647 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558232d7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558232d7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558232d7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558232d14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558232d14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558232cf98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005582329a8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005582329a8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582329a8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (2648 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cfbd97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cfbd94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cfbd9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46b3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46b318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46b3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46b311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cfbd2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cfbd2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cfbd128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cfb9c1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cfb9c1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f46b311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46b311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46b311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cfb9c1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (2649 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63666ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c636669e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c63666d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa727e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa727e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa727e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa727e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c636602bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c636602a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6365e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c636296e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c636296b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa727e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa727e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa727e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c636296a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (2650 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | ... # `---data was truncated (10240/12958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563159f48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563159f45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563159f4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52f5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52f52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52f5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52f5231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563159edebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563159edea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563159ec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563159b72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563159b72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f52f5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52f52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52f52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563159b72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (2651 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa01c4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa01c4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa01c5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa3b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa3b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa3b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa3b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa01be5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa01be5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa01bca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa01879e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa01879b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faa3b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa3b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa3b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa01879a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (2652 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/71955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568eab44eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568eab41e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568eab4562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd78f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd78f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568eaadabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568eaadaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568eaabf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568ea76ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568ea76eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd78f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568ea76ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (2653 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align # | ... # `---data was truncated (10240/10944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056024ef92eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056024ef8fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056024ef9362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f095541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09554725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f095541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0955403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056024ef28bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056024ef28a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056024ef0d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056024ebbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056024ebbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0955404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09554050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09554050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056024ebbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (2654 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056063e3c7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056063e3c4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056063e3c862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe257733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe25778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe257733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe25771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056063e35dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056063e35da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056063e3428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056063dff1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056063dff1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe25771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe25771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe25771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056063dff1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (2655 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a20ae6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a20ae3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a20ae762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83c6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83c618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83c6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83c611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a20a7cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a20a7ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a20a618b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a20710e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a20710b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83c611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83c611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83c611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a20710a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (2656 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eadc454eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eadc451e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eadc45562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd645f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd645f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd645f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd645eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eadc3eabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eadc3eaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eadc3cf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eadc07ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eadc07eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd645eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd645eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd645eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eadc07ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (2657 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %bas # | ... # `---data was truncated (10240/29817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560eb8fb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560eb8fb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560eb8fb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d3c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d3c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d3c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d3c831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560eb8f4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560eb8f4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560eb8f2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560eb8bdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560eb8bdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d3c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d3c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d3c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560eb8bdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (2658 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # | #0 0x0000556fc0bc8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fc0bc5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fc0bc962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f342441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34244725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f342441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3424403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fc0b5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fc0b5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fc0b438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fc07f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fc07f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3424404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34244050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34244050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fc07f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (2659 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (2660 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055734d0d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055734d0d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055734d0d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68a1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68a198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68a1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68a191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055734d06bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055734d06ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055734d0508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055734ccffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055734ccffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f68a191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68a191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68a191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055734ccffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (2661 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2662 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv64i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv64i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_ # | ... # `---data was truncated (10240/15323) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4304abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4304a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4304ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b0c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b0c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b0c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b0c803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b430441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b430441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4304268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4300d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4300d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b0c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b0c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b0c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4300d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (2663 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623ab418eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623ab415e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623ab41962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc48f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc48f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc48f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc48f431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623ab3aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623ab3aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623ab3938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623ab042e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623ab042b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc48f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc48f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc48f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623ab042a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (2664 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (2665 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = c # | ... # `---data was truncated (10240/41433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6cc009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6cc006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6cc00a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6c8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6c818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6c8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6c811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6cbf9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6cbf9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6cbf848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6cbc33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6cbc33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe6c811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6c811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6c811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6cbc33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (2666 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056043c166eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056043c163e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056043c16762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16e6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16e6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16e6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16e6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056043c0fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056043c0fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056043c0e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056043bd90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056043bd90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f16e6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16e6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16e6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056043bd90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (2667 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri # | ... # `---data was truncated (10240/20523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056101d7f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056101d7f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056101d7f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff657f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff657f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff657f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff657eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056101d78cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056101d78ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056101d7718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056101d420e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056101d420b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff657eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff657eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff657eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056101d420a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (2668 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fecfc32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fecfc2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fecfc3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc095049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc095049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc095031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fecfbc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fecfbc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fecfbad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fecf85ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fecf85cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc095032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0950330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fecf85ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (2669 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559269d35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559269d32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559269d3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0003933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f000398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0003933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f000391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559269ccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559269ccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559269cb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055926995fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055926995fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f000391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f000391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f000391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055926995fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (2670 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ae58c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ae58bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ae58c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8626849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86268a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8626849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8626831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ae5856bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ae5856a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ae583b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ae54eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ae54eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8626832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86268330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86268330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ae54eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2671 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ec8820eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557ec881de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557ec882162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3fe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3fe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3fe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3fe31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ec87b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557ec87b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557ec879b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557ec844ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557ec844ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd3fe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3fe31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3fe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ec844aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (2672 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd1c009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bd1c006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bd1c00a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1322449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13224a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1322449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1322431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd1bf9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bd1bf9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bd1bf848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bd1bc33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bd1bc33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1322432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13224330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13224330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd1bc33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2673 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e56b6ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e56b69e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e56b6d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff1c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff1c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff1c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff1c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e56b02bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e56b02a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e56ae78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e56796e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e56796b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff1c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff1c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff1c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e56796a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2674 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2fd16deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2fd16ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2fd16e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ca5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ca50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ca5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ca5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2fd103bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b2fd103a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2fd0e88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b2fcd97e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b2fcd97b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ca5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ca50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ca50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2fcd97a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (2675 of 27910) ******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | @X = global i32 0, align 4 # | @Y = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @foo() #0 { # | entry: # | %retval = alloca i32, align 4 # | %i = alloca i32, align 4 # | store i32 0, ptr %i, align 4 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %entry # | %0 = load i32, ptr %i, align 4 # | %cmp = icmp slt i32 %0, 100 # | br i1 %cmp, label %for.body, label %for.end # | # | for.body: ; preds = %for.cond # | br label %for.end # | # | for.inc: ; No predecessors! # | %1 = load i32, ptr %i, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %i, align 4 # | br label %for.cond # | # | for.end: ; preds = %for.body, %for.cond # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type] # | 13 | } # | | ^ # | 1 warning generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # | #0 0x000055dacfe27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dacfe24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dacfe2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ecae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ecaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ecae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ecae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dacfdbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dacfdbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dacfda28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dacfa51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dacfa51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ecae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ecae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ecae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dacfa51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (2676 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056299a02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056299a027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056299a02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29a6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29a6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29a6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29a6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562999fc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562999fc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562999fa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562999c54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562999c54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29a6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29a6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29a6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562999c54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (2677 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a0631eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615a062ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615a063262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7aa5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7aa58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7aa5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7aa5831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a05c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615a05c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615a05ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615a025be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615a025bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7aa5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7aa58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7aa58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a025ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (2678 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbb51f8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cbb51f5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cbb51f962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a67533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a6758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a67533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a6751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbb518ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cbb518ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cbb51738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cbb4e22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cbb4e22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a6751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a6751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a6751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbb4e22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (2679 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce06babeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ce06ba8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ce06bac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e12c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e12ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e12c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e12c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce06b41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ce06b41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ce06b268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ce067d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ce067d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0e12c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e12c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e12c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce067d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (2680 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bf30beeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563bf30bbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563bf30bf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b0dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b0dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b0dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b0dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bf3054bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563bf3054a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563bf30398b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563bf2ce8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563bf2ce8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b0dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b0dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b0dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bf2ce8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (2681 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f71005feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f71005ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f71006062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4f9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4f998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4f9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4f991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f70fff5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f70fff5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f70ffda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f70fc89e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f70fc89b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4f991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4f991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4f991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f70fc89a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (2682 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (2683 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620b1975eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620b1972e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620b197662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfffa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfffaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfffa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfffa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620b190bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620b190ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620b18f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620b159fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620b159fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdfffa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfffa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfffa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620b159fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (2684 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bef837ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bef8379e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bef837d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a26049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a260a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a26049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a26031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bef8312bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bef8312a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bef82f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bef7fa6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bef7fa6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a26032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a260330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a260330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bef7fa6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (2685 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (2686 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff0192feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff0192ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff0193062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f948fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f948fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f948fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f948fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff018c5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff018c5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff018aa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff01559e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff01559b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f948fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f948fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f948fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff01559a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2687 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614eb6c5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005614eb6c2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005614eb6c662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd42b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd42b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd42b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd42b831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614eb65bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005614eb65ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005614eb6408b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005614eb2efe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005614eb2efb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd42b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd42b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd42b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614eb2efa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (2688 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055910113aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559101137e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055910113b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1678d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1678d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1678d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1678d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591010d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591010d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591010b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559100d64e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559100d64b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1678d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1678d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1678d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559100d64a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (2689 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055625c6c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055625c6c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055625c6c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc07133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc0718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc07133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc0711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055625c659bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055625c659a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055625c63e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055625c2ede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055625c2edb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc0711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc0711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc0711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055625c2eda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (2690 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f127c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557f127bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557f127c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74a6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74a6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74a6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74a6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f12758bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557f12758a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557f1273d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557f123ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557f123ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74a6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74a6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74a6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f123eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (2691 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4314edeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4314eae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4314ee62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbea5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbea56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbea5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbea5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e431483bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e431483a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4314688b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e431117e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e431117b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbea5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbea56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbea56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e431117a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (2692 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609725e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005609725e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005609725e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b1bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560972579bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560972579a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056097255e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056097220de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056097220db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7b1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056097220da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2693 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572084eceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572084e9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572084ed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a5dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a5dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a5dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a5dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557208482bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557208482a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572084678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557208116e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557208116b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a5dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a5dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a5dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557208116a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (2694 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (2695 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b29ac80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b29ac7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b29ac8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79d7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79d78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79d7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79d7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b29ac16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b29ac16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b29abfb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b29a8aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b29a8aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f79d7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79d78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79d78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b29a8aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (2696 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d681e5ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d681e59e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d681e5d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef9031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d681df2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d681df2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d681dd78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d681a86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d681a86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbef9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d681a86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (2697 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1 # | ... # `---data was truncated (10240/26772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6cc1e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6cc1e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6cc1e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5a5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6cc17bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6cc17ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6cc1608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6cbe0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6cbe0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff5a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5a5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6cbe0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (2698 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eda3e73eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eda3e70e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eda3e7462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f989c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f989c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f989c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f989c431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eda3e09bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eda3e09a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eda3dee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eda3a9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eda3a9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f989c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f989c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f989c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eda3a9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (2699 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619aa0f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005619aa0f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005619aa0fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9ab733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9ab78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9ab733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9ab71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619aa08fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005619aa08fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005619aa0748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005619a9d23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005619a9d23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9ab71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9ab71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9ab71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619a9d23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (2700 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aedf51aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aedf517e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aedf51b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f394a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f394a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f394a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f394a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aedf4b0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aedf4b0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aedf4958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aedf144e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aedf144b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f394a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f394a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f394a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aedf144a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (2701 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (2702 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c387b72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c387b6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c387b7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd58ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd58ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd58ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd58ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c387b08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c387b08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c387aed8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c38779ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c38779cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd58ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd58ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd58ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c38779ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (2703 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.a # | ... # `---data was truncated (10240/38299) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056423a691eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056423a68ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056423a69262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d19933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d1998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d19933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d1991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056423a627bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056423a627a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056423a60c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056423a2bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056423a2bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d1991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d1991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d1991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056423a2bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (2704 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = and <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = and <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = and <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = and <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr # | ... # `---data was truncated (10240/11060) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564699347eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564699344e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056469934862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d1e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d1e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d1e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d1e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646992ddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646992dda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646992c28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564698f71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564698f71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d1e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d1e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d1e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564698f71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (2705 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8a857aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8a8577e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8a857b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cdea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cdeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cdea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cdea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8a8510bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8a8510a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8a84f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8a81a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8a81a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3cdea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cdea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cdea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8a81a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (2706 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef # | ... # `---data was truncated (10240/14333) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db06192eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db0618fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db0619362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03df933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03df98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03df933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03df91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db06128bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db06128a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db0610d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db05dbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db05dbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03df91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03df91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03df91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db05dbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2707 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c1109beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c11098e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c1109c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd5c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c11031bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c11031a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c110168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c10cc5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c10cc5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c10cc5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (2708 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso # | ... # `---data was truncated (10240/148012) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab2882eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ab2882be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ab2882f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77edc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77edca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77edc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77edc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab287c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ab287c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ab287a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ab28458e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ab28458b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f77edc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77edc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77edc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab28458a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (2709 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv64i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u64m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/30303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557852318eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557852315e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055785231962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94dfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94dfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94dfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94dfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578522aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005578522aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005578522938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557851f42e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557851f42b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94dfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94dfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94dfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557851f42a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (2710 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2711 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) # # | ... # `---data was truncated (10240/26584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e70788eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556e70785e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556e7078962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff871849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8718a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff871849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff871831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e7071ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556e7071ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556e707038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556e703b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556e703b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff871832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8718330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8718330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e703b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (2712 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f0ce3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f0ce3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f0ce3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddb7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddb7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddb7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddb7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f0cdd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f0cdd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f0cdb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f0ca68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f0ca68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fddb7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddb7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddb7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f0ca68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (2713 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (2714 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e2f48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005646e2f45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646e2f4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff5df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e2edebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005646e2edea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005646e2ec38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646e2b72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646e2b72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e2b72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (2715 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a9eb5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557a9eb57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557a9eb5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9901f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9901f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9901f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9901eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a9eaf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557a9eaf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557a9ead58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557a9e784e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557a9e784b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9901eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9901eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9901eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a9e784a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (2716 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = # | ... # `---data was truncated (10240/10936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feadb29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055feadb26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055feadb2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c79049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c790a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c79049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c79031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feadabfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055feadabfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055feadaa48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fead753e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fead753b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c79032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c790330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c790330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fead753a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2717 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6341b2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6341afe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6341b362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fb9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fb9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fb9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fb9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f634148bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f634148a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f63412d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f633ddce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f633ddcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7fb9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fb9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fb9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f633ddca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (2718 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstrid # | ... # `---data was truncated (10240/28111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056361a55beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056361a558e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056361a55c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb77b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb77b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb77b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb77b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056361a4f1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056361a4f1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056361a4d68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056361a185e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056361a185b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb77b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb77b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb77b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056361a185a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (2719 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksed1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c11f3b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c11f3b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c11f3b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf80505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf8055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf80505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf804ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c11f34bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c11f34ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c11f3308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c11efdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c11efdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf804eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf804ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf804ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c11efdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (2720 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24072) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cabc58feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cabc58ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cabc59062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f937a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f937a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f937a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f937a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cabc525bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cabc525a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cabc50a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cabc1b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cabc1b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f937a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f937a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f937a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cabc1b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (2721 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edbd3f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055edbd3f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055edbd3f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec0f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec0f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec0f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec0f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edbd38cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055edbd38ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055edbd3718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055edbd020e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055edbd020b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec0f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec0f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec0f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edbd020a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (2722 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (2723 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65ce50eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f65ce4de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f65ce5162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8ea333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8ea38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8ea333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8ea31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65cde6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f65cde6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f65cdcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f65ca7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f65ca7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8ea31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8ea31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8ea31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65ca7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (2724 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0238e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0238e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0238e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61cc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61cc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61cc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61cc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e02387abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e02387aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e02385f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e02350ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e02350eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61cc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61cc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61cc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e02350ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (2725 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca3c868eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca3c865e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca3c86962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88fd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca3c7febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca3c7fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca3c7e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca3c492e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca3c492b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f88fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca3c492a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (2726 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (2727 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e02e2caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e02e2c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e02e2cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4da505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4da55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4da505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4da4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e02e260bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e02e260a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e02e2458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e02def4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e02def4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4da4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4da4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4da4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e02def4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (2728 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/29136) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563da932beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563da9328e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563da932c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff10a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff10a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff10a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff10a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563da92c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563da92c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563da92a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563da8f55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563da8f55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff10a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff10a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff10a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563da8f55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (2729 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590ffffdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005590ffffae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005590ffffe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa936705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa93675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa936705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9366ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590fff93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005590fff93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590fff788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005590ffc27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005590ffc27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9366eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9366ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9366ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590ffc27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (2730 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (2731 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d008009eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d008006e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d00800a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9362d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9362d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9362d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9362d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d007f9fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d007f9fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d007f848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d007c33e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d007c33b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9362d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9362d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9362d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d007c33a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (2732 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # | #0 0x000055cce6796eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cce6793e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cce679762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2707f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2707f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2707f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2707f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cce672cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cce672ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cce67118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cce63c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cce63c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2707f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2707f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2707f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cce63c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (2733 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, al # | ... # `---data was truncated (10240/28866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a45da7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a45da4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a45da862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e6d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a45d3dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a45d3da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a45d228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a459d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a459d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a459d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (2734 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fa7d8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556fa7d8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556fa7d9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe10e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe10e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe10e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe10e431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fa7d25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556fa7d25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556fa7d0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556fa79b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556fa79b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe10e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe10e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe10e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fa79b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (2735 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdfba94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdfba91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdfba9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4cab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4cab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4cab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4cab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdfba2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdfba2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdfba0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdfb6bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdfb6beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc4cab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4cab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4cab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdfb6bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (2736 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055891e967eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055891e964e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055891e96862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f410f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f410f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f410f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f410f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055891e8fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055891e8fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055891e8e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055891e591e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055891e591b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f410f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f410f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f410f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055891e591a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (2737 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055797ffffeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055797fffce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055798000062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cbe105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cbe15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cbe105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cbe0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055797ff95bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055797ff95a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055797ff7a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055797fc29e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055797fc29b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6cbe0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cbe0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cbe0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055797fc29a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (2738 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e934c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e934c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e934c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1a5a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1a5a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1a5a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1a5a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e9345cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e9345ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e934418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e930f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e930f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1a5a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1a5a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1a5a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e930f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (2739 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643c5582eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643c557fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643c558362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a20933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a2098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a20933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a2091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643c5518bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643c5518a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643c54fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643c51ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643c51acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a2091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a2091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a2091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643c51aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (2740 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055639d1eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055639d1e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055639d1eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94a9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94a96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94a9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94a9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055639d180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055639d180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055639d1658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055639ce14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055639ce14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94a9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94a96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94a96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055639ce14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (2741 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630d4546eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630d4543e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630d454762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5b4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5b46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5b4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5b4631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630d44dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630d44dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630d44c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630d4170e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630d4170b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5b4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5b46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5b46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630d4170a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (2742 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572f459aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572f4597e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572f459b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0170133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f017018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0170133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f017011b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572f4530bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572f4530a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572f45158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572f41c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572f41c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f017011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f017011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f017011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572f41c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (2743 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac21bb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ac21bb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ac21bb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d56933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d5698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d56933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d5691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac21b4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ac21b4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ac21b338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ac217e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ac217e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7d5691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d5691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d5691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac217e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (2744 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568d773beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568d7738e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568d773c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f0b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f0b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f0b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f0b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568d76d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568d76d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568d76b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568d7365e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568d7365b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7f0b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f0b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f0b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568d7365a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (2745 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b333475eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b333472e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b33347662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2862f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2862f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2862f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2862f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b33340bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b33340ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b3333f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b33309fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b33309fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2862f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2862f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2862f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b33309fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (2746 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d429c11eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d429c0ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d429c1262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faad981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faad98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faad981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faad9803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d429ba7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d429ba7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d429b8c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d42983be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d42983bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faad9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faad98050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faad98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d42983ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (2747 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617d6599eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617d6596e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617d659a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc39b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc39b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc39b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc39b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617d652fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617d652fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617d65148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617d61c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617d61c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdc39b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc39b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc39b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617d61c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (2748 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cff5067eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cff5064e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cff506862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c7101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c710725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c7101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c71003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cff4ffdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cff4ffda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cff4fe28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cff4c91e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cff4c91b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c71004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c710050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c710050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cff4c91a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (2749 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055599c340eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055599c33de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055599c34162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2182b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2182b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2182b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2182b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055599c2d6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055599c2d6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055599c2bb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055599bf6ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055599bf6ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2182b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2182b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2182b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055599bf6aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (2750 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055626d864eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055626d861e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055626d86562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8f111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055626d7fabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055626d7faa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055626d7df8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055626d48ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055626d48eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8f111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055626d48ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (2751 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f22f51eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561f22f4ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561f22f5262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c7941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c794725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c7941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c79403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f22ee7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561f22ee7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561f22ecc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561f22b7be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561f22b7bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c79404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c794050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c794050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f22b7ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (2752 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_ # | ... # `---data was truncated (10240/35087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640f44abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640f44a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640f44ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17c2105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17c215c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17c2105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17c20ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640f4441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640f4441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640f44268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640f40d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640f40d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f17c20eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17c20ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17c20ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640f40d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (2753 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (2754 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630f90fceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630f90f9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630f90fd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69efb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630f9092bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630f9092a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630f90778b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005630f8d26e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005630f8d26b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f69efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630f8d26a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (2755 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557efab61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557efab5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557efab6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3efc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3efca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3efc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3efc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557efaaf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557efaaf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557efaadc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557efa78be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557efa78bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3efc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3efc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3efc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557efa78ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (2756 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7edc0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7edc0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7edc0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8686333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f868638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8686333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f868631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7edba3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b7edba3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7edb888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7ed837e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7ed837b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f868631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f868631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f868631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7ed837a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (2757 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/47706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055559eceaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055559ece7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055559eceb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd331333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd33138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd331333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd33131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055559ec80bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055559ec80a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055559ec658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055559e914e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055559e914b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd33131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd33131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd33131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055559e914a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (2758 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a91fd83eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a91fd80e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a91fd8462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ec0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ec06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ec0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ec0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a91fd19bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a91fd19a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a91fcfe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a91f9ade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a91f9adb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ec0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ec06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ec06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a91f9ada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (2759 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , a # | ... # `---data was truncated (10240/98149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c9f7c1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c9f7bee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c9f7c262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f63f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f63f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f63f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f63f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c9f757bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c9f757a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c9f73c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c9f3ebe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c9f3ebb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f63f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f63f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f63f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c9f3eba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (2760 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e415420eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e41541de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e41542162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0139b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0139b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0139b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0139b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4153b6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4153b6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e41539b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e41504ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e41504ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0139b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0139b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0139b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e41504aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (2761 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a873377eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a873374e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a87337862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a72849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a728a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a72849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a72831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a87330dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a87330da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a8732f28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a872fa1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a872fa1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1a72832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a728330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a728330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a872fa1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (2762 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563aec0b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563aec0b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563aec0ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a2bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a2bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a2bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a2bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563aec04fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563aec04fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563aec0348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563aebce3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563aebce3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a2bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a2bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a2bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563aebce3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (2763 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2764 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e30b74eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e30b71e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e30b7562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9fbb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9fbb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9fbb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9fbaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e30b0abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e30b0aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e30aef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e3079ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e3079eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9fbaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9fbaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9fbaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e3079ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (2765 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.n # | ... # `---data was truncated (10240/33624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cb9ffbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cb9ff8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cb9ffc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94a2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94a28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94a2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94a2831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cb9f91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cb9f91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cb9f768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cb9c25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cb9c25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f94a2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94a28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94a28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cb9c25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (2766 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564df6255eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564df6252e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564df625662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb608733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb60878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb608733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb60871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564df61ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564df61eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564df61d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564df5e7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564df5e7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb60871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb60871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb60871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564df5e7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (2767 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561882f20eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561882f1de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561882f2162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e1b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e1b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e1b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e1b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561882eb6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561882eb6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561882e9b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561882b4ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561882b4ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e1b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e1b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e1b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561882b4aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/cx-complex-range.c (2768 of 27910) ******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %coerce.real, ptr %retval.realp, align 4 # | store float %coerce.imag, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__divsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %coerce.real, ptr %.realp1, align 4 # | store float %coerce.imag, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul_ac = fmul float %a.real, %b.real # | %mul_bd = fmul float %a.imag, %b.imag # | %mul_ad = fmul float %a.real, %b.imag # | %mul_bc = fmul float %a.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %real_mul_phi, ptr %retval.realp, align 4 # | store float %imag_mul_phi, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__mulsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul_ac = fmul float %.real, %b.real # | %mul_bd = fmul float %.imag, %b.imag # | %mul_ad = fmul float %.real, %b.imag # | %mul_bc = fmul float %.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %real_mul_phi, ptr %.realp2, align 4 # | store float %imag_mul_phi, ptr %.imagp3, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b = alloca { double, double }, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %2, align 8 # | %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %3, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load doub # | ... # `---data was truncated (10240/29171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000560933863eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560933860e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056093386462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a91733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a9178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a91733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a9171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609337f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005609337f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005609337de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056093348de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056093348db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5a9171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a9171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a9171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056093348da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (2769 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d725eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564d725ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564d725ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c0e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c0e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c0e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c0e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d72584bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564d72584a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564d725698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564d72218e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564d72218b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c0e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c0e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c0e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d72218a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (2770 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056420ede9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056420ede6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056420edea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8e0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8e06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8e0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8e0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056420ed7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056420ed7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056420ed648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056420ea13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056420ea13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8e0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8e06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8e06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056420ea13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (2771 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db4f762eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055db4f75fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055db4f76362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d4c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d4c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d4c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d4c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db4f6f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055db4f6f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055db4f6dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055db4f38ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055db4f38cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8d4c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d4c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d4c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db4f38ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (2772 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556235b62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556235b5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556235b6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff408f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff408f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff408f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff408f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556235af8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556235af8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556235add8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055623578ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055623578cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff408f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff408f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff408f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055623578ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (2773 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c0a910eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c0a90de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c0a91162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe852b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe852b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe852b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe852b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c0a8a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c0a8a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c0a88b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c0a53ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c0a53ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe852b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe852b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe852b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c0a53aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (2774 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, # | ... # `---data was truncated (10240/29443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c119f6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c119f68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c119f6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f918541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91854725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f918541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9185403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c119f01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c119f01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c119ee68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c119b95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c119b95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9185404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91854050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91854050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c119b95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (2775 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563770d1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563770d18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563770d1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa103f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa103f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa103f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa103f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563770cb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563770cb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563770c968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563770945e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563770945b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa103f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa103f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa103f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563770945a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2776 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a7efadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a7efaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a7efae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ee6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ee62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ee6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ee6231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a7ef43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a7ef43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a7ef288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a7ebd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a7ebd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ee6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ee62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ee62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a7ebd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (2777 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600c16c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600c16bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600c16c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82e9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82e9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82e9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82e9aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600c1658bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600c1658a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600c163d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600c12ece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600c12ecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f82e9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82e9aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82e9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600c12eca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (2778 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff6f962eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff6f95fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff6f96362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce07133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce0718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce07133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce0711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff6f8f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff6f8f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff6f8dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff6f58ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff6f58cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce0711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce0711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce0711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff6f58ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (2779 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f67d9baeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f67d9b7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f67d9bb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5efd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5efd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5efd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5efd231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f67d950bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f67d950a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f67d9358b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f67d5e4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f67d5e4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5efd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5efd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5efd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f67d5e4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (2780 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (2781 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de56d68eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de56d65e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de56d6962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb4ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb4cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb4ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb4ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de56cfebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de56cfea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de56ce38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de56992e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de56992b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb4ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb4ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb4ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de56992a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (2782 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10878) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec86c0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec86c09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec86c0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa026a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa026aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa026a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa026a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec86ba2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec86ba2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec86b878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec86836e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec86836b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa026a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa026a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa026a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec86836a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (2783 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623275e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623275e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623275ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff49b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff49b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff49b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff49aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056232757fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056232757fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623275648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562327213e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562327213b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007eff49aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff49aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff49aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562327213a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (2784 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cdba155eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cdba152e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cdba15662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c64133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c6418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c64133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c6411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdba0ebbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cdba0eba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cdba0d08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cdb9d7fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cdb9d7fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c6411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c6411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c6411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdb9d7fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (2785 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642fc50eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642fc50be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642fc50f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1ee71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642fc4a4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642fc4a4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642fc4898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642fc138e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642fc138b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642fc138a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (2786 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d878bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563d878b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563d878bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4730d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4730d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4730d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4730ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d87852bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563d87852a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563d878378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563d874e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563d874e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4730ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4730cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4730cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d874e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (2787 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555966c5feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555966c5ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555966c6062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3aa4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3aa4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3aa4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3aa4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555966bf5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555966bf5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555966bda8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555966889e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555966889b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3aa4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3aa4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3aa4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555966889a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (2788 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581c7b85eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581c7b82e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581c7b8662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d1fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d1faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d1fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d1fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581c7b1bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581c7b1ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581c7b008b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581c77afe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581c77afb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d1fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d1fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d1fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581c77afa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (2789 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e05374eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558e05371e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558e0537562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ca5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ca58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ca5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ca5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e0530abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558e0530aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558e052ef8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558e04f9ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558e04f9eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6ca5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ca58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ca58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e04f9ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2790 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f9457ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564f94579e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564f9457d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaec249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaec2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaec249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaec231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f94512bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564f94512a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564f944f78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564f941a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564f941a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faaec232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaec2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaec2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f941a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (2791 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637f60a8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637f60a5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637f60a962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bdc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bdc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bdc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bdc431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637f603ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637f603ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637f60238b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637f5cd2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637f5cd2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bdc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bdc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bdc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637f5cd2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (2792 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, # | ... # `---data was truncated (10240/30874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c22af2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c22aefe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c22af362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f1f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f1f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f1f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f1f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c22a88bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c22a88a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c22a6d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c2271ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c2271cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f1f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f1f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f1f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c2271ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (2793 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vect # | ... # `---data was truncated (10240/24229) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640b2675eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640b2672e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640b267662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ebda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ebdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ebda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ebda31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640b260bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640b260ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640b25f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640b229fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640b229fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9ebda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ebda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ebda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640b229fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (2794 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f5d843eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f5d840e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f5d84462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2656933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f265698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2656933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f265691b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f5d7d9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f5d7d9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f5d7be8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f5d46de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f5d46db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f265691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f265691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f265691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f5d46da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (2795 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652b7661eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652b765ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652b766262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f967dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f967dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f967dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f967dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652b75f7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652b75f7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005652b75dc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005652b728be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005652b728bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f967dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f967dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f967dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652b728ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (2796 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedo # | ... # `---data was truncated (10240/30751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056367c007eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056367c004e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056367c00862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ca3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ca38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ca3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ca3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056367bf9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056367bf9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056367bf828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056367bc31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056367bc31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ca3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ca38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ca38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056367bc31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (2797 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b17729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b17726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b1772a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe59e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe59e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe59e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe59e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b176bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b176bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b176a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b17353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b17353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe59e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe59e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe59e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b17353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2798 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd21710eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd2170de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd2171162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ce9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ce9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ce9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ce9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd216a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd216a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd2168b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd2133ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd2133ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ce9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ce9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ce9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd2133aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (2799 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562577e3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562577e39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562577e3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca10e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca10ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca10e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca10e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562577dd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562577dd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562577db78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562577a66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562577a66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca10e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca10e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca10e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562577a66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (2800 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5f591feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5f591ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5f592062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd01c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd01c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd01c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd01c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5f58b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5f58b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5f589a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5f5549e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5f5549b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd01c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd01c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd01c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5f5549a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (2801 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bc0efbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bc0ef8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bc0efc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec00733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec0078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec00733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec0071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bc0e91bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bc0e91a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bc0e768b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bc0b25e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bc0b25b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec0071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec0071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec0071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bc0b25a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (2802 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557120313eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557120310e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055712031462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76dd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76dd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76dd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76dd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571202a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571202a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055712028e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055711ff3de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055711ff3db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76dd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76dd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76dd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055711ff3da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (2803 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d844d66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d844d63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d844d6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03d9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03d9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03d9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03d9a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d844cfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d844cfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d844ce18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d844990e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d844990b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03d9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03d9a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03d9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d844990a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (2804 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649b7dcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649b7dc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649b7dcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a7a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a7a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a7a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a7a403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649b7d62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649b7d62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649b7d478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649b79f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649b79f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a7a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a7a4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a7a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649b79f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (2805 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562d1079eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005562d1076e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005562d107a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f14f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f14f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f14f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f14f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562d100fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562d100fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562d0ff48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005562d0ca3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005562d0ca3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9f14f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f14f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f14f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562d0ca3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (2806 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fafb2faeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fafb2f7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fafb2fb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25f7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25f718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25f7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25f711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fafb290bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fafb290a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fafb2758b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fafaf24e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fafaf24b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f25f711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25f711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25f711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fafaf24a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (2807 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6f6234eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d6f6231e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d6f623562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ff3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ff3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ff3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ff3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6f61cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d6f61caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d6f61af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d6f5e5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d6f5e5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ff3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ff3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ff3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6f5e5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (2808 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_zt0() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_zt0() #1 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_zt0() #2 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_zt0() #3 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_zt0() #4 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_za_zt0() #5 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_za_zt0() #6 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_za_zt0() #7 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_za_zt0() #8 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_za_zt0() #9 { # | entry: # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea31322eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea3131fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea3132362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc57b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc57b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc57b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc57b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea312b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea312b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea3129d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea30f4ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea30f4cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc57b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc57b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc57b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea30f4ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x000055579a0f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055579a0f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055579a0f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dc5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dc5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dc5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dc5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055579a08dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055579a08da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055579a0728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555799d21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555799d21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9dc5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dc5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dc5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555799d21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (2809 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a7d00aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564a7d007e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564a7d00b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb551133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb55118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb551133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb55111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a7cfa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564a7cfa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564a7cf858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564a7cc34e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564a7cc34b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb55111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb55111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb55111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a7cc34a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (2810 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfc19cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cfc19cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cfc19ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33f2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33f28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33f2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33f2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfc1963bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cfc1963a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cfc19488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cfc15f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cfc15f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33f2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33f28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33f28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfc15f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (2811 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ce10c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ce10c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ce10c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ab0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ab06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ab0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ab0631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ce105ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ce105ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ce10438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555ce0cf2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555ce0cf2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ab0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ab06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ab06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ce0cf2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (2812 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560002e38eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560002e35e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560002e3962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc373933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc37398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc373933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc37391b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560002dcebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560002dcea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560002db38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560002a62e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560002a62b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc37391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc37391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc37391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560002a62a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (2813 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20139) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563c779ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005563c7799e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005563c779d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f386d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f386d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f386d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f386d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563c7732bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005563c7732a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563c77178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563c73c6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563c73c6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f386d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f386d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f386d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563c73c6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (2814 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557809afeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557809afbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557809aff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03a1905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03a195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03a1905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03a18ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557809a94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557809a94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557809a798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557809728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557809728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03a18eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03a18ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03a18ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557809728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (2815 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056185fe2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056185fe28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056185fe2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f137921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13792725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f137921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1379203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056185fdc1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056185fdc1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056185fda68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056185fa55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056185fa55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1379204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13792050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13792050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056185fa55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (2816 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4a57caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a4a57c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a4a57cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2c7305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2c735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2c7305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2c72ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4a5760bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a4a5760a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a4a57458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a4a53f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a4a53f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa2c72eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2c72ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2c72ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4a53f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (2817 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c1e43feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c1e43ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c1e44062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0812705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f081275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0812705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08126ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c1e3d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c1e3d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c1e3ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c1e069e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c1e069b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08126eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08126ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08126ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c1e069a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2818 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a96a39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562a96a36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562a96a3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5768933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5768933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a969cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562a969cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562a969b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562a96663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562a96663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f576891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a96663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (2819 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623ec050eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005623ec04de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005623ec05162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa7ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa7baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa7ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa7ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623ebfe6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623ebfe6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623ebfcb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005623ebc7ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005623ebc7ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa7ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa7ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa7ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623ebc7aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (2820 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056236ee97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056236ee94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056236ee9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57b0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57b0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57b0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57b0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056236ee2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056236ee2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056236ee128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056236eac1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056236eac1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f57b0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57b0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57b0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056236eac1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (2821 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec04037eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec04034e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec0403862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f6a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f6a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f6a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f6a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec03fcdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec03fcda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec03fb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec03c61e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec03c61b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f6a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f6a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f6a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec03c61a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (2822 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572c2a0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005572c2a0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005572c2a1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0abe705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0abe75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0abe705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0abe6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572c29a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005572c29a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005572c298a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005572c2639e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005572c2639b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0abe6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0abe6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0abe6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572c2639a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-neon-shifts.c (2823 of 27910) ******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"apcs-gnu"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612d4f6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005612d4f6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005612d4f7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4777a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4777aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4777a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4777a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612d4f05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005612d4f05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612d4eea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005612d4b99e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005612d4b99b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4777a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4777a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4777a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612d4b99a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (2824 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (2825 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d6b77feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d6b77ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d6b78062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb92b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb92b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb92b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb92b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d6b715bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d6b715a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d6b6fa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d6b3a9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d6b3a9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb92b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb92b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb92b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d6b3a9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (2826 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a75f1c3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a75f1c0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a75f1c462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dcac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dcaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dcac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dcac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a75f159bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a75f159a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a75f13e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a75edede46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a75ededb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9dcac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dcac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dcac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a75ededa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (2827 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c4bf75eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c4bf72e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c4bf7662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f908821bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90882725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f908821ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9088203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c4bf0bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c4bf0ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c4bef08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c4bb9fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c4bb9fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9088204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90882050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90882050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c4bb9fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (2828 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b412ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b412e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b412ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e1d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e1d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e1d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e1d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b41281bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b41281a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b412668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b40f15e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b40f15b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6e1d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e1d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e1d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b40f15a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (2829 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562127526eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562127523e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056212752762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9854133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f985418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9854133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f985411b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621274bcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621274bca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621274a18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562127150e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562127150b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f985411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f985411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f985411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562127150a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (2830 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fcmp oeq <4 x float> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = fcmp oeq <4 x float> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = icmp eq <4 x i32> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = # | ... # `---data was truncated (10240/125481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642ae4aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005642ae4a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005642ae4ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6dffb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6dffb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6dffb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6dffb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642ae442bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005642ae442a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005642ae4278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005642ae0d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005642ae0d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6dffb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6dffb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6dffb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642ae0d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (2831 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (2832 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056314c49deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056314c49ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056314c49e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35a4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35a40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35a4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35a4031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056314c433bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056314c433a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056314c4188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056314c0c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056314c0c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35a4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35a40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35a40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056314c0c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (2833 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (2834 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (2835 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64( poison # | ... # `---data was truncated (10240/18569) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a94d72eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560a94d6fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560a94d7362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e9c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e9c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e9c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e9c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a94d08bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560a94d08a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560a94ced8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560a9499ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560a9499cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1e9c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e9c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e9c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a9499ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (2836 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i64 immar # | ... # `---data was truncated (10240/14780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0ade08eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d0ade05e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d0ade0962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe465449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4654a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe465449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe465431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0add9ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d0add9ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d0add838b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d0ada32e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d0ada32b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe465432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4654330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4654330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0ada32a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (2837 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e2856ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563e28569e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563e2856d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3d9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3d978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3d9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3d971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e28502bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563e28502a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563e284e78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563e28196e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563e28196b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff3d971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3d971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3d971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e28196a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2838 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m2_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv32i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m2_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m2_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv8i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m4_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv16i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv16i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m8_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv32i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv32i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale # | ... # `---data was truncated (10240/40902) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591e1db0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591e1dade85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591e1db162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5659b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5659b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5659b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5659b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591e1d46bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591e1d46a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591e1d2b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591e19dae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591e19dab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5659b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5659b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5659b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591e19daa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (2839 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591ed562eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591ed55fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591ed56362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fe0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fe098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fe0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fe091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591ed4f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591ed4f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591ed4dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591ed18ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591ed18cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4fe091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fe091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fe091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591ed18ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (2840 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056489b802eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056489b7ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056489b80362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056489b798bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056489b798a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056489b77d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056489b42ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056489b42cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbef291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056489b42ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (2841 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561537a14eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561537a11e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561537a1562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f451ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f451aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f451ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f451ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615379aabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615379aaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056153798f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056153763ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056153763eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f451ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f451ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f451ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056153763ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (2842 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aeeba86eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aeeba83e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aeeba8762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff805305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff80535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff805305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8052ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aeeba1cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aeeba1ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aeeba018b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aeeb6b0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aeeb6b0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8052eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8052ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8052ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aeeb6b0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (2843 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (2844 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055744dc04eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055744dc01e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055744dc0562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe71961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7196725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe71961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe719603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055744db9abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055744db9aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055744db7f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055744d82ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055744d82eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe719604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7196050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7196050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055744d82ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (2845 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/64341) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055625539ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556255399e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055625539d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a4a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a4a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a4a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a4a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556255332bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556255332a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562553178b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556254fc6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556254fc6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a4a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a4a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a4a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556254fc6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2846 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (2847 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c2ae82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563c2ae7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563c2ae8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f898a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f898a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f898a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f898a831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c2ae18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563c2ae18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563c2adfd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563c2aaace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563c2aaacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f898a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f898a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f898a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c2aaaca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (2848 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571e4bb3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005571e4bb0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005571e4bb462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf92b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571e4b49bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571e4b49a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571e4b2e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005571e47dde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005571e47ddb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571e47dda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (2849 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576bcb2ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576bcb29e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576bcb2d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d3c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d3c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d3c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d3c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576bcac2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576bcac2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576bcaa78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576bc756e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576bc756b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6d3c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d3c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d3c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576bc756a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (2850 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e83fe48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e83fe45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e83fe4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71c8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71c88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71c8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71c8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e83fddebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e83fddea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e83fdc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e83fa72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e83fa72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f71c8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71c88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71c88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e83fa72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (2851 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556afd111eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556afd10ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556afd11262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d16049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d160a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d16049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d16031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556afd0a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556afd0a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556afd08c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556afcd3be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556afcd3bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d16032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d160330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d160330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556afcd3ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (2852 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba35563eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ba35560e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ba3556462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3705049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37050a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3705049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3705031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba354f9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ba354f9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ba354de8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ba3518de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ba3518db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3705032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37050330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37050330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba3518da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (2853 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a2a2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005615a2a2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005615a2a2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea98b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea98b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea98b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea98b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a29c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005615a29c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005615a29a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005615a2657e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005615a2657b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea98b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea98b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea98b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a2657a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (2854 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret # | ... # `---data was truncated (10240/29371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da49729eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da49726e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da4972a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f923e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f923e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f923e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f923e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da496bfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da496bfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da496a48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da49353e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da49353b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f923e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f923e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f923e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da49353a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (2855 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (2856 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bf5b0deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bf5b0ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bf5b0e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d25849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d258a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d25849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d25831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bf5aa3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bf5aa3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bf5a888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bf5737e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bf5737b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d25832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d258330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d258330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bf5737a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (2857 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d715195eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d715192e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d71519662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e9d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e9d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e9d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e9d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d71512bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d71512ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7151108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d714dbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d714dbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e9d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e9d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e9d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d714dbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (2858 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559bf5beeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559bf5bebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559bf5bef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f68f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f68f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f68f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f68f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559bf5b84bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559bf5b84a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559bf5b698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559bf5818e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559bf5818b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f68f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f68f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f68f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bf5818a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (2859 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | # | ... # `---data was truncated (10240/29535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557029e48eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557029e45e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557029e4962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f958eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f958eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f958eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f958eaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557029ddebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557029ddea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557029dc38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557029a72e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557029a72b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f958eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f958eaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f958eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557029a72a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (2860 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056062af97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056062af94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056062af9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc63a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc63aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc63a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc63a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056062af2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056062af2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056062af128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056062abc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056062abc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc63a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc63a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc63a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056062abc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (2861 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056292429eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056292429be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056292429f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8bf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8bf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8bf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8bf031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562924234bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562924234a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005629242198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562923ec8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562923ec8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8bf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8bf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8bf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562923ec8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (2862 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ba1410eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ba140de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ba141162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d38b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d38b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d38b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d38b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ba13a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ba13a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ba138b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ba103ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ba103ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d38b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d38b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d38b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ba103aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (2863 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/14461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2155cceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2155c9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2155cd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58cf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58cf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58cf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58cf031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e215562bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e215562a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2155478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2151f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2151f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58cf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58cf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58cf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2151f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (2864 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/64349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595551f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595551f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595551f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd082f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd082f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd082f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd082f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559555189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559555189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055955516e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559554e1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559554e1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd082f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd082f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd082f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559554e1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (2865 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.srshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nos # | ... # `---data was truncated (10240/11578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056414c4caeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056414c4c7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056414c4cb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf40b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf40b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf40b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf40b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056414c460bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056414c460a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056414c4458b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056414c0f4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056414c0f4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf40b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf40b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf40b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056414c0f4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (2866 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/13617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c7b2d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c7b2cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c7b2d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7626b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7626b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7626b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7626aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c7b266bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c7b266a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c7b24b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c7aefae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c7aefab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7626aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7626aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7626aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c7aefaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (2867 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056527f63beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056527f638e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056527f63c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8442449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84424a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8442449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8442431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056527f5d1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056527f5d1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056527f5b68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056527f265e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056527f265b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8442432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84424330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84424330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056527f265a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (2868 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d289a13eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d289a10e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d289a1462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2b5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2b5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2b5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2b5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2899a9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2899a9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d28998e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d28963de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d28963db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc2b5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2b5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2b5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d28963da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (2869 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/65723) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e3f3b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e3f3b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e3f3b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f535f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f535f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f535f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f535f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e3f34bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e3f34ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e3f3308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e3efdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e3efdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f535f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f535f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f535f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e3efdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (2870 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fb6cbdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fb6cbae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fb6cbe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb1bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fb6c53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fb6c53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fb6c388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fb68e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fb68e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fb68e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (2871 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store % # | ... # `---data was truncated (10240/13308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591ac370eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005591ac36de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005591ac37162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a1a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a1a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a1a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a1a403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591ac306bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005591ac306a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005591ac2eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005591abf9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005591abf9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2a1a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a1a4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a1a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591abf9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (2872 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (2873 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652155efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005652155ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005652155f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85d4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85d498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85d4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85d491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565215585bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565215585a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056521556a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565215219e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565215219b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85d491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85d491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85d491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565215219a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (2874 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80) # | %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64) # | %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %addr, ptr %addr.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4) # | %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1 # | store <2 x i64> %6, ptr %0, align 8 # | %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559eb8580eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559eb857de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559eb858162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6adde1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6adde725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6adde1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6adde03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559eb8516bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559eb8516a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559eb84fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559eb81aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559eb81aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6adde04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6adde050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6adde050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559eb81aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (2875 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa391f6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa391f3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa391f762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6b0431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa3918cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa3918ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa391718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa38e20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa38e20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6b04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa38e20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (2876 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, alig # | ... # `---data was truncated (10240/26754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644998d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644998d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644998da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01d891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056449986fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056449986fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644998548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564499503e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564499503b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01d891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564499503a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (2877 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4c47e8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4c47e5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4c47e962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5045933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f504598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5045933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f504591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4c477ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4c477ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4c47638b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4c4412e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4c4412b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f504591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f504591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f504591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4c4412a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (2878 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056291d682eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056291d67fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056291d68362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc50ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc50ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc50ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc50ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056291d618bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056291d618a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056291d5fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056291d2ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056291d2acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc50ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc50ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc50ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056291d2aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (2879 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a601ab8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a601ab5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a601ab962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ab5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ab56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ab5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ab5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a601a4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a601a4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a601a338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6016e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6016e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ab5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ab56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ab56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6016e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (2880 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600e4cc9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600e4cc6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600e4cca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1974705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f197475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1974705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19746ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600e4c5fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600e4c5fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600e4c448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600e48f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600e48f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f19746eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19746ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19746ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600e48f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (2881 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback # | ... # `---data was truncated (10240/15245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561861efeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005561861ece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005561861f062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc65d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc65d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc65d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc65d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556186185bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556186185a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055618616a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556185e19e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556185e19b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc65d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc65d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc65d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556185e19a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (2882 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594c2616eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594c2613e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594c261762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57c8d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57c8d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57c8d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57c8d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594c25acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594c25aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594c25918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594c2240e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594c2240b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f57c8d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57c8d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57c8d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594c2240a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (2883 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2884 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6405c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6405c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6405ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2988d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2988d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2988d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2988ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c64055fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c64055fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6405448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6401f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6401f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2988ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2988cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2988cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6401f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (2885 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555dd0c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555dd0c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555dd0ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f524e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f524e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f524e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f524e631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555dd05fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555dd05fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555dd0448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555dccf3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555dccf3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f524e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f524e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f524e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555dccf3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (2886 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056486c317eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056486c314e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056486c31862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03d7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03d738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03d7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03d731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056486c2adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056486c2ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056486c2928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056486bf41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056486bf41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03d731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03d731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03d731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056486bf41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (2887 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055584cfb1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055584cfaee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055584cfb262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68ab133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68ab18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68ab133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68ab11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055584cf47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055584cf47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055584cf2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055584cbdbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055584cbdbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f68ab11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68ab11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68ab11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055584cbdba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (2888 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | % # | ... # `---data was truncated (10240/13690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1f9017eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f1f9014e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f1f901862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc022533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc02258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc022533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc02251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1f8fadbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f1f8fada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f1f8f928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f1f8c41e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f1f8c41b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc02251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc02251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc02251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1f8c41a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (2889 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (2890 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617f3790eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005617f378de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005617f379162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f008281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00828725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f008281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0082803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617f3726bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005617f3726a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005617f370b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005617f33bae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005617f33bab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0082804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00828050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00828050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617f33baa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (2891 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (2892 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (2893 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad85d37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ad85d34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ad85d3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f18849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f18849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f18831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad85ccdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ad85ccda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ad85cb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ad85961e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ad85961b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f18832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f188330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad85961a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (2894 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056220f395eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056220f392e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056220f39662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8e9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8e9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8e9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8e9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056220f32bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056220f32ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056220f3108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056220efbfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056220efbfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8e9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8e9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8e9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056220efbfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (2895 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff670bfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ff670bce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ff670c062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91abf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff67055bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ff67055a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ff6703a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ff66ce9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ff66ce9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f91abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff66ce9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (2896 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9a876aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c9a8767e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c9a876b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f16733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f1678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f16733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f1671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9a8700bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c9a8700a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c9a86e58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c9a8394e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c9a8394b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f1671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f1671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f1671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9a8394a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (2897 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (2898 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aab4e70eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aab4e6de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aab4e7162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f769ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f769ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f769ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f769ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aab4e06bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aab4e06a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aab4deb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aab4a9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aab4a9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f769ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f769ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f769ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aab4a9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (2899 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (2900 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8c25f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f8c25ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f8c25f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b56d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b56d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b56d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b56d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8c2586bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f8c2586a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f8c256b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f8c221ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f8c221ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0b56d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b56d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b56d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8c221aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (2901 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557a3842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557a383fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557a384362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01a5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01a5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01a5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01a5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557a37d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557a37d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557a37bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557a346ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557a346cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f01a5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01a5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01a5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557a346ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2902 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca # | ... # `---data was truncated (10240/12137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d06dc6deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d06dc6ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d06dc6e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bbb733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bbb78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bbb733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bbb71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d06dc03bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d06dc03a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d06dbe88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d06d897e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d06d897b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bbb71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bbb71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bbb71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d06d897a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (2903 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2904 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c57f1eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c57f1e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c57f1eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc95b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc95b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc95b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc95b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c57f180bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c57f180a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c57f1658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c57ee14e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c57ee14b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc95b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc95b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc95b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c57ee14a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (2905 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a4e0dfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556a4e0dce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556a4e0e062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce1621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce162725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce1621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce16203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a4e075bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556a4e075a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556a4e05a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556a4dd09e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556a4dd09b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce16204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce162050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce162050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a4dd09a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (2906 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (2907 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563188ac8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563188ac5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563188ac962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c5d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c5d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c5d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c5d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563188a5ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563188a5ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563188a438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005631886f2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005631886f2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2c5d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c5d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c5d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631886f2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (2908 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd79d0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fd79d0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fd79d0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f573cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f573cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f573cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f573caed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd79ca4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fd79ca4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fd79c898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fd79938e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fd79938b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f573caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f573caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f573caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd79938a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (2909 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/18691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d842193eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d842190e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d84219462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe797e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe797ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe797e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe797e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d842129bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d842129a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d84210e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d841dbde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d841dbdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe797e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe797e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe797e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d841dbda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (2910 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624f46a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624f46a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624f46a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f118be1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f118be725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f118be1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f118be03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624f463dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624f463da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624f46228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624f42d1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624f42d1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f118be04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f118be050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f118be050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624f42d1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (2911 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (2912 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1104e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1104e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1104e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa40d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa40d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa40d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa40d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a11047abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a11047aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a11045f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a11010ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a11010eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa40d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa40d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa40d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a11010ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (2913 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfcb8b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfcb8b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfcb8b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f671ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f671baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f671ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f671ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfcb84ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfcb84ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfcb8338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfcb4e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfcb4e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f671ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f671ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f671ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfcb4e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (2914 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/83088) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598457b9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598457b6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598457ba62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76fff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76fff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76fff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76fff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055984574fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055984574fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598457348b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598453e3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598453e3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76fff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76fff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76fff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598453e3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (2915 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056082b05beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056082b058e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056082b05c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1b1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1b118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1b1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1b111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056082aff1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056082aff1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056082afd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056082ac85e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056082ac85b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1b111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1b111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1b111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056082ac85a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (2916 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559997702eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599976ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055999770362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac96133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac9618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac96133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac9611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559997698bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559997698a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055999767d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055999732ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055999732cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac9611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac9611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac9611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055999732ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (2917 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, # | ... # `---data was truncated (10240/27986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647654b4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005647654b1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005647654b562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83bfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83bfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83bfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83bfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056476544abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056476544aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056476542f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005647650dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005647650deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f83bfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83bfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83bfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647650dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (2918 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641af4f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005641af4f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005641af4fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f26449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f26449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f26431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641af48fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005641af48fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005641af4748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005641af123e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005641af123b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f26432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641af123a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (2919 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624c0e3ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624c0e39e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624c0e3d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f836cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f836cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f836cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f836cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624c0dd2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624c0dd2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624c0db78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624c0a66e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624c0a66b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f836cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f836cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f836cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624c0a66a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (2920 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/11849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607f690feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607f690ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607f691062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8a0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8a04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8a0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8a0431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607f68a5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607f68a5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607f688a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607f6539e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607f6539b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb8a0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8a04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8a04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607f6539a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2921 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4090a1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f40909ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f4090a262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bbfa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bbfaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bbfa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bbfa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f409037bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f409037a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f40901c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f408ccbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f408ccbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0bbfa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bbfa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bbfa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f408ccba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (2922 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (2923 of 27910) ******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32-unknown-unknown" # | # | %struct.asc = type { i8, i16, i32, i32, float, double } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %0 = load i32, ptr %argp.next, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16 # | store ptr %argp.next2, ptr %va, align 4 # | %2 = load double, ptr %1, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %2 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11 # | %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load i32, ptr %argp.next, align 8, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0) # | store <2 x i64> %call, ptr %r, align 16, !tbaa !9 # | ret void # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr n # | ... # `---data was truncated (10240/20646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default)' --expand-variadics-override=optimize -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default) --expand-variadics-override=optimize -o - # | #0 0x000055639bba5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055639bba2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055639bba662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f461bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f461bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f461bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f461bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055639bb3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055639bb3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055639bb208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055639b7cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055639b7cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f461bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f461bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f461bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055639b7cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (2924 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568f41a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005568f41a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005568f41a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ec6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ec655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ec6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ec64ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568f4139bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005568f4139a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005568f411e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005568f3dcde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005568f3dcdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0ec64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ec64ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ec64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568f3dcda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (2925 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bba82aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556bba827e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556bba82b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3b3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3b3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3b3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3b3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bba7c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556bba7c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556bba7a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556bba454e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556bba454b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3b3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3b3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3b3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bba454a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (2926 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565813c8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565813c5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565813c962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdff1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdff138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdff1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdff131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055658135ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055658135ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565813438b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556580ff2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556580ff2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdff131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdff131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdff131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556580ff2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (2927 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (2928 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558edee28eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558edee25e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558edee2962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faca8f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faca8f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faca8f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faca8eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ededbebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ededbea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ededa38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558edea52e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558edea52b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faca8eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faca8eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faca8eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558edea52a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (2929 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b942e2deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b942e2ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b942e2e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33b9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33b9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33b9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33b9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b942dc3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b942dc3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b942da88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b942a57e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b942a57b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f33b9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33b9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33b9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b942a57a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (2930 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646124a0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056461249de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005646124a162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ba3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ba32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ba3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ba3231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564612436bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564612436a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056461241b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005646120cae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005646120cab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8ba3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ba32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ba32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646120caa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (2931 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2920e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b2920e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b2920e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a69849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a69849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a69831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b29207bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b29207ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b2920608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b291d0fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b291d0fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a69832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a698330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b291d0fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (2932 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056534b546eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056534b543e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056534b54762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9319449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9319449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9319431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056534b4dcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056534b4dca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056534b4c18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056534b170e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056534b170b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9319432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93194330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056534b170a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (2933 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (2934 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581a41f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581a41f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581a41f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f186e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f186e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f186e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f186e831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581a4189bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005581a4189a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581a416e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005581a3e1de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005581a3e1db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f186e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f186e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f186e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581a3e1da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (2935 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e45366eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555e45363e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555e4536762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2999849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2999849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2999831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e452fcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555e452fca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555e452e18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555e44f90e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555e44f90b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2999832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29998330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e44f90a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (2936 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cfe8e9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564cfe8e6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564cfe8ea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8f041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8f04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8f041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8f0403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cfe87fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564cfe87fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564cfe8648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564cfe513e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564cfe513b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe8f0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8f04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8f04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cfe513a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (2937 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (2938 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627f4073eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627f4070e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627f407462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c8e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c8e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c8e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c8e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627f4009bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005627f4009a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627f3fee8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005627f3c9de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005627f3c9db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c8e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c8e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c8e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627f3c9da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (2939 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596918a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005596918a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005596918a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a97933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a9798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a97933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a9791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559691839bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559691839a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055969181e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005596914cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005596914cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6a9791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a9791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a9791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596914cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (2940 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056145b47deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056145b47ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056145b47e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f860a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f860a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f860a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f860a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056145b413bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056145b413a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056145b3f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056145b0a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056145b0a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f860a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f860a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f860a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056145b0a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (2941 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (2942 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565d7e4feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565d7e4ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565d7e5062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6bcb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6bcb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6bcb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6bcb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565d7de5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565d7de5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565d7dca8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565d7a79e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565d7a79b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6bcb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6bcb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6bcb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565d7a79a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (2943 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056551dfadeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056551dfaae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056551dfae62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc28f105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc28f15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc28f105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc28f0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056551df43bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056551df43a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056551df288b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056551dbd7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056551dbd7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc28f0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc28f0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc28f0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056551dbd7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (2944 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598c203beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005598c2038e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005598c203c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe473533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe47358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe473533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe47351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598c1fd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005598c1fd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005598c1fb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005598c1c65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005598c1c65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe47351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe47351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe47351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598c1c65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2945 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632dc02aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005632dc027e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005632dc02b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9374c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9374c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9374c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9374c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632dbfc0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005632dbfc0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632dbfa58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005632dbc54e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005632dbc54b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9374c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9374c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9374c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632dbc54a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (2946 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e829deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564e829dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564e829df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2faa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e82974bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564e82974a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564e829598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564e82608e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564e82608b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd2faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2faa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e82608a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (2947 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b197610eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b19760de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b19761162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1cf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1cf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1cf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1cf71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1975a6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b1975a6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b19758b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b19723ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b19723ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd1cf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1cf71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1cf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b19723aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (2948 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb99db1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb99daee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb99db262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93d3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93d398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93d3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93d391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb99d47bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb99d47a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb99d2c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb999dbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb999dbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f93d391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93d391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93d391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb999dba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (2949 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe3de6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe3de6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe3de6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a79849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a798a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a79849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a79831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe3de04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe3de04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe3dde98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe3da98e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe3da98b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a79832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a798330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a798330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe3da98a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2950 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565110c9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565110c98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565110c9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbedd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbedd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbedd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbedd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565110c31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000565110c31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000565110c168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005651108c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005651108c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbedd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbedd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbedd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651108c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (2951 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (2952 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649a0716eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005649a0713e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005649a071762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f0a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649a06acbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005649a06aca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005649a06918b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005649a0340e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005649a0340b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649a0340a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (2953 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ba44a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563ba44a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563ba44a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9591f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9591f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9591f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9591f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ba443bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563ba443ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563ba44208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563ba40cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563ba40cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9591f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9591f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9591f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ba40cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (2954 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be99df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be99df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be99dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f581e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f581e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f581e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f581e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be99d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be99d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be99d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be99a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be99a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f581e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f581e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f581e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be99a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (2955 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.r # | ... # `---data was truncated (10240/33423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d11ee2feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d11ee2ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d11ee3062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0da0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0da0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0da0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0da0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d11edc5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d11edc5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d11edaa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d11ea59e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d11ea59b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0da0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0da0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0da0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d11ea59a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (2956 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583f61e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583f61e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583f61e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f395e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f395e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f395e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f395e203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583f617abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005583f617aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005583f615f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005583f5e0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005583f5e0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f395e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f395e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f395e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583f5e0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (2957 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (2958 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (2959 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0a8ac7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a0a8ac4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a0a8ac862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefc6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefc6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefc6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefc6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0a8a5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a0a8a5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a0a8a428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a0a86f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a0a86f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fefc6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefc6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefc6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0a86f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (2960 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d95233eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d95230e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d9523462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0cd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0cd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0cd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0cd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d951c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d951c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d951ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d94e5de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d94e5db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd0cd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0cd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0cd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d94e5da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (2961 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e435b8eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e435b8be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e435b8f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1404b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1404b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1404b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1404b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e435b24bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e435b24a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e435b098b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4357b8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4357b8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1404b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1404b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1404b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4357b8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (2962 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d643d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555d643d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555d643d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3bbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3bbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3bbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3bbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d6436dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555d6436da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555d643528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555d64001e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555d64001b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe3bbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3bbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3bbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d64001a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (2963 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cab4b0aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cab4b07e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cab4b0b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2986305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f298635c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2986305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29862ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cab4aa0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cab4aa0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cab4a858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cab4734e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cab4734b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f29862eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29862ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29862ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cab4734a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (2964 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561247295eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561247292e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056124729662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff901305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff90135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff901305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9012ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056124722bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056124722ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005612472108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561246ebfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561246ebfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9012eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9012ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9012ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561246ebfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2965 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648121f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648121f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648121f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc456249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4562a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc456249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc456231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056481218abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056481218aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056481216f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564811e1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564811e1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc456232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4562330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4562330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564811e1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (2966 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl. # | ... # `---data was truncated (10240/24951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dd80c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dd80c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dd80c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb35c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb35c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb35c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb35c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dd805cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dd805ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dd80418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dd7cf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dd7cf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb35c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb35c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb35c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dd7cf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2967 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2968 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function # | ... # `---data was truncated (10240/12439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d0e970eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d0e96de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d0e97162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6892733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f689278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6892733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f689271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d0e906bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d0e906a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d0e8eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d0e59ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d0e59ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f689271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f689271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f689271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d0e59aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (2969 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eab68ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eab68cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eab68cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f657bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f657bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f657bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f657baed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eab6864bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eab6864a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eab68498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eab64f8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eab64f8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f657baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f657baef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f657baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eab64f8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (2970 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (2971 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/linker-diagnostic.ll (2972 of 27910) ******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # | #0 0x0000563f468f3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563f468f0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563f468f462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9944e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9944ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9944e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9944e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f46889bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563f46889a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563f4686e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563f4651de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563f4651db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9944e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9944e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9944e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f4651da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2973 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564616b7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005564616b4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005564616b862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b0f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b0f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b0f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b0f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055646164dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055646164da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005564616328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005564612e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005564612e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3b0f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b0f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b0f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564612e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2974 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560630f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560630f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560630f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0291f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0291f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0291f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0291f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055606308abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055606308aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055606306f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556062d1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556062d1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0291f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0291f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0291f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556062d1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (2975 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (2976 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1( # | ... # `---data was truncated (10240/32505) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb2c8d4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb2c8d1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb2c8d562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f690f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f690f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f690f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f690f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb2c86abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb2c86aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb2c84f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb2c4fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb2c4feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f690f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f690f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f690f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb2c4fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (2977 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbc2502eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bbc24ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bbc250362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b77449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b774a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b77449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b77431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbc2498bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bbc2498a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bbc247d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bbc212ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bbc212cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b77432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b774330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b774330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbc212ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (2978 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056047a59eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056047a59be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056047a59f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bd5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bd538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bd5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bd531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056047a534bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056047a534a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056047a5198b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056047a1c8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056047a1c8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3bd531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bd531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bd531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056047a1c8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (2979 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (2980 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efcc775eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055efcc772e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055efcc77662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62f8305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62f835c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62f8305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62f82ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efcc70bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055efcc70ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055efcc6f08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055efcc39fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055efcc39fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62f82eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62f82ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62f82ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efcc39fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (2981 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd680b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dd680b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dd680b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad49849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad49849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad49831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd6804bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dd6804ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dd680308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dd67cdfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dd67cdfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fad49832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad498330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd67cdfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (2982 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555de0c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005555de0c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005555de0c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb901649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9016a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb901649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb901631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555de05cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005555de05ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005555de0418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005555ddcf0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005555ddcf0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb901632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9016330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9016330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555ddcf0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (2983 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626b70b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626b70b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626b70b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cdcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cdcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cdcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cdcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626b704ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626b704ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626b70338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626b6ce2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626b6ce2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5cdcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cdcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cdcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626b6ce2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (2984 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560337565eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560337562e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056033756662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f846fa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f846fa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f846fa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f846fa03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603374fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005603374fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005603374e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056033718fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056033718fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f846fa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f846fa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f846fa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056033718fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (2985 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, p # | ... # `---data was truncated (10240/33198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566380a7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005566380a4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005566380a862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fbd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fbd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fbd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fbd8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055663803dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055663803da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005566380228b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556637cd1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556637cd1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0fbd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fbd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fbd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556637cd1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (2986 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634fd989eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634fd986e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634fd98a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54e3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54e32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54e3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54e3231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634fd91fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634fd91fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634fd9048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634fd5b3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634fd5b3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f54e3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54e32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54e32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634fd5b3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (2987 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %vs2, bflo # | ... # `---data was truncated (10240/43940) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d025c21eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d025c1ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d025c2262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc23249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc232a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc23249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc23231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d025bb7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d025bb7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d025b9c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d02584be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d02584bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc23232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc232330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc232330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d02584ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (2988 of 27910) ******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.MyTask = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { ptr } # | %"struct.std::suspend_always" = type { i8 } # | %struct.Awaiter = type { ptr } # | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" } # | # | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any # | # | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type15await_transformERKi = comdat any # | # | $_ZN7Awaiter11await_readyEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any # | # | $_ZN7Awaiter12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type13final_suspendEv = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | @g_array = global [32 x i32] zeroinitializer, align 16 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local ptr @_Z6FooBarv() #0 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1 # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6 # | store ptr @_Z6FooBarv.resume, ptr %call, align 8 # | %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup # | %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8 # | store ptr %0, ptr %destroy.addr, align 8 # | %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18 # | %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24 # | %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32 # | %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40 # | %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48 # | %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56 # | %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19 # | %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16 # | %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call1, ptr %coerce.dive2, align 8 # | call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | br i1 %call3, label %init.ready, label %CoroSave # | # | CoroSave: ; preds = %entry # | %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 0, ptr %index.addr39, align 1 # | call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | init.ready: ; preds = %entry # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | store ptr @g_array, ptr %__range1.reload.addr, align 8 # | store ptr @g_array, ptr %__begin1.reload.addr, align 8 # | store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %init.ready # | %1 = load ptr, ptr %__begin1.reload.addr, align 8 # | %2 = load ptr, ptr %__end1.reload.addr, align 8 # | %cmp = icmp ne ptr %1, %2 # | br i1 %cmp, label %for.body, label %coro.final # | # | for.body: ; preds = %for.cond # | %3 = load ptr, ptr %__begin1.reload.addr, align 8 # | store ptr %3, ptr %x.reload.addr, align 8 # | %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2 # | %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4) # | %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0 # | store ptr %call5, ptr %coerce.dive6, align 8 # | %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | br i1 %call7, label %await.ready, label %CoroSave27 # | # | CoroSave27: ; preds = %for.body # | %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 1, ptr %index.addr40, align 1 # | %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call) # | %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0 # | %7 = load ptr, ptr %6, align 8 # | call void %7(ptr %5) # | br label %AfterCoroEnd # | # | await.ready: ; preds = %for.body # | call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | %cond = icmp eq i32 0, 0 # | %cond26 = icmp eq i32 0, 0 # | br i1 %cond26, label %for.inc, label %coro.final # | # | for.inc: ; preds = %await.ready # | %8 = load ptr, ptr %__begin1.reload.addr, align 8 # | %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1 # | store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8 # | br label %for.cond # | # | coro.final: ; preds = %await.ready, %for.cond # | call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7 # | %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | br i1 %call20, label %final.ready, label %CoroSave31 # | # | CoroSave31: ; preds = %coro.final # | store ptr null, ptr %call, align 8 # | call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | final.ready: ; preds = %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | %9 = icmp ne ptr %call, null # | br i1 %9, label %coro.free, label %AfterCoroEnd # | # | coro.free: ; preds = %final.ready # | call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7 # | br label %AfterCoroEnd # | # | AfterCoroEnd: ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave # | %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0 # | %10 = load ptr, ptr %coerce.dive25, align 8 # | ret ptr %10 # | } # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %this.addr = alloca ptr, align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call, ptr %coerce.dive2, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false) # | %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0 # | %0 = load ptr, ptr %coerce.dive4, align 8 # | ret ptr %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret i1 false # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 { # | entry: # | %.addr = alloca ptr, align 8 # | %.addr1 = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %0, ptr %.addr, align 8 # | store ptr %1, ptr %.addr1, align 8 # | %2 = load ptr, ptr %.addr, align 8 # | %3 = load ptr, ptr %.addr1, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7 # | # | ... # `---data was truncated (10240/37953) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # | #0 0x00005576c064deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576c064ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576c064e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e2921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e292725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e2921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e29203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576c05e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576c05e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576c05c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576c0277e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576c0277b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7e29204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e292050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e292050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576c0277a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (2989 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nx # | ... # `---data was truncated (10240/25567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613bec6eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005613bec6be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005613bec6f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08a8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08a80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08a8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08a8031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613bec04bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005613bec04a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005613bebe98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613be898e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613be898b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08a8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08a80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08a80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613be898a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (2990 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561bb6001eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561bb5ffee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561bb600262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67f0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67f0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67f0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67f0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bb5f97bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561bb5f97a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561bb5f7c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561bb5c2be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561bb5c2bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f67f0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67f0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67f0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bb5c2ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (2991 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f6c7d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f6c7cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f6c7d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a92733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a9278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a92733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a9271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f6c766bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f6c766a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f6c74b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f6c3fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f6c3fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7a9271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a9271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a9271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f6c3faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (2992 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6b3253eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6b3250e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6b325462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d0a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d0a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d0a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d0a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6b31e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b6b31e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b6b31ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6b2e7de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6b2e7db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1d0a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d0a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d0a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6b2e7da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (2993 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055719234eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055719234be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055719234f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0788049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07880a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0788049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0788031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571922e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005571922e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005571922c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557191f78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557191f78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0788032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07880330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07880330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557191f78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (2994 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634c4df9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005634c4df6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005634c4dfa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f049f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f049f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f049f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f049f831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634c4d8fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005634c4d8fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005634c4d748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005634c4a23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005634c4a23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f049f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f049f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f049f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634c4a23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (2995 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c62c43feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c62c43ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c62c44062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb98c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb98c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb98c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb98c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c62c3d5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c62c3d5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c62c3ba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c62c069e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c62c069b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb98c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb98c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb98c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c62c069a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (2996 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605b7ea3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005605b7ea0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005605b7ea462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd959933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd95998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd959933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd95991b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605b7e39bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005605b7e39a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005605b7e1e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005605b7acde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005605b7acdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd95991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd95991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd95991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605b7acda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (2997 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7bc370eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7bc36de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7bc37162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb31b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb31b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb31b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb31b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7bc306bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7bc306a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7bc2eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7bbf9ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7bbf9ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb31b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb31b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb31b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7bbf9aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (2998 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654e12f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654e12f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654e12fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a0f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a0f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a0f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a0f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654e128fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654e128fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654e12748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654e0f23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654e0f23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a0f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a0f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a0f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654e0f23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (2999 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea58d94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ea58d91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ea58d9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8e3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8e3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8e3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8e3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea58d2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ea58d2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ea58d0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ea589bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ea589beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff8e3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8e3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8e3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea589bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (3000 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056464e389eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056464e386e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056464e38a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d02f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d02f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d02f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d02f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056464e31fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056464e31fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056464e3048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056464dfb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056464dfb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d02f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d02f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d02f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056464dfb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (3001 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6cae32eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e6cae2fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e6cae3362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35d7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35d7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35d7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35d7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6cadc8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6cadc8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e6cadad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e6caa5ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e6caa5cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35d7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35d7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35d7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6caa5ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (3002 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ace50ceeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ace50cbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ace50cf62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1d0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1d038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1d0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1d031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ace5064bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ace5064a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ace50498b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ace4cf8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ace4cf8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1d031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1d031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1d031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ace4cf8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (3003 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffed24deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ffed24ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ffed24e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8bdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8bdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8bdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8bdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffed1e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ffed1e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ffed1c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ffece77e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ffece77b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd8bdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8bdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8bdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffece77a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (3004 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (3005 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576ba2c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005576ba2bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005576ba2c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b3e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b3e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b3e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b3e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576ba258bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005576ba258a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005576ba23d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005576b9eece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005576b9eecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6b3e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b3e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b3e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576b9eeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (3006 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dca966eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dca966be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dca966f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf7cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf7cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf7cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf7cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dca9604bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dca9604a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dca95e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dca9298e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dca9298b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf7cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf7cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf7cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dca9298a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (3007 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607b7893eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005607b7890e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005607b789462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c18a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c18aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c18a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c18a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607b7829bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005607b7829a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005607b780e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005607b74bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005607b74bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3c18a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c18a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c18a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607b74bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (3008 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca # | ... # `---data was truncated (10240/43625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e15a709eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e15a706e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e15a70a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0232733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f023278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0232733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f023271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e15a69fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e15a69fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e15a6848b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e15a333e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e15a333b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f023271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f023271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f023271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e15a333a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (3009 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b8f61ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559b8f619e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559b8f61d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f038cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f038cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f038cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f038cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b8f5b2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559b8f5b2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559b8f5978b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559b8f246e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559b8f246b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f038cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f038cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f038cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b8f246a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (3010 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c1144beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c11448e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c1144c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb69ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb69eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb69ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb69ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c113e1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c113e1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c113c68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c11075e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c11075b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb69ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb69ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb69ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c11075a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (3011 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a9d817eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563a9d814e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563a9d81862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02a9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02a998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02a9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02a991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a9d7adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563a9d7ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563a9d7928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563a9d441e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563a9d441b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f02a991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02a991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02a991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a9d441a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (3012 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d828e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d828dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d828e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc78649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc786a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc78649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc78631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d82877bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d82877a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d8285c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d8250be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d8250bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc78632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc786330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc786330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d8250ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (3013 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6bc711eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c6bc70ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c6bc71262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ad9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ad9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ad9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ad9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6bc6a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c6bc6a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c6bc68c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c6bc33be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c6bc33bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ad9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ad9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ad9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6bc33ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (3014 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cc499aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562cc4997e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562cc499b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb77733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb7778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb77733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb7771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cc4930bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562cc4930a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562cc49158b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562cc45c4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562cc45c4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007feb7771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb7771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb7771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cc45c4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (3015 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (3016 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056147d4d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056147d4d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056147d4d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2440e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2440ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2440e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2440e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056147d46cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056147d46ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056147d4518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056147d100e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056147d100b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2440e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2440e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2440e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056147d100a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (3017 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8ad047eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8ad044e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8ad04862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39e5505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39e555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39e5505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39e54ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8acfddbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8acfdda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8acfc28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8acc71e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8acc71b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39e54eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39e54ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39e54ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8acc71a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (3018 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557490687eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557490684e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055749068862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc124449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc124449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc124431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055749061dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055749061da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574906028b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574902b1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574902b1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc124432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574902b1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (3019 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cd6fcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555cd6fc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555cd6fcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea7df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea7df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea7df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea7df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cd6f62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555cd6f62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555cd6f478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cd6bf6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cd6bf6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fea7df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea7df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea7df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cd6bf6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm64-crc32.c (3020 of 27910) ******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32x(i32, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a548f80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a548f7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a548f8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f5df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f5df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f5df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f5df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a548f16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a548f16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a548efb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a548baae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a548baab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2f5df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f5df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f5df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a548baaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (3021 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583313e3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005583313e0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005583313e462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0c5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0c5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0c5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0c5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558331379bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558331379a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055833135e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055833100de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055833100db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa0c5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0c5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0c5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055833100da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (3022 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdc038aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fdc0387e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fdc038b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa057849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa057849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa057831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdc0320bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fdc0320a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fdc03058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fdbffb4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fdbffb4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa057832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdbffb4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (3023 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_ # | ... # `---data was truncated (10240/11895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c7a2f7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c7a2f4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c7a2f862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4522c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4522ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4522c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4522c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c7a28dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c7a28da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c7a2728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c79f21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c79f21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4522c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4522c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4522c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c79f21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/SystemZ/zvector.c (3024 of 27910) ******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c" # | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" # | target triple = "s390x-unknown-linux-gnu" # | # | @sc2 = global <16 x i8> zeroinitializer, align 8 # | @sc = global <16 x i8> zeroinitializer, align 8 # | @uc2 = global <16 x i8> zeroinitializer, align 8 # | @uc = global <16 x i8> zeroinitializer, align 8 # | @ss2 = global <8 x i16> zeroinitializer, align 8 # | @ss = global <8 x i16> zeroinitializer, align 8 # | @us2 = global <8 x i16> zeroinitializer, align 8 # | @us = global <8 x i16> zeroinitializer, align 8 # | @si2 = global <4 x i32> zeroinitializer, align 8 # | @si = global <4 x i32> zeroinitializer, align 8 # | @ui2 = global <4 x i32> zeroinitializer, align 8 # | @ui = global <4 x i32> zeroinitializer, align 8 # | @sl2 = global <2 x i64> zeroinitializer, align 8 # | @sl = global <2 x i64> zeroinitializer, align 8 # | @ul2 = global <2 x i64> zeroinitializer, align 8 # | @ul = global <2 x i64> zeroinitializer, align 8 # | @slll2 = global <1 x i128> zeroinitializer, align 8 # | @slll = global <1 x i128> zeroinitializer, align 8 # | @ulll2 = global <1 x i128> zeroinitializer, align 8 # | @ulll = global <1 x i128> zeroinitializer, align 8 # | @fd2 = global <2 x double> zeroinitializer, align 8 # | @fd = global <2 x double> zeroinitializer, align 8 # | @bc2 = global <16 x i8> zeroinitializer, align 8 # | @bc = global <16 x i8> zeroinitializer, align 8 # | @bs2 = global <8 x i16> zeroinitializer, align 8 # | @bs = global <8 x i16> zeroinitializer, align 8 # | @bi2 = global <4 x i32> zeroinitializer, align 8 # | @bi = global <4 x i32> zeroinitializer, align 8 # | @bl2 = global <2 x i64> zeroinitializer, align 8 # | @bl = global <2 x i64> zeroinitializer, align 8 # | @blll2 = global <1 x i128> zeroinitializer, align 8 # | @blll = global <1 x i128> zeroinitializer, align 8 # | @cnt = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_assign() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_pos() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_neg() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %sub = sub <16 x i8> zeroinitializer, %0 # | store volatile <16 x i8> %sub, ptr @sc, align 8 # | %1 = load volatile <8 x i16>, ptr @ss2, align 8 # | %sub1 = sub <8 x i16> zeroinitializer, %1 # | store volatile <8 x i16> %sub1, ptr @ss, align 8 # | %2 = load volatile <4 x i32>, ptr @si2, align 8 # | %sub2 = sub <4 x i32> zeroinitializer, %2 # | store volatile <4 x i32> %sub2, ptr @si, align 8 # | %3 = load volatile <2 x i64>, ptr @sl2, align 8 # | %sub3 = sub <2 x i64> zeroinitializer, %3 # | store volatile <2 x i64> %sub3, ptr @sl, align 8 # | %4 = load volatile <1 x i128>, ptr @slll2, align 8 # | %sub4 = sub <1 x i128> zeroinitializer, %4 # | store volatile <1 x i128> %sub4, ptr @slll, align 8 # | %5 = load volatile <2 x double>, ptr @fd2, align 8 # | %fneg = fneg <2 x double> %5 # | store volatile <2 x double> %fneg, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_preinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_postinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_predec() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %dec = add <16 x i8> %0, splat (i8 -1) # | store volatile <16 x i8> %dec, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %dec1 = add <16 x i8> %1, splat (i8 -1) # | store volatile <16 x i8> %dec1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %dec2 = add <8 x i16> %2, splat (i16 -1) # | store volatile <8 x i16> %dec2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %dec3 = add <8 x i16> %3, splat (i16 -1) # | store volatile <8 x i16> %dec3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %dec4 = add <4 x i32> %4, splat (i32 -1) # | store volatile <4 x i32> %dec4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %dec5 = add <4 x i32> %5, splat (i32 -1) # | store volatile <4 x i32> %dec5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %dec6 = add <2 x i64> %6, splat (i64 -1) # | store volatile <2 x i64> %dec6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %dec7 = add <2 x i64> %7, splat (i64 -1) # | store volatile <2 x i64> %dec7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %dec8 = add <1 x i128> %8, splat (i128 -1) # | store volatile <1 x i128> %dec8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %dec # | ... # `---data was truncated (10240/152876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e5f365eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e5f362e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e5f36662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70a9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70a938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70a9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70a931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e5f2fbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e5f2fba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e5f2e08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e5ef8fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e5ef8fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f70a931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70a931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70a931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e5ef8fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (3025 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560142d3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560142d3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560142d3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4fd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4fd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4fd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4fd231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560142cd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560142cd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560142cb98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560142968e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560142968b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4fd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4fd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4fd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560142968a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (3026 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (3027 of 27910) ******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s0, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x i32> # | %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 # | ... # `---data was truncated (10240/18482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005570f4082eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570f407fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570f408362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa318b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa318b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa318b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa318b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570f4018bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570f4018a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570f3ffd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570f3cace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570f3cacb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa318b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa318b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa318b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570f3caca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (3028 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.add # | ... # `---data was truncated (10240/153913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b851f97eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b851f94e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b851f9862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9b781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9b78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9b781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9b7803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b851f2dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b851f2da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b851f128b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b851bc1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b851bc1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9b7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9b78050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9b78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b851bc1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (3029 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627288d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005627288d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005627288d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc7a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc7a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc7a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc7a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056272886ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056272886ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005627288538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562728502e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562728502b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcc7a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc7a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc7a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562728502a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (3030 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d92382eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d92382be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d92382f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faabfa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faabfa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faabfa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faabfa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9237c4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d9237c4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d9237a98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d923458e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d923458b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007faabfa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faabfa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faabfa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d923458a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (3031 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556240842eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055624083fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055624084362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61c9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61c98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61c9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61c9831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562407d8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005562407d8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005562407bd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055624046ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055624046cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f61c9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61c98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61c98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055624046ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (3032 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d59d9c6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d59d9c3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d59d9c762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc601933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc60198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc601933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc60191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d59d95cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d59d95ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d59d9418b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d59d5f0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d59d5f0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc60191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc60191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc60191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d59d5f0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (3033 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611191b8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005611191b5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005611191b962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1092533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f109258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1092533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f109251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056111914ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056111914ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005611191338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561118de2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561118de2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f109251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f109251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f109251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561118de2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (3034 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caf0bb7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055caf0bb4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055caf0bb862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6881333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f688138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6881333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f688131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caf0b4dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055caf0b4da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055caf0b328b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055caf07e1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055caf07e1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f688131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f688131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f688131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caf07e1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (3035 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed0de0ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ed0de09e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ed0de0d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d75b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d75b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d75b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d75b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed0dda2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ed0dda2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ed0dd878b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ed0da36e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ed0da36b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d75b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d75b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d75b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed0da36a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (3036 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.a # | ... # `---data was truncated (10240/32394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ce083eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ce083be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ce083f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0c0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0c0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0c0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0c0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ce07d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ce07d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ce07b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ce0468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ce0468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb0c0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0c0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0c0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ce0468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (3037 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056326818aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563268187e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056326818b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7f4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7f42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7f4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7f4231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563268120bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563268120a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005632681058b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563267db4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563267db4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd7f4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7f42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7f42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563267db4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (3038 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (3039 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604b93ebeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005604b93e8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005604b93ec62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6473849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64738a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6473849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6473831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604b9381bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005604b9381a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005604b93668b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005604b9015e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005604b9015b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6473832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64738330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64738330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604b9015a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (3040 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600c3512eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005600c350fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005600c351362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1621249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1621249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1621231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600c34a8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005600c34a8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005600c348d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600c313ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600c313cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1621232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16212330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600c313ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (3041 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565112667eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565112664e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056511266862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ee3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ee3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ee3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ee3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651125fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005651125fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005651125e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000565112291e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000565112291b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2ee3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ee3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ee3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565112291a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (3042 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f116e7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556f116e4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556f116e862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf44849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf448a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf44849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf44831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f1167dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556f1167da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556f116628b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556f11311e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556f11311b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbf44832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf448330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf448330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f11311a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (3043 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056130cabdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056130cabae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056130cabe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe114a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe114aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe114a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe114a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056130ca53bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056130ca53a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056130ca388b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056130c6e7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056130c6e7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe114a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe114a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe114a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056130c6e7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (3044 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de0f25ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055de0f259e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055de0f25d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb146849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb146849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb146831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de0f1f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055de0f1f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055de0f1d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055de0ee86e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055de0ee86b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb146832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1468330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de0ee86a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (3045 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c3b07feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556c3b07ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556c3b08062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fae449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fae4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fae449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fae431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c3b015bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556c3b015a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556c3affa8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556c3aca9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556c3aca9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1fae432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fae4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fae4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c3aca9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (3046 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588b4601eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005588b45fee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005588b460262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe324449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe324449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe324431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588b4597bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005588b4597a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005588b457c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005588b422be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005588b422bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe324432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588b422ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (3047 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c2152aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c21527e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c2152b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e42a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e42aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e42a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e42a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c214c0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c214c0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c214a58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c21154e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c21154b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e42a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e42a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e42a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c21154a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (3048 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595e4e3beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005595e4e38e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005595e4e3c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3576133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f357618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3576133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f357611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595e4dd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005595e4dd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005595e4db68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005595e4a65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005595e4a65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f357611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f357611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f357611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595e4a65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (3049 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (3050 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a58090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a5808de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a5809162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f094c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f094c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f094c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f094c203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a58026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a58026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a5800b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a57cbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a57cbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f094c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f094c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f094c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a57cbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (3051 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ... # `---data was truncated (10240/14904) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f64f43eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555f64f40e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555f64f4462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce86a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce86aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce86a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce86a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f64ed9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555f64ed9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555f64ebe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555f64b6de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555f64b6db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fce86a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce86a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce86a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f64b6da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (3052 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7e254deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f7e254ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f7e254e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f400f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f400f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f400f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f400f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7e24e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f7e24e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7e24c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7e2177e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7e2177b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f400f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f400f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f400f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7e2177a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (3053 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c733795eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c733792e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c73379662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7947449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7947449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7947431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c73372bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c73372ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c7337108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c7333bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c7333bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7947432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79474330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7333bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (3054 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574668b5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574668b2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574668b662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4bf449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4bf4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4bf449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4bf431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055746684bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055746684ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574668308b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574664dfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574664dfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd4bf432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4bf4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4bf4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574664dfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (3055 of 27910) ******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load bfloat, ptr %a.addr, align 2 # | %fpext = fpext bfloat %0 to float # | %fptrunc = fptrunc float %fpext to half # | ret half %fptrunc # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %fpext = fpext half %0 to float # | %fptrunc = fptrunc float %fpext to bfloat # | ret bfloat %fptrunc # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ec8e3eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562ec8e3be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562ec8e3f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37b0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37b08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37b0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37b0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ec8dd4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562ec8dd4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562ec8db98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562ec8a68e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562ec8a68b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f37b0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37b08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37b08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ec8a68a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (3056 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfd52bceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfd52b9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfd52bd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74b1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfd5252bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfd5252a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfd52378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfd4ee6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfd4ee6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f74b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfd4ee6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (3057 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8f0e69eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e8f0e66e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e8f0e6a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3ee71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8f0dffbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e8f0dffa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e8f0de48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e8f0a93e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e8f0a93b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc3ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f0a93a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (3058 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m4_bf16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vcreate_v_bf16mf4x2( %v0, %v1) #0 { # | entry: # | %v0.add # | ... # `---data was truncated (10240/71275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6984d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b6984cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b6984d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e0ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e0ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e0ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e0ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b698466bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b698466a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b69844b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b6980fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b6980fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4e0ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e0ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e0ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6980faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (3059 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (3060 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , pt # | ... # `---data was truncated (10240/32402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f31cfb4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f31cfb1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f31cfb562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1b2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1b2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1b2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1b2aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f31cf4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f31cf4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f31cf2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f31cbdee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f31cbdeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe1b2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1b2aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1b2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f31cbdea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (3061 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c23ef3feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c23ef3ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c23ef4062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9af7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9af7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9af7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9af7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c23eed5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c23eed5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c23eeba8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c23eb69e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c23eb69b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9af7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9af7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9af7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c23eb69a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (3062 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610bc595eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005610bc592e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005610bc59662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6c9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6c958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6c9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6c951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005610bc52bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005610bc52ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005610bc5108b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005610bc1bfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005610bc1bfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa6c951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6c951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6c951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610bc1bfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (3063 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2_m( %mask, # | ... # `---data was truncated (10240/13544) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcde039eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcde036e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcde03a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f303fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f303fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f303fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f303fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcddfcfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcddfcfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcddfb48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcddc63e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcddc63b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f303fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f303fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f303fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcddc63a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (3064 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635e7e24eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635e7e21e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635e7e2562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5d8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5d82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5d8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5d8231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635e7dbabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005635e7dbaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635e7d9f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005635e7a4ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005635e7a4eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5d8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5d82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5d82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635e7a4ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (3065 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (3066 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/26748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637922feeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637922fbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637922ff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f563d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f563d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f563d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f563d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563792294bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563792294a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637922798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563791f28e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563791f28b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f563d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f563d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f563d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563791f28a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (3067 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, ali # | ... # `---data was truncated (10240/33772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056146dc5aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056146dc57e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056146dc5b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1749a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1749aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1749a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1749a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056146dbf0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056146dbf0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056146dbd58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056146d884e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056146d884b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1749a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1749a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1749a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056146d884a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (3068 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654c0ccceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654c0cc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654c0ccd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbeacc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbeacca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbeacc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbeacc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654c0c62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654c0c62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654c0c478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654c08f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654c08f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbeacc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbeacc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbeacc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654c08f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (3069 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f267934eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f267931e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f26793562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5a6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5a695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5a6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5a68ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2678cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2678caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2678af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f26755ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f26755eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5a68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5a68ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5a68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f26755ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (3070 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c9a699eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560c9a696e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560c9a69a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0664733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f066478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0664733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f066471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c9a62fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560c9a62fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560c9a6148b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560c9a2c3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560c9a2c3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f066471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f066471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f066471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c9a2c3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (3071 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6f47c9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6f47c6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6f47ca62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff777333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff77738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff777333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff77731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6f475fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6f475fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6f47448b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6f43f3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6f43f3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff77731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff77731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff77731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6f43f3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (3072 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fa412beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559fa4128e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559fa412c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bcda1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bcda725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bcda1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bcda03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fa40c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559fa40c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559fa40a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559fa3d55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559fa3d55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9bcda04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bcda050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bcda050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fa3d55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (3073 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8b7853eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8b7850e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8b785462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5064333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f506438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5064333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f506431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8b77e9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8b77e9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8b77ce8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8b747de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8b747db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f506431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f506431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f506431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8b747da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (3074 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056193c65ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056193c659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056193c65d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd54d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd54d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd54d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd54d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056193c5f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056193c5f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056193c5d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056193c286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056193c286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbd54d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd54d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd54d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056193c286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (3075 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.abs.i32(i32 %0, i1 true) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.abs.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp sle i32 %0, %1 # | %sle = zext i1 %2 to i32 # | ret i32 %sle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp ule i32 %0, %1 # | %sleu = zext i1 %2 to i32 # | ret i32 %sleu # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = sext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exths = sext i16 %1 to i32 # | ret i32 %exths # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = zext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exthz = zext i16 %1 to i32 # | ret i32 %exthz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = sext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbs = sext i8 %1 to i32 # | ret i32 %extbs # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = zext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbz = zext i8 %1 to i32 # | ret i32 %extbz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xcvalu1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca19df7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ca19df4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ca19df862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff207849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff207849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff207831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca19d8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ca19d8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ca19d728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ca19a21e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ca19a21b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff207832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2078330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca19a21a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (3076 of 27910) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1 # | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ae8991eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556ae898ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556ae899262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3eac905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3eac95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3eac905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3eac8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ae8927bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556ae8927a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556ae890c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556ae85bbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556ae85bbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3eac8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3eac8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3eac8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ae85bba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (3077 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559442ef0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559442eede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559442ef162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0938b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0938b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0938b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0938aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559442e86bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559442e86a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559442e6b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559442b1ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559442b1ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0938aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0938aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0938aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559442b1aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (3078 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 nounde # | ... # `---data was truncated (10240/26592) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557821d49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557821d46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557821d4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb72e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb72ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb72e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb72e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557821cdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557821cdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557821cc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557821973e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557821973b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb72e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb72e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb72e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557821973a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (3079 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (3080 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f248718eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f248715e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f24871962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f15f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f15f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f15f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f15f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2486aebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f2486aea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f2486938b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f248342e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f248342b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0f15f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f15f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f15f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f248342a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (3081 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bfb04abeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bfb04a8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bfb04ac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febc2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febc2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febc2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febc2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfb0441bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bfb0441a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bfb04268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bfb00d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bfb00d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febc2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febc2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febc2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfb00d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (3082 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055556aa2beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055556aa28e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055556aa2c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf26133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf2618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf26133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf2611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055556a9c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055556a9c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055556a9a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055556a655e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055556a655b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdf2611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf2611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf2611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055556a655a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (3083 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f814c66eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f814c63e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f814c6762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc5b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc5b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc5b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc5b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f814bfcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f814bfca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f814be18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f814890e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f814890b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbc5b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc5b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc5b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f814890a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (3084 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i6 # | ... # `---data was truncated (10240/11946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056228a5aaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056228a5a7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056228a5ab62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a03333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a0338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a03333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a0331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056228a540bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056228a540a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056228a5258b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056228a1d4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056228a1d4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9a0331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a0331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a0331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056228a1d4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (3085 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f083ffdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f083ffae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f083ffe62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f824701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82470725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f824701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8247003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f083f93bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f083f93a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f083f788b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f083c27e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f083c27b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8247004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82470050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82470050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f083c27a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (3086 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (3087 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056294da6feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056294da6ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056294da7062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c55049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c550a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c55049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c55031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056294da05bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056294da05a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056294d9ea8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056294d699e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056294d699b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0c55032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c550330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c550330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056294d699a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (3088 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056253fdbbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056253fdb8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056253fdbc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf4cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf4cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf4cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf4cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056253fd51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056253fd51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056253fd368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056253f9e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056253f9e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcf4cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf4cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf4cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056253f9e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (3089 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fba049eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557fba046e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557fba04a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6161e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6161ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6161e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6161e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fb9fdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557fb9fdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557fb9fc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557fb9c73e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557fb9c73b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6161e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6161e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6161e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fb9c73a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (3090 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594fdff5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005594fdff2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005594fdff662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5f6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5f695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5f6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5f68ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594fdf8bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594fdf8ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594fdf708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005594fdc1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005594fdc1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5f68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5f68ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5f68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594fdc1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (3091 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/26984) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa62e02eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055aa62dffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055aa62e0362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8eeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa62d98bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055aa62d98a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055aa62d7d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055aa62a2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055aa62a2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa8eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa62a2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (3092 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635433eeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005635433ebe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005635433ef62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92a5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92a54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92a5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92a5431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563543384bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563543384a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005635433698b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563543018e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563543018b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f92a5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92a54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92a54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563543018a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (3093 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626e9ac7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005626e9ac4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005626e9ac862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2db3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2db378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2db3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2db371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005626e9a5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005626e9a5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005626e9a428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005626e96f1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005626e96f1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2db371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2db371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2db371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005626e96f1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (3094 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b053d7ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b053d79e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b053d7d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd45da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd45daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd45da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd45da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b053d12bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b053d12a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b053cf78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b0539a6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b0539a6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd45da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd45da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd45da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0539a6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (3095 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056433ecbceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056433ecb9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056433ecbd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a19733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a1978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a19733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a1971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056433ec52bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056433ec52a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056433ec378b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056433e8e6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056433e8e6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8a1971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a1971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a1971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056433e8e6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (3096 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577995f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005577995ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005577995f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc772a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc772a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc772a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc772a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557799586bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557799586a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055779956b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055779921ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055779921ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc772a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc772a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc772a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055779921aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (3097 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d922c0feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d922c0ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d922c1062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdefc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdefc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdefc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdefc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d922ba5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d922ba5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d922b8a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d922839e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d922839b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdefc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdefc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdefc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d922839a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (3098 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/32709) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f99405eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558f99402e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558f9940662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe668e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe668e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe668e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe668e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f9939bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558f9939ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558f993808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558f9902fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558f9902fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe668e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe668e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe668e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f9902fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (3099 of 27910) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # | #0 0x000055680307beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556803078e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055680307c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3abd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3abd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3abd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3abd8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556803011bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556803011a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556802ff68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556802ca5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556802ca5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3abd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3abd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3abd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556802ca5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (3100 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621fe3d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621fe3d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621fe3da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f561f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f561f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f561f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f561f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621fe36fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621fe36fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621fe3548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621fe003e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621fe003b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f561f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f561f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f561f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621fe003a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (3101 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d01eaceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560d01ea9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560d01ead62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0620649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06206a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0620649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0620631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d01e42bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560d01e42a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560d01e278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560d01ad6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560d01ad6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0620632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06206330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06206330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d01ad6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (3102 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565293804eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565293801e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056529380562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a6d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a6d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a6d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a6d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056529379abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056529379aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056529377f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056529342ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056529342eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3a6d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a6d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a6d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056529342ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (3103 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574685a5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005574685a2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005574685a662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc741333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc74138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc741333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc74131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055746853bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055746853ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005574685208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005574681cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005574681cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc74131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc74131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc74131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574681cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (3104 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056286a03beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056286a038e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056286a03c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1627849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16278a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1627849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1627831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562869fd1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562869fd1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562869fb68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562869c65e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562869c65b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1627832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16278330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16278330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562869c65a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (3105 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b4e36beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561b4e368e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561b4e36c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43e6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43e6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43e6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43e6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b4e301bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561b4e301a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561b4e2e68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561b4df95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561b4df95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f43e6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43e6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43e6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b4df95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (3106 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16 # | ... # `---data was truncated (10240/33616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563035660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056303565de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056303566162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e5ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e5caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e5ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e5ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630355f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005630355f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630355db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056303528ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056303528ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e5ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e5ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e5ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056303528aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (3107 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558659b71eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558659b6ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558659b7262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e7a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e7a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e7a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e7a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558659b07bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558659b07a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558659aec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055865979be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055865979bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5e7a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e7a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e7a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055865979ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (3108 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b449a88eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b449a85e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b449a8962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f60cef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60cef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f60cef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60cef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b449a1ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b449a1ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b449a038b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4496b2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4496b2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f60cef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60cef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60cef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4496b2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (3109 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/15203) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4a9867eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e4a9864e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e4a986862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0820849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08208a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0820849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0820831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4a97fdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e4a97fda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4a97e28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e4a9491e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e4a9491b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0820832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08208330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08208330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4a9491a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (3110 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/30759) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055576cfa5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055576cfa2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055576cfa662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f489e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f489e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f489e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f489e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055576cf3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055576cf3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055576cf208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055576cbcfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055576cbcfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f489e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f489e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f489e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055576cbcfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (3111 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ce09f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ce09f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ce09f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4459333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f445938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4459333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f445931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ce098bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ce098ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ce09708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ce061fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ce061fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f445931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f445931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f445931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ce061fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (3112 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056384a5a4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056384a5a1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056384a5a562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd5ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd5baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd5ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd5ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056384a53abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056384a53aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056384a51f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056384a1cee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056384a1ceb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdd5ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd5ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd5ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056384a1cea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (3113 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0) # | %2 = extractvalue { <8 x half>, <8 x half> } %1, 0 # | %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0 # | %4 = extractvalue { <8 x half>, <8 x half> } %1, 1 # | %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1 # | ret %struct.float16x8x2_t %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0) # | %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 # | %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0 # | %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 # | %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1 # | %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 # | %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2 # | %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3 # | %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3 # | ret %struct.uint8x16x4_t %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.uint32x4x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.uint32x4x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0 # | store [2 x <4 x i32>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0 # | %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.int8x16x4_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.int8x16x4_t, align 8 # | %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0 # | store [4 x <16 x i8>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false) # | %3 = load %struct.int8x16x4_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.int8x16x4_t %3, 0, 0 # | %5 = extractvalue %struct.int8x16x4_t %3, 0, 1 # | %6 = extractvalue %struct.int8x16x4_t %3, 0, 2 # | %7 = extractvalue %struct.int8x16x4_t %3, 0, 3 # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.float16x8x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.float16x8x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0 # | store [2 x <8 x half>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.float16x8x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.float16x8x2_t %3, 0, 0 # | %5 = extractvalue %struct.float16x8x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %values.addr = alloca ptr, align 4 # | %v = alloca %struct.uint16x8x2_t, align 8 # | %tmp = alloca %struct.uint16x8x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %values, ptr %values.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0) # | %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0 # | %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0 # | %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1 # | %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1 # | store %struct.uint16x8x2_t %5, ptr %tmp, align 8 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false) # | %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0 # | %6 = load <8 x i16>, ptr %arrayidx, align 8 # | %7 = load ptr, ptr %values.addr, align 4 # | %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0 # | store <8 x i16> %6, ptr %arrayidx1, align 8 # | %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1 # | %8 = load <8 x i16>, ptr %arrayidx3, align 8 # | %9 = load ptr, ptr %values.addr, align 4 # | %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1 # | store <8 x i16> %8, ptr %arrayidx4, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %ref.tmp = alloca %struct.int32x4x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0) # | %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0 # | %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1 # | %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1 # | store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8 # | %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0 # | %6 = load <4 x i32>, ptr %arrayidx, align 8 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055fe8e3eaeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fe8e3e7e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fe8e3eb62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eab333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eab38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eab333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eab31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe8e380bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fe8e380a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fe8e3658b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fe8e014e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fe8e014b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8eab31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eab31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eab31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe8e014a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (3114 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f08edd4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f08edd1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f08edd562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f08849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f088a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f08849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f08831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f08ed6abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f08ed6aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f08ed4f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f08e9fee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f08e9feb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4f08832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f088330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f088330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f08e9fea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (3115 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (3116 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (3117 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i # | ... # `---data was truncated (10240/51303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fceef94eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fceef91e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fceef9562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04fc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04fc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04fc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04fc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fceef2abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fceef2aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fceef0f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fceebbee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fceebbeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f04fc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04fc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04fc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fceebbea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (3118 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644ca35aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005644ca357e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005644ca35b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08fb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644ca2f0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005644ca2f0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644ca2d58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644c9f84e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644c9f84b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f08fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644c9f84a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (3119 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbf3aefeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dbf3aece85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dbf3af062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76c4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76c4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76c4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76c4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbf3a85bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dbf3a85a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dbf3a6a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dbf3719e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dbf3719b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f76c4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76c4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76c4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbf3719a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (3120 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (3121 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (3122 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056114c0f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056114c0f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056114c0f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63e1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63e16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63e1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63e1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056114c08bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056114c08ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056114c0708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056114bd1fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056114bd1fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f63e1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63e16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63e16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056114bd1fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (3123 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624f20f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005624f20f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005624f20f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bb4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bb418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bb4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bb411b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624f208abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005624f208aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005624f206f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005624f1d1ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005624f1d1eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bb411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bb411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bb411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624f1d1ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (3124 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebcf994eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ebcf991e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ebcf99562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb67ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb67eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb67ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb67ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebcf92abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ebcf92aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ebcf90f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ebcf5bee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ebcf5beb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb67ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb67ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb67ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebcf5bea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (3125 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055808cf1aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055808cf17e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055808cf1b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e34049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e34049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e34031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055808ceb0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055808ceb0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055808ce958b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055808cb44e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055808cb44b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2e34032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e340330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055808cb44a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (3126 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbe4334eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbe4331e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbe433562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb992c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb992ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb992c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb992c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbe42cabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbe42caa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbe42af8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbe3f5ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbe3f5eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb992c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb992c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb992c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbe3f5ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/builtins-loongarch.c (3127 of 27910) ******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "loongarch32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 4, ptr %res, align 4 # | store volatile i32 5, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a25e3e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a25e3e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a25e3e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b71b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b71b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b71b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b71b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a25e37abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a25e37aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a25e35f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a25e00ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a25e00eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2b71b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b71b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b71b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a25e00ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (3128 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e4aa39eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559e4aa36e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559e4aa3a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b6af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b6af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b6af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b6af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e4a9cfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559e4a9cfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559e4a9b48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559e4a663e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559e4a663b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5b6af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b6af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b6af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e4a663a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (3129 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,10 # | ... # `---data was truncated (10240/48393) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563dd7106eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563dd7103e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563dd710762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f627aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f627aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f627aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f627aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563dd709cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563dd709ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563dd70818b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563dd6d30e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563dd6d30b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f627aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f627aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f627aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563dd6d30a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (3130 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (3131 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (3132 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (3133 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (3134 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630860cbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005630860c8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005630860cc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a03649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a036a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a03649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a03631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563086061bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563086061a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005630860468b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563085cf5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563085cf5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a03632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a036330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a036330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563085cf5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (3135 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557809b9beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557809b98e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557809b9c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34f2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34f20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34f2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34f2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557809b31bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557809b31a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557809b168b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005578097c5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005578097c5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f34f2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34f20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34f20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578097c5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (3136 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b8807ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558b88079e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558b8807d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc194705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc19475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc194705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1946ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b88012bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558b88012a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558b87ff78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558b87ca6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558b87ca6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc1946eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1946ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1946ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b87ca6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (3137 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f33c8a6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f33c8a3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f33c8a762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc267a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc267aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc267a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc267a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f33c83cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f33c83ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f33c8218b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f33c4d0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f33c4d0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc267a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc267a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc267a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f33c4d0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (3138 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (3139 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a2d20deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559a2d20ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559a2d20e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbdd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbdd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbdd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbdd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a2d1a3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559a2d1a3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559a2d1888b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a2ce37e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a2ce37b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbbdd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbdd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbdd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a2ce37a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (3140 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056355cdcceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056355cdc9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056355cdcd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d78933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d7898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d78933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d7891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056355cd62bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056355cd62a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056355cd478b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056355c9f6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056355c9f6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5d7891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d7891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d7891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056355c9f6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (3141 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557be26aeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557be26abe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557be26af62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2d431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557be2644bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557be2644a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557be26298b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557be22d8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557be22d8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff2d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2d431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557be22d8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (3142 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0a747aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e0a7477e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e0a747b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85cb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85cb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85cb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85cb831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0a7410bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e0a7410a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e0a73f58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e0a70a4e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e0a70a4b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f85cb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85cb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85cb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0a70a4a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (3143 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b18bf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560b18bf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560b18bf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb35e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb35e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb35e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb35e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b18b8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560b18b8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560b18b728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560b18821e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560b18821b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb35e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb35e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb35e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b18821a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (3144 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a15fee4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a15fee1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a15fee562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbabfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbabfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbabfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbabfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a15fe7abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a15fe7aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a15fe5f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a15fb0ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a15fb0eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fbabfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbabfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbabfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a15fb0ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (3145 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556dd893eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005556dd890e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005556dd89462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbdb705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbdb75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbdb705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbdb6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556dd829bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005556dd829a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005556dd80e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005556dd4bde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005556dd4bdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbdb6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbdb6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbdb6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556dd4bda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (3146 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/22367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055865ff98eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055865ff95e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055865ff9962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff10dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff10dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff10dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff10dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055865ff2ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055865ff2ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055865ff138b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055865fbc2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055865fbc2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff10dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff10dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff10dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055865fbc2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (3147 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e09724eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557e09721e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557e0972562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe587333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe58738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe587333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe58731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e096babbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557e096baa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557e0969f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557e0934ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557e0934eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe58731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe58731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe58731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e0934ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (3148 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599a2471eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599a246ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599a247262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c90449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c904a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c90449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c90431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599a2407bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599a2407a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599a23ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599a209be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599a209bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c90432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c904330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c904330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599a209ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (3149 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559730d37eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559730d34e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559730d3862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f540c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f540c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f540c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f540c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559730ccdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559730ccda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559730cb28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559730961e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559730961b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f540c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f540c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f540c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559730961a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (3150 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e791641eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e79163ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e79164262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f46c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f46ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f46c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f46c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7915d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e7915d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e7915bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e79126be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e79126bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f46c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f46c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f46c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e79126ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (3151 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (3152 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558de47d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558de47d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558de47d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab35333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab3538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab35333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab3531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558de476cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558de476ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558de47518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558de4400e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558de4400b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fab3531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab3531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab3531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558de4400a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (3153 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4dd905eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b4dd902e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b4dd90662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc817849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc817849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc817831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4dd89bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b4dd89ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b4dd8808b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b4dd52fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b4dd52fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc817832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4dd52fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (3154 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, a # | ... # `---data was truncated (10240/18875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565ced10eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565ced0de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565ced1162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10fc705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10fc75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10fc705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10fc6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565ceca6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565ceca6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565cec8b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565ce93ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565ce93ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f10fc6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10fc6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10fc6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565ce93aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (3155 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6615e4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6615e1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6615e562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f64c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f64c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f64c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f64c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a66157abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a66157aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a66155f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a66120ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a66120eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1f64c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f64c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f64c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a66120ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (3156 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eda7e29eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eda7e26e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eda7e2a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3027505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f302755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3027505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30274ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eda7dbfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eda7dbfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eda7da48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eda7a53e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eda7a53b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f30274eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30274ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30274ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eda7a53a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (3157 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565258a23eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000565258a20e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000565258a2462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f609d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f609d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f609d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f609d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652589b9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005652589b9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056525899e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056525864de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056525864db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f609d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f609d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f609d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056525864da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (3158 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (3159 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d90141eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557d9013ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557d9014262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c3ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c3caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c3ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c3ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d900d7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557d900d7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557d900bc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557d8fd6be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557d8fd6bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6c3ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c3ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c3ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d8fd6ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (3160 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = add <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fadd <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = add <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fadd <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055c1813e5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c1813e2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c1813e662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f601d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f601d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f601d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f601d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c18137bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c18137ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c1813608b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c18100fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c18100fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f601d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f601d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f601d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c18100fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (3161 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056171d257eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056171d254e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056171d25862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9530b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9530b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9530b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9530b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056171d1edbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056171d1eda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056171d1d28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056171ce81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056171ce81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9530b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9530b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9530b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056171ce81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (3162 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aa020beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559aa0208e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559aa020c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f453f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f453f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f453f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f453f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aa01a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559aa01a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559aa01868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559a9fe35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559a9fe35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f453f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f453f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f453f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a9fe35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (3163 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %ba # | ... # `---data was truncated (10240/24100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d281360eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d28135de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d28136162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7dda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2812f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d2812f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d2812db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d280f8ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d280f8ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb7dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7dda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d280f8aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (3164 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b25cdb6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b25cdb3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b25cdb762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f463a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f463a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f463a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b25cd4cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b25cd4ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b25cd318b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b25c9e0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b25c9e0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f463a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f463a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f463a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b25c9e0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (3165 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cc478deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558cc478ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558cc478e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd526b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd526b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd526b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd526b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cc4723bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558cc4723a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558cc47088b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558cc43b7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558cc43b7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd526b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd526b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd526b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cc43b7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (3166 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (3167 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c29f327eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c29f324e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c29f32862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f755b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f755b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f755b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f755b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c29f2bdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c29f2bda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c29f2a28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c29ef51e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c29ef51b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f755b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f755b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f755b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c29ef51a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (3168 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb3362deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fb3362ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fb3362e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f284fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f284fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f284fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f284fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb335c3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fb335c3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fb335a88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fb33257e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fb33257b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f284fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f284fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f284fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb33257a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (3169 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055be96adfeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055be96adce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055be96ae062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9941f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9941f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9941f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9941f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055be96a75bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055be96a75a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055be96a5a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055be96709e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055be96709b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9941f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9941f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9941f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055be96709a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (3170 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (3171 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8a19f0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b8a19ede85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b8a19f162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa69933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa6998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa69933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa6991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8a1986bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b8a1986a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b8a196b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b8a161ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b8a161ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa6991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa6991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa6991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8a161aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (3172 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c415c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557c415bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557c415c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eeb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eeb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eeb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eeb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c41556bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557c41556a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557c4153b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557c411eae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557c411eab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4eeb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eeb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eeb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c411eaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (3173 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/13593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d8c517eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559d8c514e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559d8c51862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec7e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec7e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec7e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec7e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d8c4adbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559d8c4ada06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559d8c4928b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559d8c141e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559d8c141b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fec7e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec7e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec7e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d8c141a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (3174 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/34589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055944140aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559441407e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055944140b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc147733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc14778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc147733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc14771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594413a0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005594413a0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005594413858b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559441034e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559441034b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc14771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc14771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc14771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559441034a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (3175 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %not = xor i64 %0, -1 # | %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c89de6beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c89de68e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c89de6c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb813449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8134a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb813449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb813431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c89de01bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c89de01a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c89dde68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c89da95e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c89da95b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb813432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8134330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8134330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c89da95a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (3176 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565e1cb8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005565e1cb5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005565e1cb962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ab7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ab7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ab7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ab7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565e1c4ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005565e1c4ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005565e1c338b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005565e18e2e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005565e18e2b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7ab7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ab7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ab7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565e18e2a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (3177 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562306259eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562306256e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056230625a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe12849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe128a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe12849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe12831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623061efbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005623061efa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005623061d48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562305e83e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562305e83b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efe12832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe128330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe128330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562305e83a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (3178 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (3179 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/54488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f781584eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f781581e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f78158562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3eef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3eef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3eef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3eef231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f78151abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f78151aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f7814ff8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f7811aee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f7811aeb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3eef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3eef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3eef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7811aea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (3180 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota # | ... # `---data was truncated (10240/94681) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643f743aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005643f7437e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005643f743b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9fb01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9fb0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9fb01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9fb003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643f73d0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005643f73d0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005643f73b58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005643f7064e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005643f7064b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb9fb004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9fb0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9fb0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643f7064a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (3181 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, al # | ... # `---data was truncated (10240/26756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056224a2c2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056224a2bfe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056224a2c362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056224a258bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056224a258a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056224a23d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562249eece46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562249eecb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff9b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562249eeca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (3182 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x half> # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x float> # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 { # | entry: # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 { # | entry: # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055c63ffabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c63ffa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c63ffac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28cd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28cd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28cd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28cd6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63ff41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c63ff41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c63ff268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c63fbd5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c63fbd5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f28cd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28cd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28cd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63fbd5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (3183 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (3184 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc9c7d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cc9c7d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cc9c7d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fbd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fbd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fbd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fbd831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc9c76ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cc9c76ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cc9c7538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cc9c402e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cc9c402b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6fbd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fbd8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fbd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc9c402a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (3185 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559809f7eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559809f7be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559809f7f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d7ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d7aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d7ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d7ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559809f14bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559809f14a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559809ef98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559809ba8e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559809ba8b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9d7ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d7ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d7ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559809ba8a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/sse.c (3186 of 27910) ******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fb022beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564fb0228e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564fb022c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecf1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecf1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecf1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecf1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fb01c1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564fb01c1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564fb01a68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564fafe55e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564fafe55b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fecf1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecf1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecf1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fafe55a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (3187 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561946d35eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561946d32e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561946d3662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccb6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccb6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccb6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccb6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561946ccbbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561946ccba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561946cb08b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056194695fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056194695fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fccb6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccb6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccb6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056194695fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (3188 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056533caeceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056533cae9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056533caed62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba28933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba2898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba28933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba2891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056533ca82bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056533ca82a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056533ca678b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056533c716e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056533c716b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fba2891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba2891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba2891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056533c716a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (3189 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620f5de9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620f5de6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620f5dea62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6562933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f656298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6562933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f656291b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620f5d7fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620f5d7fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620f5d648b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620f5a13e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620f5a13b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f656291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f656291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f656291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620f5a13a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (3190 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i3 # | ... # `---data was truncated (10240/57708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ae66d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558ae66d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558ae66d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90dd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90dd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90dd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90dd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ae666dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558ae666da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558ae66528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558ae6301e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558ae6301b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f90dd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90dd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90dd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ae6301a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (3191 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056188a722eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056188a71fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056188a72362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1faa249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1faa2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1faa249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1faa231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056188a6b8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056188a6b8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056188a69d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056188a34ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056188a34cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1faa232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1faa2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1faa2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056188a34ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (3192 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c147ad7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c147ad4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c147ad862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f714db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f714db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f714db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f714db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c147a6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c147a6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c147a528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c147701e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c147701b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f714db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f714db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f714db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c147701a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (3193 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3d1660eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a3d165de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a3d166162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb92733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb9278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb92733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb9271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3d15f6bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a3d15f6a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a3d15db8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a3d128ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a3d128ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffb9271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb9271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb9271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3d128aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (3194 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637cdd34eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005637cdd31e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005637cdd3562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4a1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637cdccabbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005637cdccaa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005637cdcaf8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005637cd95ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005637cd95eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa4a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4a1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637cd95ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (3195 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0b59f5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0b59f2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0b59f662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f884b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f884b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f884b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f884b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0b598bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f0b598ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f0b59708b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f0b561fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f0b561fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f884b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f884b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f884b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0b561fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (3196 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | s # | ... # `---data was truncated (10240/58326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056267bb96eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056267bb93e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056267bb9762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5fb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5fb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5fb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5fb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056267bb2cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056267bb2ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056267bb118b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056267b7c0e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056267b7c0b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe5fb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5fb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5fb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056267b7c0a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (3197 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/20090) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616a5fc7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616a5fc4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616a5fc862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5bf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5bf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5bf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5bf71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616a5f5dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005616a5f5da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616a5f428b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005616a5bf1e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005616a5bf1b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5bf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5bf71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5bf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616a5bf1a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (3198 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbd2aafeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fbd2aace85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fbd2ab062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0219049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02190a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0219049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0219031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbd2a45bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fbd2a45a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fbd2a2a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fbd26d9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fbd26d9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0219032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02190330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02190330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbd26d9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (3199 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (3200 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558681171eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055868116ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055868117262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6749649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67496a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6749649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6749631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558681107bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558681107a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005586810ec8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558680d9be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558680d9bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6749632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67496330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67496330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558680d9ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (3201 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (3202 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645702e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005645702dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005645702e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa512c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa512ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa512c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa512c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564570277bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564570277a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056457025c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056456ff0be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056456ff0bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa512c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa512c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa512c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056456ff0ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (3203 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfc0e57eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dfc0e54e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dfc0e5862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f134cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f134cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f134cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f134cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfc0dedbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dfc0deda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dfc0dd28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dfc0a81e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dfc0a81b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f134cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f134cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f134cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfc0a81a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (3204 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593f4a82eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005593f4a7fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005593f4a8362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4ca81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4ca8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4ca81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4ca803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593f4a18bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593f4a18a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593f49fd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005593f46ace46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005593f46acb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe4ca804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4ca8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4ca8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593f46aca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (3205 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | # | ... # `---data was truncated (10240/23061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e634511eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e63450ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e63451262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0160333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f016038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0160333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f016031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6344a7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e6344a7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e63448c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e63413be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e63413bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f016031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f016031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f016031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e63413ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (3206 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056472c515eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056472c512e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056472c51662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9e0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9e0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9e0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9e0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056472c4abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056472c4aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056472c4908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056472c13fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056472c13fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa9e0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9e0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9e0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056472c13fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (3207 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c07b80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559c07b7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559c07b8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1bd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1bd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1bd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1bd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c07b16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559c07b16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559c07afb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559c077aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559c077aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff1bd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1bd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1bd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c077aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (3208 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563870a33eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563870a30e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563870a3462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbac333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbac38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbac333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbac31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638709c9bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005638709c9a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005638709ae8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056387065de46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056387065db63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbac31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbac31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbac31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056387065da51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (3209 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (3210 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564439a7deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564439a7ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564439a7e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe359f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe359f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe359f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe359f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564439a13bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564439a13a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005644399f88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005644396a7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005644396a7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe359f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe359f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe359f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644396a7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (3211 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect # | ... # `---data was truncated (10240/32932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560004acdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560004acae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560004ace62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff784b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff784b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff784b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff784b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560004a63bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560004a63a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560004a488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005600046f7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005600046f7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff784b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff784b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff784b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600046f7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (3212 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (3213 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621cd3c0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005621cd3bde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005621cd3c162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffafa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffafa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffafa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffafa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621cd356bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005621cd356a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005621cd33b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005621ccfeae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005621ccfeab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffafa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffafa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffafa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621ccfeaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (3214 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dab090eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564dab08de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564dab09162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b8e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b8e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b8e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b8e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dab026bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564dab026a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564dab00b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564daacbae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564daacbab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4b8e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b8e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b8e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564daacbaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (3215 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055deed568eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055deed565e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055deed56962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1294449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1294449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1294431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055deed4febbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055deed4fea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055deed4e38b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055deed192e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055deed192b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1294432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12944330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055deed192a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (3216 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ca53cdeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559ca53cae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559ca53ce62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55e1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55e14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55e1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55e1431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ca5363bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559ca5363a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559ca53488b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559ca4ff7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559ca4ff7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f55e1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55e14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55e14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ca4ff7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (3217 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (3218 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560fe65ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005560fe659e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005560fe65d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb280049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2800a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb280049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb280031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560fe5f2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005560fe5f2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005560fe5d78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005560fe286e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005560fe286b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb280032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2800330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2800330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560fe286a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (3219 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb8e383eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055eb8e380e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055eb8e38462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cfd01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cfd0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cfd01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cfd003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb8e319bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055eb8e319a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055eb8e2fe8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055eb8dfade46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055eb8dfadb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0cfd004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cfd0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cfd0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb8dfada51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (3220 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da19d8feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055da19d8ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055da19d9062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb35f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb35f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb35f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb35f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da19d25bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055da19d25a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055da19d0a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055da199b9e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055da199b9b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb35f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb35f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb35f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da199b9a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (3221 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg # | ... # `---data was truncated (10240/20531) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c79cdceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564c79cd9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564c79cdd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effdc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effdc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effdc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effdc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c79c72bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564c79c72a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564c79c578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564c79906e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564c79906b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007effdc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effdc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effdc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c79906a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (3222 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557170c0eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000557170c0be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000557170c0f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa547305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa54735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa547305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5472ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557170ba4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557170ba4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000557170b898b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557170838e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557170838b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa5472eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5472ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5472ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557170838a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (3223 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a03b4aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561a03b47e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561a03b4b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff092933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff09298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff092933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff09291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a03ae0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561a03ae0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561a03ac58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561a03774e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561a03774b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff09291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff09291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff09291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a03774a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (3224 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ccab4ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555ccab49e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555ccab4d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc31905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc3195c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc31905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc318ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ccaae2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555ccaae2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555ccaac78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555cca776e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555cca776b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc318eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc318ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc318ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cca776a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (3225 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fba099deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055fba099ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055fba099e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbdfd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbdfd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbdfd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbdfd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fba0933bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055fba0933a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055fba09188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055fba05c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055fba05c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffbdfd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbdfd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbdfd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fba05c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (3226 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcd883eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055dcd883be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055dcd883f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f901e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f901e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f901e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f901e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcd87d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055dcd87d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055dcd87b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055dcd8468e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055dcd8468b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f901e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f901e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f901e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcd8468a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (3227 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae5daabeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ae5daa8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ae5daac62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa09533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa0958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa09533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa0951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae5da41bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ae5da41a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ae5da268b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ae5d6d5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ae5d6d5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ffa0951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa0951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa0951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae5d6d5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (3228 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofre # | ... # `---data was truncated (10240/183431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6de61feeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f6de61ce85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f6de62062b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1831933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1831933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6de5b5bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f6de5b5a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f6de59a8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f6de249e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f6de249b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f183191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6de249a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (3229 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581232dceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005581232d9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005581232dd62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c77133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c7718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c77133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c7711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558123272bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558123272a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005581232578b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558122f06e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558122f06b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1c7711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c7711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c7711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558122f06a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (3230 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640a2f89eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005640a2f86e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005640a2f8a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cf0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cf095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cf0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cf08ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640a2f1fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005640a2f1fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005640a2f048b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005640a2bb3e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005640a2bb3b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8cf08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cf08ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cf08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640a2bb3a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (3231 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (3232 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559661ad7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559661ad4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000559661ad862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6a7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6a7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6a7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6a7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559661a6dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000559661a6da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000559661a528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559661701e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559661701b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007ff6a7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6a7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6a7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559661701a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (3233 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vtdiscard() #0 { # | entry: # | call void @llvm.riscv.sf.vtdiscard() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtdiscard() #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abb7c1beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055abb7c18e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055abb7c1c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bcc249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bcc2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bcc249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bcc231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abb7bb1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055abb7bb1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055abb7b968b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055abb7845e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055abb7845b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6bcc232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bcc2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bcc2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abb7845a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (3234 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , float, i64) # | ... # `---data was truncated (10240/34765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616636d9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005616636d6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005616636da62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e82b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e82b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e82b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e82b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056166366fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056166366fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005616636548b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561663303e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561663303b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9e82b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e82b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e82b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561663303a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (3235 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055879512ceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558795129e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055879512d62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7c4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7c42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7c4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7c4231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587950c2bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005587950c2a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005587950a78b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558794d56e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558794d56b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc7c4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7c42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7c42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558794d56a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (3236 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4e9a80eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c4e9a7de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c4e9a8162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62fe01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62fe0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62fe01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62fe003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4e9a16bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c4e9a16a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c4e99fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c4e96aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c4e96aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62fe004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62fe0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62fe0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4e96aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (3237 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7898aceeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055b7898a9e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055b7898ad62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d8a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d8a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d8a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d8a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b789842bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055b789842a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055b7898278b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055b7894d6e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055b7894d6b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3d8a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d8a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d8a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7894d6a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (3238 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (3239 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 # | ... # `---data was truncated (10240/73182) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055703bca5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055703bca2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055703bca662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9da9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9da978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9da9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9da971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055703bc3bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055703bc3ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055703bc208b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055703b8cfe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055703b8cfb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f9da971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9da971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9da971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055703b8cfa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (3240 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653af4f2eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005653af4efe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005653af4f362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb3401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb340725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb3401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb34003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653af488bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005653af488a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005653af46d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005653af11ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005653af11cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fdb34004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb340050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb340050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653af11ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (3241 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (3242 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6d8092eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a6d808fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a6d809362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6784533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f678458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6784533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f678451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6d8028bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a6d8028a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a6d800d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a6d7cbce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a6d7cbcb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f678451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f678451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f678451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6d7cbca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (3243 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056000e7a3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056000e7a0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056000e7a462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe44d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe44d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe44d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe44d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056000e739bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056000e739a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056000e71e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056000e3cde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056000e3cdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe44d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe44d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe44d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056000e3cda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (3244 of 27910) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 # | ... # `---data was truncated (10240/11881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c4091deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562c4091ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562c4091e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d8fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d8fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d8fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d8fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c408b3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562c408b3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562c408988b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562c40547e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562c40547b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2d8fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d8fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d8fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c40547a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (3245 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561047ff8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561047ff5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561047ff962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03fb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03fb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03fb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03fb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561047f8ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561047f8ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561047f738b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561047c22e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561047c22b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f03fb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03fb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03fb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561047c22a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (3246 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055673ec27eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055673ec24e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055673ec2862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf7505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf7505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf74ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055673ebbdbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055673ebbda06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055673eba28b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055673e851e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055673e851b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febf74eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf74ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf74ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055673e851a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (3247 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (3248 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570c994deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005570c994ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005570c994e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f604761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60476725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f604761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6047603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570c98e3bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005570c98e3a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005570c98c88b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005570c9577e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005570c9577b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6047604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60476050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60476050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570c9577a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (3249 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557514302eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005575142ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055751430362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13cfe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13cfe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13cfe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13cfe03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557514298bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000557514298a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055751427d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000557513f2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000557513f2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f13cfe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13cfe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13cfe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557513f2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (3250 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563afd262eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000563afd25fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000563afd26362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0090333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f009038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0090333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f009031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563afd1f8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000563afd1f8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000563afd1dd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000563afce8ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000563afce8cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f009031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f009031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f009031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563afce8ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (3251 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559fbd61eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005559fbd5ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005559fbd6262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8203d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8203d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8203d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8203d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559fbcf7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005559fbcf7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005559fbcdc8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005559fb98be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005559fb98bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8203d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8203d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8203d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559fb98ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (3252 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558243cf7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000558243cf4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000558243cf862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6ab533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6ab58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6ab533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6ab51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558243c8dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000558243c8da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000558243c728b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000558243921e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000558243921b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc6ab51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6ab51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6ab51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558243921a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (3253 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5fc515eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c5fc512e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c5fc51662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc780449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7804a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc780449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc780431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5fc4abbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c5fc4aba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c5fc4908b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c5fc13fe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c5fc13fb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc780432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7804330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7804330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5fc13fa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (3254 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561308abbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561308ab8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561308abc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35abf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35abf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35abf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35abf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561308a51bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561308a51a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561308a368b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005613086e5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005613086e5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f35abf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35abf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35abf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613086e5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (3255 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (3256 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (3257 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c93c62eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000561c93c5fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000561c93c6362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfe7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfe7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfe7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfe7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c93bf8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000561c93bf8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000561c93bdd8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000561c9388ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000561c9388cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfe7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfe7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfe7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c9388ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (3258 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b1a87beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562b1a878e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562b1a87c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd95a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd95a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd95a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd95a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b1a811bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562b1a811a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562b1a7f68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562b1a4a5e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562b1a4a5b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fd95a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd95a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd95a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b1a4a5a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (3259 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (3260 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ae0f26eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564ae0f23e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564ae0f2762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65f7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65f7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65f7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65f7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ae0ebcbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564ae0ebca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564ae0ea18b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000564ae0b50e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000564ae0b50b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f65f7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65f7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65f7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ae0b50a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (3261 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (3262 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, al # | ... # `---data was truncated (10240/30013) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0547e1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055f0547dee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055f0547e262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda75d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda75d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda75d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda75d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f054777bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055f054777a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055f05475c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055f05440be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055f05440bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fda75d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda75d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda75d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f05440ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (3263 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c57e07eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555c57e04e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555c57e0862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2855649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28556a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2855649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2855631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c57d9dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555c57d9da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555c57d828b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555c57a31e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555c57a31b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f2855632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28556330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28556330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c57a31a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (3264 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7bbc49eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d7bbc46e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d7bbc4a62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac1f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac1f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac1f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac1f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7bbbdfbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d7bbbdfa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d7bbbc48b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d7bb873e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d7bb873b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fac1f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac1f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac1f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7bb873a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (3265 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e482670eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e48266de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e48267162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5498d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5498d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5498d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5498d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e482606bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e482606a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e4825eb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e48229ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e48229ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f5498d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5498d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5498d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e48229aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3266 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e979d6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562e979d3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562e979d762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd04d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd04d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd04d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd04d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e9796cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562e9796ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562e979518b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562e97600e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562e97600b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcd04d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd04d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd04d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e97600a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (3267 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c628b00eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c628afde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c628b0162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca2b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca2b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca2b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca2b4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c628a96bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c628a96a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c628a7b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c62872ae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c62872ab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fca2b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca2b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca2b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c62872aa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (3268 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (3269 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %b # | ... # `---data was truncated (10240/38307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056511c8d7eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000056511c8d4e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000056511c8d862b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfdab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfdab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfdab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfdab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056511c86dbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000056511c86da06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000056511c8528b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000056511c501e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000056511c501b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fcfdab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfdab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfdab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056511c501a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (3270 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3 # | ... # `---data was truncated (10240/14330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec7c0d8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055ec7c0d5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055ec7c0d962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c0731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec7c06ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055ec7c06ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055ec7c0538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055ec7bd02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055ec7bd02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8c0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c0731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec7bd02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (3271 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648f24d5eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005648f24d2e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005648f24d662b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40e0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40e078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40e0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40e071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648f246bbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005648f246ba06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005648f24508b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005648f20ffe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005648f20ffb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f40e071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40e071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40e071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648f20ffa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (3272 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/13581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a441d5beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a441d58e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a441d5c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa34ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa34ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa34ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa34ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a441cf1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a441cf1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a441cd68b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a441985e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a441985b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fa34ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa34ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa34ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a441985a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (3273 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555850edbeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000555850ed8e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000555850edc62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8c4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8c4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8c4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8c4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555850e71bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000555850e71a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000555850e568b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000555850b05e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000555850b05b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc8c4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8c4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8c4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555850b05a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (3274 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (3275 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | ... # `---data was truncated (10240/12457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557ef5deeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005557ef5dbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005557ef5df62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9cf649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9cf6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9cf649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9cf631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557ef574bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005557ef574a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005557ef5598b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005557ef208e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005557ef208b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fc9cf632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9cf6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9cf6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557ef208a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (3276 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f0680beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560f06808e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560f0680c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ed5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ed5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ed5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ed5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f067a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560f067a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560f067868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560f06435e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560f06435b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ed5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ed5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ed5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f06435a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (3277 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c79d46eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055c79d46be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055c79d46f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8813d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8813d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8813d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8813d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c79d404bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055c79d404a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055c79d3e98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055c79d098e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055c79d098b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8813d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8813d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8813d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c79d098a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (3278 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564515db4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000564515db1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000564515db562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8508049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8508049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8508031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564515d4abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000564515d4aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000564515d2f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005645159dee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005645159deb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8508032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85080330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645159dea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (3279 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d70c1f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d70c1f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d70c1fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3867b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3867b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3867b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3867b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d70c18fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d70c18fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d70c1748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d70be23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d70be23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f3867b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3867b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3867b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d70be23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (3280 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599ff302eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005599ff2ffe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005599ff30362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febc2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febc22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febc2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febc2231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599ff298bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005599ff298a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005599ff27d8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005599fef2ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005599fef2cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febc2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febc22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febc22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599fef2ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3281 of 27910) ******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-none-elf" # | # | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any # | # | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any # | # | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any # | # | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10 # | ret i32 %2 # | } # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{i32 1, !5} # | !5 = !{!"aarch64.mem_hint", i32 0} # | !6 = !{i32 1, !7} # | !7 = !{!"aarch64.mem_hint", i32 1} # | !8 = !{i32 0, !9} # | !9 = !{!"aarch64.mem_hint", i32 3} # | !10 = !{i32 0, !11} # | !11 = !{!"aarch64.mem_hint", i32 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cedbff6eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055cedbff3e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055cedbff762b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb76ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb76eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb76ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb76ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cedbf8cbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055cedbf8ca06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055cedbf718b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055cedbc20e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055cedbc20b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fb76ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb76ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb76ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cedbc20a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (3282 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055577eafeeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055577eafbe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055577eaff62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9a7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9a76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9a7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9a7631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055577ea94bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055577ea94a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055577ea798b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055577e728e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055577e728b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007fe9a7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9a76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9a76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055577e728a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (3283 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl. # | ... # `---data was truncated (10240/11504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556365480eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055636547de85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055636548162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ccc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ccc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ccc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ccc831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556365416bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556365416a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005563653fb8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005563650aae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005563650aab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4ccc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ccc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ccc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563650aaa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (3284 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620d153eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005620d153be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005620d153f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a02c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a02ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a02c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a02c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620d14d4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005620d14d4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005620d14b98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005620d1168e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005620d1168b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a02c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a02c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a02c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620d1168a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (3285 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d6a9d0eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000562d6a9cde85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000562d6a9d162b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39ed905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39ed95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39ed905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39ed8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d6a966bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000562d6a966a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000562d6a94b8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000562d6a5fae46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000562d6a5fab63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f39ed8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39ed8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39ed8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d6a5faa51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (3286 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559034931eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055903492ee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055903493262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f8ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f8cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f8ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f8ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590348c7bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005590348c7a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005590348ac8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055903455be46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055903455bb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f8f8ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f8ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f8ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055903455ba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (3287 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556200fd8eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000556200fd5e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000556200fd962b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a0cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a0cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556200f6ebbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000556200f6ea06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000556200f538b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000556200c02e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000556200c02b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f0a0cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556200c02a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (3288 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2a824eeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e2a824be85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e2a824f62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6557a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6557aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6557a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6557a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2a81e4bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e2a81e4a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e2a81c98b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e2a7e78e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e2a7e78b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f6557a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6557a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6557a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2a7e78a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (3289 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ada4f4eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000560ada4f1e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x0000560ada4f562b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ef0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ef06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ef0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ef0631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ada48abbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x0000560ada48aa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x0000560ada46f8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000560ada11ee46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000560ada11eb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f1ef0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ef06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ef06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ada11ea51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (3290 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1545d3eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055a1545d0e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055a1545d462b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58cb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58cb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58cb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58cb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a154569bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055a154569a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055a15454e8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055a1541fde46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055a1541fdb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f58cb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58cb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58cb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1541fda51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (3291 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654e030beeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x00005654e0308e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x00005654e030c62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7aa4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7aa4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7aa4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7aa4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654e02a1bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005654e02a1a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005654e02868b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x00005654dff35e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x00005654dff35b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f7aa4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7aa4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7aa4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654dff35a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (3292 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb182d1eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055bb182cee85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055bb182d262b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a84a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a84aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a84a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a84a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb18267bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055bb18267a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055bb1824c8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055bb17efbe46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055bb17efbb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f4a84a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a84a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a84a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb17efba51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (3293 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5a2632eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055e5a262fe85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055e5a263362b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc37933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc3798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc37933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc3791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5a25c8bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055e5a25c8a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055e5a25ad8b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055e5a225ce46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055e5a225cb63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007efc3791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc3791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc3791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5a225ca51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (3294 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d40a2f9eeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055d40a2f6e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055d40a2fa62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf8b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf8b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf8b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf8b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d40a28fbbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055d40a28fa06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055d40a2748b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055d409f23e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055d409f23b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007febf8b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf8b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf8b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d409f23a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (3295 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055daf9d9deeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x000055daf9d9ae85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055daf9d9e62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62d5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62d52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62d5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62d5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055daf9d33bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x000055daf9d33a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x000055daf9d188b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x000055daf99c7e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x000055daf99c7b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f62d5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62d52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62d52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055daf99c7a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (3296 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (3609 of 27910) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055931474aeeb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a22eeb) # | #1 0x0000559314747e85 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a1fe85) # | #2 0x000055931474b62b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72b9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72b9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72b9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72b9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593146e0bbd llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8bbd) # | #8 0x00005593146e0a06 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8a06) # | #9 0x00005593146c58b9 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599d8b9) # | #10 0x0000559314374e46 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ce46) # | #11 0x0000559314374b63 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cb63) # | #12 0x00007f72b9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72b9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72b9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559314374a51 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ca51) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. ******************** Failed Tests (3297): Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c Clang :: CodeGen/2005-09-24-AsmUserPrefix.c Clang :: CodeGen/2008-07-17-no-emit-on-error.c Clang :: CodeGen/AArch64/atomic-hint-template.cpp Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c Clang :: CodeGen/AArch64/fp8-cast.c Clang :: CodeGen/AArch64/fp8-extract.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c Clang :: CodeGen/AArch64/neon-2velem.c Clang :: CodeGen/AArch64/neon-3v.c Clang :: CodeGen/AArch64/neon-dot-product.c Clang :: CodeGen/AArch64/neon-extract.c Clang :: CodeGen/AArch64/neon-fma.c Clang :: CodeGen/AArch64/neon-fp16fml.c Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/neon-intrinsics.c Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c Clang :: CodeGen/AArch64/neon-misc-constrained.c Clang :: CodeGen/AArch64/neon-misc.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c Clang :: CodeGen/AArch64/neon-shifts.c Clang :: CodeGen/AArch64/neon-tbl.c Clang :: CodeGen/AArch64/neon-vcmla.c Clang :: CodeGen/AArch64/neon-vcombine.c Clang :: CodeGen/AArch64/neon-vget-hilo.c Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c Clang :: CodeGen/AArch64/neon/add.c Clang :: CodeGen/AArch64/neon/bf16-getset.c Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c Clang :: CodeGen/AArch64/neon/f16-getset.c Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiply.c Clang :: CodeGen/AArch64/neon/getset.c Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c Clang :: CodeGen/AArch64/neon/intrinsics.c Clang :: CodeGen/AArch64/neon/load.c Clang :: CodeGen/AArch64/neon/perm.c Clang :: CodeGen/AArch64/neon/rounding-v8.5.c Clang :: CodeGen/AArch64/neon/rounding.c Clang :: CodeGen/AArch64/neon/store.c Clang :: CodeGen/AArch64/neon/subtraction.c Clang :: CodeGen/AArch64/neon/vpaddl.c Clang :: CodeGen/AArch64/neon/widen.c Clang :: CodeGen/AArch64/poly128.c Clang :: CodeGen/AArch64/poly64.c Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c Clang :: CodeGen/AArch64/sve-vector-arith-ops.c Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vector-compare-ops.c Clang :: CodeGen/AArch64/sve-vector-shift-ops.c Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c Clang :: CodeGen/AArch64/sve-vls-arith-ops.c Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vls-compare-ops.c Clang :: CodeGen/AArch64/sve-vls-shift-ops.c Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c Clang :: CodeGen/AArch64/sve/addv.c Clang :: CodeGen/AArch64/sve/andv.c Clang :: CodeGen/AArch64/sve/dup.c Clang :: CodeGen/AArch64/sve/eorv.c Clang :: CodeGen/AArch64/sve/len.c Clang :: CodeGen/AArch64/sve/maxnmv.c Clang :: CodeGen/AArch64/sve/maxv.c Clang :: CodeGen/AArch64/sve/minnmv.c Clang :: CodeGen/AArch64/sve/minv.c Clang :: CodeGen/AArch64/sve/nand.c Clang :: CodeGen/AArch64/sve/nor.c Clang :: CodeGen/AArch64/sve/orn.c Clang :: CodeGen/AArch64/sve/orv.c Clang :: CodeGen/AArch64/sve/pfalse.c Clang :: CodeGen/AArch64/sve/recpe.c Clang :: CodeGen/AArch64/sve/recps.c Clang :: CodeGen/AArch64/sve/rsqrte.c Clang :: CodeGen/AArch64/sve/rsqrts.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/builtin-cpu-is.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c Clang :: CodeGen/RISCV/riscv-xcvalu.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c Clang :: CodeGen/RISCV/rvp-intrinsics.c Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/SystemZ/zvector.c Clang :: CodeGen/WebAssembly/builtins-table-externref.c Clang :: CodeGen/WebAssembly/builtins-table-funcref.c Clang :: CodeGen/X86/avx-cmp-builtins.c Clang :: CodeGen/X86/avx-shuffle-builtins.c Clang :: CodeGen/X86/bfloat16-convert-half.c Clang :: CodeGen/X86/sse.c Clang :: CodeGen/aapcs-bitfield.c Clang :: CodeGen/arm-bf16-convert-intrinsics.c Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c Clang :: CodeGen/arm-bf16-params-returns.c Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c Clang :: CodeGen/arm-cde-gpr.c Clang :: CodeGen/arm-cde-reinterpret.c Clang :: CodeGen/arm-cde-vec.c Clang :: CodeGen/arm-cde-vfp.c Clang :: CodeGen/arm-crc32.c Clang :: CodeGen/arm-mfp8.c Clang :: CodeGen/arm-mve-intrinsics/absneg.c Clang :: CodeGen/arm-mve-intrinsics/admin.c Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c Clang :: CodeGen/arm-mve-intrinsics/compare.c Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp Clang :: CodeGen/arm-mve-intrinsics/dup.c Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c Clang :: CodeGen/arm-mve-intrinsics/idup.c Clang :: CodeGen/arm-mve-intrinsics/load-store.c Clang :: CodeGen/arm-mve-intrinsics/predicates.c Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c Clang :: CodeGen/arm-mve-intrinsics/ternary.c Clang :: CodeGen/arm-mve-intrinsics/vabavq.c Clang :: CodeGen/arm-mve-intrinsics/vabdq.c Clang :: CodeGen/arm-mve-intrinsics/vadc.c Clang :: CodeGen/arm-mve-intrinsics/vaddq.c Clang :: CodeGen/arm-mve-intrinsics/vaddv.c Clang :: CodeGen/arm-mve-intrinsics/vandq.c Clang :: CodeGen/arm-mve-intrinsics/vbicq.c Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vclz.c Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c Clang :: CodeGen/arm-mve-intrinsics/vcvt.c Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c Clang :: CodeGen/arm-mve-intrinsics/veorq.c Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c Clang :: CodeGen/arm-mve-intrinsics/vld24.c Clang :: CodeGen/arm-mve-intrinsics/vldr.c Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c Clang :: CodeGen/arm-mve-intrinsics/vminaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c Clang :: CodeGen/arm-mve-intrinsics/vminq.c Clang :: CodeGen/arm-mve-intrinsics/vminvq.c Clang :: CodeGen/arm-mve-intrinsics/vmldav.c Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c Clang :: CodeGen/arm-mve-intrinsics/vmovl.c Clang :: CodeGen/arm-mve-intrinsics/vmovn.c Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vmulq.c Clang :: CodeGen/arm-mve-intrinsics/vornq.c Clang :: CodeGen/arm-mve-intrinsics/vorrq.c Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c Clang :: CodeGen/arm-mve-intrinsics/vrev.c Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vrnd.c Clang :: CodeGen/arm-mve-intrinsics/vshlc.c Clang :: CodeGen/arm-mve-intrinsics/vsubq.c Clang :: CodeGen/arm-neon-directed-rounding-constrained.c Clang :: CodeGen/arm-neon-directed-rounding.c Clang :: CodeGen/arm-neon-dot-product.c Clang :: CodeGen/arm-neon-endianness.c Clang :: CodeGen/arm-neon-fma.c Clang :: CodeGen/arm-neon-numeric-maxmin.c Clang :: CodeGen/arm-neon-shifts.c Clang :: CodeGen/arm-neon-vcadd.c Clang :: CodeGen/arm-neon-vcvtX.c Clang :: CodeGen/arm-neon-vget.c Clang :: CodeGen/arm-neon-vld.c Clang :: CodeGen/arm-neon-vst.c Clang :: CodeGen/arm-poly-add.c Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c Clang :: CodeGen/arm-vector_type-params-returns.c Clang :: CodeGen/arm64-crc32.c Clang :: CodeGen/arm64-lanes.c Clang :: CodeGen/arm64_vcopy.c Clang :: CodeGen/arm64_vcreate.c Clang :: CodeGen/arm64_vdupq_n_f64.c Clang :: CodeGen/arm_acle.c Clang :: CodeGen/arm_acle_swp.c Clang :: CodeGen/arm_neon_intrinsics.c Clang :: CodeGen/attr-counted-by-issue200014.c Clang :: CodeGen/builtin-align.c Clang :: CodeGen/builtins-arm-exclusive.c Clang :: CodeGen/builtins-arm.c Clang :: CodeGen/builtins-arm64.c Clang :: CodeGen/builtins-loongarch.c Clang :: CodeGen/builtins-riscv.c Clang :: CodeGen/cx-complex-range-real.c Clang :: CodeGen/cx-complex-range.c Clang :: CodeGen/distributed-thin-lto/backend-skip.ll Clang :: CodeGen/distributed-thin-lto/basic.ll Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll Clang :: CodeGen/distributed-thin-lto/cfi.ll Clang :: CodeGen/distributed-thin-lto/newpm.ll Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll Clang :: CodeGen/linker-diagnostic.ll Clang :: CodeGen/memcmp-inline-builtin-to-asm.c Clang :: CodeGen/mozilla-ms-inline-asm.c Clang :: CodeGen/packed-structure.c Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll Clang :: CodeGen/thinlto-funcattr-prop.ll Clang :: CodeGen/thinlto-multi-module.ll Clang :: CodeGen/thinlto-opaque-typed-mix.ll Clang :: CodeGen/thinlto_backend.ll Clang :: CodeGen/thinlto_backend_local_name_conflict.ll Clang :: CodeGen/thinlto_embed_bitcode.ll Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp Clang :: CodeGenCXX/attr-musttail.cpp Clang :: CodeGenCXX/ctor-globalopt.cpp Clang :: CodeGenCXX/inline-then-fold-variadics.cpp Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll Clang :: CodeGenCXX/virtual-base-ctor.cpp Clang :: CodeGenCoroutines/coro-gro4.cpp Clang :: CodeGenCoroutines/pr65054.cpp Clang :: CodeGenHIP/offload-pgo-sections.hip Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl Clang :: Modules/pr93497.cppm Testing Time: 158.74s Total Discovered Tests: 55926 Skipped : 37 (0.07%) Unsupported : 1675 (3.00%) Passed : 50888 (90.99%) Expectedly Failed: 29 (0.05%) Failed : 3297 (5.90%) FAILED: gen/clang/test/run-lit python3 bin/llvm-lit -sv ../../clang/test ninja: build stopped: subcommand failed. Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.